DESIGN, FABRICATION AND CHARACTERISTICSOF THE N-WELL CMOS PROCESS.
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Authors Hsieh, Jaw-Haw.
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HSIEH, JAW-HAW
DESIGN, FABRICATION AND CHARACTERISTICS OF THE N-WELL CMOS PROCESS
THE UNIVERSITY OF ARIZONA M.S. 1983
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DESIGN, FABRICATION AND CHARACTERISTICS
OF THE N-WELL CMOS PROCESS
by
Jaw-Haw Hsieh
A Thesis Submitted to the Faculty of the
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
In Partial Fulfillment of the Requirements For the Degree of
MASTER OF SCIENCE
In the Graduate College
THE UNIVERSITY OF ARIZONA
19 8 3
STATEMENT BY AUTHOR
This thesis has been submitted in partial fulfillment of requirements for an advanced degree at The University of Arizona and is deposited in the University Library to be made available to borrowers under rules of the Library.
Brief quotations from this thesis are allowable without special permission, provided that accurate acknowledgment of source is made. Requests for permission for extended quotation from or reproduction of this manuscript in whole or in part may be granted by the head of the major department or the Dean of the Graduate College when in his judgment the proposed use of the material is in the interests of scholarship. In all other instances, however, permission must be obtained from the author.
SIGNED:
APPROVAL BY THESIS DIRECTOR
This thesis has been approved on the date shown below:
// /KhrfinJbu /7 tflTA J. H. HOHL Dati*
Adjunct Professor of Electrical and Computer
Engineering
To my wife
Hui-Tse Chen Hsieh
i$
• • • xxi
ACKNOWLEDGMENTS
I would like to express my cordial thanks to my
advisor, Dr. Jakob H. Hohl, and to Dr. James N. Fordemwalt,
Director of the Microelectronics Laboratory, for much advice
and instruction while working on my thesis. Also, I want to
thank Dr. Reginald Call for his academic advice. Especially
I would like to express my deepest gratitude to Mr. Ying
Zhao, Visiting Scholar from the People's Republic of China,
for his cooperation on this project and for the many valu
able suggestions for the process design and computer simula
tion. Also, I want to thank Mr. Leonard S. Raymond and Mr.
James A. Homoki for their technical assistance. Finally, I
want to thank Ms. Glenda Harvey for her preliminary typing.
Last but not least, I thank my wife for her constant encour
agement and moral support.
iv
TABLE OF CONTENTS
Page
LIST OF ILLUSTRATIONS vi-
LIST OF TABLES viii
ABSTRACT ix
CHAPTER
1. INTRODUCTION 1
2. MAIN FEATURES OF THE CMOS PROCESS 5
Fully Ion-Implanted 5 Local Oxidation of Silicon 6 Plasma Etching 8 Low-Pressure Chemical Vapor Deposition . . 9 Other Features 10
3. DETAILS OF THE CMOS PROCESS 12
Process and Simulation 12 Detailed Process Description 17
4. EVALUATION AND DISCUSSION OF RESULTS 43
Processing Experience 43 Process and Transistor Characteristics . . 44
Comparison Between SUPREM Results and Measured Parameters 44
I-V Characteristic Curves 48 Applicable Theory 50
General Preview 50 Threshold Voltage 51 Body Effect 59 Mobility 60 Channel-Length Modulation Parameter . 61
5. CONCLUSIONS 65
REFERENCES 69
v
LIST OF ILLUSTRATIONS
Figure Page
1-1 Dynamic (Domino) CMOS circuit 4
2-1. Thick recessed oxide outside of source, gate and drain region 7
3-1. N-well CMOS chip fabrication steps 15
3-2. Simulation of the n-well CMOS process (PMOS profile, cross-section A-A) 18
3-3. Simulation of the n-well CMOS process (PMOS profile, cross-section, B-B) 19
3-4. Simulation of the n-well CMOS process (NMOS profile, cross-section C-C) 20
3-5. Simulation of the n-well CMOS process (NMOS profile, cross-section D-D) 21
3-6. Starting wafer 22
3-7. Cross-section after first photolithography . . 23
3-8. Cross-section after silicon moat etching ... 25
3-9. Cross-section after local oxidation of silicon 27
3-10. Cross-section after oxide and nitride removal 28
3-11. Cross-section after second photolithography . 29
3-12. Cross-section after drive-in of n-well .... 30
3-13. Cross-section after gate oxide growth .... 33
3-14. Cross-section after polysilicon deposition . . 34
3-15. Cross-section after polysilicon etching ... 35
vi
vii
LIST OF ILLUSTRATIONS -- Continued
Figure Page
3-16. Cross-section after phosphorus implantation for source and drain 36
3-17. Cross-section after phosphosilicate glass deposition 39
3-18. Cross-section after aluminum etching and photoresist stripping 41
4-1. Cross-sectional view of the PMOS transistor of the n-well CMOS process, illustrating the design parameters 45
4-2. I-V curve for PMOS transistor 49
4-3. I-V curve for NMOS transistor 49
4-4. /I^g as a function of V^g for PMOS
transistor 56
4-5. /Ij-jg as a function of V^g for NMOS
transistor 57
4-6. NMOS transistor output characteristics, showing the early voltage 63
4-7. PMOS transistor output characteristics, showing the early voltage 64
5-1 I-V curve of PMOS transistor . 66
5-2 I-V curve of NMOS transistor 66
LIST OF TABLES
Table Page
4-1. Design considerations affecting n-well junction depth for the n-well CMOS structure 46
4-2. Comparison of SUPREM-generated and experimentally measured process parameters . . 47
viii
ABSTRACT
A new bulk CMOS (complementary metal-oxide-silicon)
technology, which is called n-well CMOS technology, will be
described in this thesis. The advantages of this technology
are the realization of high switching speed, high packing
density and lower power consumption in order to achieve high
performance in the circuit applications. Local oxidation on
silicon, low-pressure chemical vapor deposition, plasma
etching, and full ion-implantation were employed in this
process design.
Computer simulation of the process was used for the
process design. The experimental results of the process
parameters showed good agreement with the computer simulation
results.
ix
CHAPTER 1
INTRODUCTION
An n-well CMOS (complementary metal-oxide-silicon)
field-effect transistor process was designed for the Micro
electronics Laboratory of the University of Arizona and is
described in this thesis. During the past decade, as a
result of very aggressive device and feature miniaturization,
NMOS (n-channel metal-oxide-silicon) transistors have been
the leading technology. During the same period, in spite of
its well known low power requirements, CMOS technology has
been of lesser importance because of its lower speed, lower
density and higher cost. In the next decade, as the semi
conductor industry moves into the VLSI (very large-scale
integration) era, a given technology will be judged on both
its speed -power product and circuit density. Accordingly,
a n-well CMOS process was designed in order to combine the
advantages of both NMOS devices and CMOS devices. The advan
tages of an n-well CMOS process can be summarized as follows:
1. Within the limits of device scaling, n-channel
transistors exhibit a transconductance improvement
of about twice that of corresponding p-channel
transistors. In addition to the device-gain
1
2
advantage, the sheet resistance of an n+ diffusion
is typically half as large as that of a p+ diffusion.
The source and drain series resistance will be a
critical factor limiting the effective drive capa
bility of micrometer and submicrometer transistors.
Except for purely static complementary logic in a
clocked CMOS design, n-channel transistors will be
used more frequently to form logic elements to pro-
vice speed and density, while p-channel transistors
will serve mostly as efficient loads [1].
2. Because of the diffused n-well, a p-type substrate
may be used. By using a high resistivity substrate,
parasitic diffusion capacitances of the NMOS transis
tors are reduced in comparison with those of NMOS
transistors fabricated in p-wells, resulting in
higher switching speed [2].
3. The parasitic transistors in the n-well CMOS struc
ture are PNP transistors, which have a lower gain
than corresponding NPN transistors in a p-well CMOS
structure, thus reducing the probability of latch-up
[3].
4. The process is compatible with the conventional NMOS
process and uses the same substrate as the NMOS process
(p-type). This offers a manufacturing logistics
advantage if both CMOS and NMOS processes are to be
run on the same process line [4].
Many CMOS designs today contain more n-channel
devices than p-channel devices, because n-channel
transistors in logic elements provide higher speed
and density. Also, modern complex CMOS circuits are
designed with many n-channel transistors and fewer
p-channel transistors to avoid the area penalty of
static CMOS circuits and to take better advantage of
the lower power consumption of CMOS circuits. This
is demonstrated by the Domino CMOS circuit shown in
Figure 1-1. The n-well approach has an advantage
here, because optimum device characteristics are
required for the n-channel transistors, but not for
the p-channel devices [4]. Since the number of
p-channel transistors is reduced, the possibility of
forming p-n-p or n-p-n parasitic transistors can be
lowered to prevent latch-up [5]. Also, the number
of n-wells is reduced.
4
VDD °"
H&
-iC
i,
H[t Clock o-
f Hll!n J HUn
.J Hfr J
Output
- V ss
Figure 1-1. Dynamic (Domino) CMOS circuit.
CHAPTER 2
MAIN FEATURES OF THE CMOS PROCESS
The process described in this thesis was designed
using transistors with a minimum channel length of 4 ym.
Although this channel length is not very small, all the
techniques which are developed can also be applied to the
fabrication of transistors with very small channel lengths
in the micrometer or submicrometer range.
The following descriptions discuss the major advan
tages of this process.
Fully Ion-Implanted
The CMOS concept has added substantial flexibility
to MOS integrated circuits by combining n-channel and
p-channel devices on the same chip. In this process design,
ion-implantation was used exclusively because of the fol
lowing major advantages [6, 7]:
• It offers precise control over the number of impuri
ties introduced into the silicon.
• Impurities can be introduced predominantly below the
surface.
• Implanted junctions can be self-aligned to the mask
edge.
5
6
• It provides a flexibility not available with diffu
sion.
• An ion-implantation is used to tailor the threshold
voltage (which is defined as the gate-to-source
voltage required to achieve surface inversion and,
as a result, conduction between the drain and source
region).
In this n-well process design, four ion-implantations were
employed. They are: n-well implant; V ^ (channel threshold
voltage), and V ^ (field threshold voltage) adjustment; n+
drain and source formation; and p+ drain and source formation.
Local Oxidation of Silicon
A typical feature of the planar process is that the
pn-junction is not flat but rather curved near the window
edges. In many instances only the horizontal part of the
junction is essential; the other part causes an excess capaci
tance and a decreased breakdown voltage. Thus it is desir
able to reduce or eliminate completely the curved portion of
the junction. This may be accomplished by means of local
oxidation using silicon nitride as an oxidation mask. Sili
con nitride is oxidized only very slowly, and a film of the
material will protect silicon from oxidation. If the nitride
film contains a pattern of windows, the silicon will oxidize
only locally in the windows where the nitride is absent.
Hence the name "LOCOS" is used for the LOcal Oxidation of
Silicon. The resulting structure may be thought of as a
cross between junction isolation and dielectric isolation.
Dielectric isolation is of great interest for high-speed
digital circuits because of the reduced capacitance and the
smaller device geometry that is achieved by the oxide isola
tion [8]. Figure 2-1 shows a cross-section of the LOCOS
structure, illustrating how the thick oxide forms the borders
for the junction.
§
LOCOS
Figure 2-1. Thick recessed oxide outside of source, gate and drain regions.
For good high-frequency performance of the MOS
transistor, it is desirable to reduce the junction capaci
tance of the drain region. The LOCOS technology provides a
thick recessed oxide outside the source, drain and gate area,
which reduces the pn-junction area, and thus the junction
capacitance. This technique is employed in the n-well CMOS
technology as well as in the n-channel technology for the
same reasons.
8
Plasma Etching
Advances in silicon integrated circuit technology--
in particular recent developments in pattern generation--
place an increasing emphasis on good pattern transfer. The
transfer of these patterns into the underlying layers of the
devices requires a tightly controlled etching process. Wet
chemical etches have been the dominant techniques for pattern
transfer employed in microelectronic fabrication, but dry
processes such as plasma etching are becoming popular for
many applications. Wet etching of very fine patterns with
high precision is limited by the viscosity of the liquids and
mobility of the active radicals and reaction products in the
etch. Dry etching can be expected to overcome these short
comings. The plasma is created by passing reactant gases at
reduced pressure through an RF field at a frequency of 13.5
MHz [9].
To etch silicon and silicon nitride, fluorine-
containing gases are used, frequently CF^, commonly known as
Freon 14. CF^ is broken down into CF2, CF2, CF and F radicals
in the plasma. The F radical is thought to be the most
effective in etching silicon, while the others are the most
effective in etching the oxide and nitride. Usually oxygen
is added (typically 4%) to enhance the etch rate. In the
process designed here, plasma etching was used to etch the
nitride and silicon in the pattern used for LOCOS. The
9
etchant used in this process was CF^ with the addition of
4% oxygen (this combination is sold commercially under the
trademark PDE-100 by Matheson Division, Searle Medical Pro
ducts U.S.A., Inc., 30 Seaview Drive, Secaucus, New Jersey.
Low-Pressure Chemical Vapor Deposition
MOS integrated circuits are fabricated by systematic
formation and patterning of layer upon layer of dielectric
or interconnect materials. For reliability and high yield,
every layer should be perfectly uniform, with no included
defects, and should contain no unwanted contaminants. Until
recently the techniques used to deposit layers have involved
chemical vapor deposition at atmospheric pressure. However,
these processes have problems with control of uniformity and
avoidance of particulate formation.
The development of commercially available reactors
for chemically depositing the desired layers at much reduced
pressure, e.g., 0.5 Torr, has helped to overcome these prob
lems. This process is called low-pressure chemical vapor
deposition, or LPCVD for short.
Chemical vapor deposition processes are surface
reactions, and if the reaction rate at the optimum deposition
temperature is small compared to the mass transfer rate (the
rate at which gas can be pumped through the reactor tube),
then the deposition process will be uniform because the den
sities of active gaseous species are uniform; that is, the
10
active species are not significantly depleted along the
length of the tube.
LPCVD was used to deposit polycrystalline silicon in
this process. The pressure was set at 22.5 Torr with a
temperature of 700°C.
Other Features
1. Reduction of the gate overlap over source and drain
requires either very accurate mask alignment or some
type of self-aligned gate structure. The means of
achieving a self-aligned gate in an MOS structure is to
develop the gate before the drain and source are formed.
In the process described here the gate electrode consists
of LPCVD polycrystalline silicon. The gate is deposited
first and then the ion-implantation is used to form the
drain and source and to simultaneously dope the gate.
The polycrystalline silicon acts as a mask for the ion
implantation of the source and drain, as the gate is
thus "self-aligned." This keeps the overlap between gate
and drain or source to a minimum.
2. The polycrystalline silicon gate was designed for this
process also [10]. As is well known, the threshold volt
age, V h, is dependent on the work function, $mg- If we
use a polycrystalline silicon gate, its work function can
be adjusted such that the negative threshold voltage in
11
a p-channel device becomes more negative and that the
threshold voltage in an n-channel device is only
slightly less negative than that of a metal gate.
Silicon-gate structures are in wide use today for another
reason in addition to the threshold voltage modification:
the polycrystalline silicon can withstand high tempera
tures and allows a further oxide to be grown over the
silicon-gate by thermal oxidation or by chemical vapor
deposition.
CHAPTER 3
DETAILS OF THE CMOS PROCESS
Process and Simulation
In this thesis a silicon-gate n-well CMOS technology
and a process technique to realize gate lengths of 4 ym in
both NMOS and PMOS (p-channel metal-oxide-silicon) transis-
ors is described. The process sequence differs from that of
a standard silicon-gate CMOS process mainly by the use of an
n-well for PMOS transistors in a p-type substrate. The n+
silicon-gate n-well CMOS process presented is accomplished
utilizing eight photomasks. P-type silicon wafers with a
resistivity of 20 to 30 ft-cm and <100> orientation were used
in this process. Four ion-implantation steps were employed:
(1) a phosphorus implant for n-well formation; (2) a boron
implant for setting field threshold voltage and threshold
voltage of both NMOS and PMOS transistors; (3) a phosphorus
implant for the formation of the source and drain of the NMOS
transistors; and (4) a boron implant for the formation of the
source and drain of the PMOS transistors. Low-pressure
chemical vapor deposition and LOCOS were also employed in the
process. The n-well region was formed by implanting phos
phorus ions with an energy of 100 keV and with a dose of
12
13 12 -2
5 x 10 cm . The ion dose was chosen to achieve a sheet
resistance of 1000 £2/n for the n-well region. To make a
uniform well, a drive-in cycle in N£ gas was performed at
1200°C for 14 hours.
Before the processes were performed in the laboratory
they were simulated by using the SUPREM program (the Stan
ford University Process Engineering Models) [11]. This
program is a computer simulator capable of simulating most
typical IC (integrated circuit) fabrication steps. The pro
gram is designed so that these steps can be simulated either
individually or sequentially, just as they would occur during
the actual fabrication process. The output of the program,
available at the end of each step, consists of the one-
dimensional profiles of all the dopants present in the
silicon and silicon-dioxide materials. It is understood that
in sequential step simulation the output of a processing
step constitutes the initial conditions for the subsequent
step. The junction depths and sheet resistances of all n- or
p-layers formed during the process are also calculated.
The fabrication step simulation is based on several
process models. The models implemented in SUPREM consist of
ion implantation, chemical predeposition through the surface
Cgaseous or solid), oxidation or drive-in, epitaxial growth,
etching, and oxide deposition. Migration of impurities is
/
14
fully accounted for in any of the above models involving high
temperature.
The SUPREM program was applied to the n-well CMOS
process here, and the simulation profiles following the
fabrication steps are illustrated in Figure 3-1. The local
oxidation windows were defined first, and the resulting pro
file is shown in Figure 3-l(a). A cross-sectional view of
the device after n-well formation is shown in Figure 3-1 (b).
Due to the deep junction of the n-well (x^ = 7 ym), the
lateral diffusion width on both sides under the LOCOS was
wide enough to bridge together, because the width of LOCOS
was only about 3.5 ym and the lateral diffusion of each side
(0.77 Xj) was about 5.2 ym. The 80 nm gate oxidation and 400
nm polycrystalline silicon deposition are shown in Figure
3-1(c). The n+ and p+ regions are formed by sequentially
implanting phosphorus and boron ions at 100 keV to a dose of
3 x 1015 ions per square cm through the 80 nm oxide. Two
cross-sectional views of the device at this stage are shown
in Figures 3-l(d) and 3-l(e). A thick field oxide was then
deposited using the "Rotox" chemical vapor deposition (CVD)
system. Contact windows to the silicon were then opened
in the oxide and 800 nm of aluminum was deposited in a vacuum
system using a source heated by an electron-beam. The cross-
sectional view of this stage, following photolithographic
patterning of the aluminum, is shown in Figure 3-l(f).
Figure 3-1. N-well CMOS chip fabrication steps.
a. After local oxidation.
b. After n-well formation.
c. After gate oxide and polysilicon deposition.
d. After n+ implantation.
e. After p"1 implantation.
f. After PSG field oxide, contact window opening and metallization.
a. After local oxidation.
b. After n-well formation
olysilicon
c. After gate oxide and polysilicon deposition.
Figure 3-1.
16
O
d. After n+ implantation.
After p+ implantation.
metal
f. After PSG field oxide, contact window opening and metallization.
Figure 3-1. -- Continued
17
Figures 3-2 through 3-5 show the SUPREM-generated
impurity profiles for the n-well CMOS fabrication process
illustrated in Figure 3-l(e).
Detailed Process Description
The individual process procedures are given as
follows.
1. Raw Wafer: The raw materials used were silicon wafers
with <100> orientation covered with 30 nm SiC^ and 300
nm silicon nitride. Because the wafers were covered
with these two films, it was necessary to remove the
SigN^ and SiC^ layers on a test wafer utilizing proce
dures (3) and (4) below in order to measure the resis
tivity.
The resistivity measured on the test wafer was
29 ft-cm. The doping concentration corresponding to this
resistivity is 8 x 10^ cm~^ as determined from the curve
of resistivity versus impurity concentration. A cross-
section of the starting material is shown in Figure 3-6.
18
21
20
u 19
CO
I •p < to 18 o •J
S3
•S 17 +j rt n 4-> S3
8 16 S3 O o
15
14
oo C O
o°° o°r
H n-well
Qooc o ooo coo cc CO, oo.
p-Sub
-OC C O
_ L
° o°
—be——
•0.03 0.00 2.00 4.00 6.00 8,
(Depth ym)
00
Figure 3-2. Simulation of the profile of the PMOS transistor through cross-section A-A in Figure 3.1(e).
21
20
o 19 o CO e o < 18 bD
O iJ v c 17 o •rl 4J Cti U g 16 <u o
c o o
15
14
n-well- 4-p-sub
oooo_ o o ocooo
° O O C C C , cor
O r.oc< © C°"
o I o
-1.40 0.00 2.00 4.00 6.00 8.00
Depth (vim)
Figure 3-3. Simulation of the profile of the PMOS transistor through cross-section B-B in Figure 3.1(e).
21
o o
CO B o •U < bC O •J
§ •H 4-> CO U U
C <L> O G O U
20
19
18
17
16
15
14
,0"
n p-sub
O O O O O O O O O O O O O O O O C O O O O O O O O O O 0 0 0 0 0 0
-0.05 0.00 2.00 4.00 6.00 8.00
Depth (ym)
Figure 3-4. Simulation of the profile of the NMOS transistor through cross-section C-C in Figure 3.1(e).
21
20
19
18
o o CO E o 4J < bD O hJ
6 17 o •rH •w CO >-l c 16 <D a
C o a
15
14
p-sub
O O O O O O O O O O O O O O O O O O O O O O O C O O O O C
-0.03 0.00 2.00 4.00
Depth (ym)
6 . 0 0 8 . 0 0
Figure 3-5. Simulation of the profile of the NMOS transistor through cross-section D-D in Figure 3.1(e).
2:2
Si3N4 Si02
30 nm
p-substrate 29 ftcm <100>
Figure 3-6. Starting wafer.
First Photolithography for Isolation Moates: In this
step the pattern of the isolation moats was developed
for the subsequent growth of the local oxide (LOCOS).
Negative photoresist was used. The cross-section after
this procedure is shown in Figure 3-7.
Procedure:
Chemicals Step
Clean
Rinse
Spin dry
Prebake
Piranha solution
4; HoSO,. :H202 (4:1)
D.I. running water
N2
Blue M oven with N,
Apply HMDS HMDSjxylene (1:1)
Apply Waycoat 60 photoresist
Temperature
100°C + 10°C
25°C
25°C
135°C + 5°C
25°C
25°C
Time
5 min
15 min
3 min
25 min
6000 rpm
20 s 6000 rpm
Soft bake Using Blue M oven 85°C + 5°C 15 min
23
Procedure (Con't.):
Step
Expose
Chemicals Temperature Time
Using KASPER A-17 25°C aligner
6 s
Develop Xylene 20°C - 25°C 15 s
Postbake In Blue M oven with 130°C + 5°C 30 min
The concentration of the undiluted sulfuric acid for all
procedures is 95 to 98?0. HMDS is hexamethyldisilazane
and is supplied by KTI Corporation, 1170 Sonara Court,
Sunnyvale, California.
Photoresist
SiO 4
p-substrate
Figure 3-7. Cross-section after first photolithography.
Nitride Etching: The LFE PDS/PDE 301 barrel reactor
manufactured by LFE Company, 1601 Trapelo Road, Waltham,
MA 02254) was used for plasma etching of the nitride
exposed by the pattern developed in the previous step.
The gas used was PDE 100 . The following procedures
gave an etch rate of 20 nm/min for the Si^N^.
Procedure
RF Power Step
Pump down
RF power
Etch
150 W forward < 5 W reflected
150 W forward < 5 W reflected
Time Gas Pressure
30 min 0.02 Torr
1 Torr PDE 100
15 min 1 Torr PDE 100
Oxide Etching: Utilizing the procedure below, the sili
con dioxide in the nitride windows was etched by using
buffered HF. The ratio of NH^F to HF given below gives
an etch rate of 23 nm/min.
Procedure:
Chemical Temperature Time
NH4F:HF (10:1) 20 + 2°C
Step
Etch
Rinse
Blow dry
Bake
D.I. running water 25°C
N 25°C
In Blue M oven with 135 + 5°C N,
2 min
10 min
15 min
25
Silicon Moat Etching: The silicon was etched to form
the moat in which the oxide will be grown. The LFE PDE/
PDS-301 barrel reactor with PDE 100® etchant gas was used,
giving an etch rate of 24 nm/min. The depth of the moat
after etching was 900 nm. The cross-section after this
procedure is shown in Figure 3-8.
Procedure
Power Step
Pump down
RF power
Etch
Time
150 W forward < 5 W reflected
20 min
Gas Pressure
0.02 Torr
1 Torr PDE >100
1 Torr PDE 100
Photoresist
=q_Si3N4
—= SiOo
p-substrate
Figure 3-8. Cross-section after silicon moat etching.
Photoresist Strip: The photoresist is stripped before
the oxide is grown.
26
Procedure:
Step
Strip
Rinse
Spin dry
Chemical Temperature
H2S04:H202 (4:1) 110°C
D.I. running water 25°C
N, 25°C
Time
10 min
15 min
3 min
Local Oxidation of Silicon (LOCOS): Immediately before
the oxide was grown, the wafers were cleaned, following
the first three steps of procedure 2, in order to mini
mize the contamination.
Since the oxidation rate of the silicon nitride is
much less than that of silicon, we can use the silicon
nitride as a mask to grow the oxide in the unmasked area
to the desired thickness. The cross-section after this
procedure is shown in Figure 3-9.
Procedure:
Temperature Time Gas Flow Step
In tube entrance
Push
Oxide growth
Oxide growth
Oxide growth
Pull
1200°C
1200°C
1200°C
1200°C
1200°C
5 min
3 min
20 min
Dry 02,
3.2 1/min
Dry 02,
3.2 1/min
Dry 02,
3.2 1/min
120 min Wet 02,
3.2 1/min
10 min Dry 02,
3.2 1/min
3 min Dry 02,
3.2 1/min
27
Procedure (Con't.):
Step Temperature Time Gas Flow
Pull 1200°C 3 min Dry O2,
3.2 1/min
In tube entrance 5 min
The thickness was measured to be 800 + 50 nm
Wet O2 means 3 1/min of O2 bubbled through water at
95°C before it enters the furnace.
-LOCOS
SiO, \ \ \ s s s s \\\\\\\\\s s s ^ iWVwV " "
&
Si02
Si3N4
p-substrate
Figure 3-9. Cross-section after local oxidation of silicon.
8. Oxide-Nitride Removal: The undesired oxide which grew
on the nitride during the LOCOS process was etched away
by dipping in Hf (10:1) for 1 minute before the nitride
was removed. The cross-section after this procedure is
shown in Figure 3-10.
28
LOCOS
p-substrate
Figure 3-10. Cross-section after oxide and nitride removal.
Procedure
Step
Dip
Rinse
Spin dry
RF power
Etch
Chemicals Time
HF:H20 (1:10) 1 min
D.I. running 10 min water
N2 (25°C) 3 min
150 W forward < 5 W reflected
PDE-100 15 min
Gas Pressure
1 Torr PDE 100
1 Torr PDE 100
9. Second Photolithography for n-well Implant: In this
step the n-well pattern was defined following procedure 2,
10. Ion Implant to Form n-well: The phosphorus was implanted
through the windows which were opened in the photoresist
layer in the previous step. In this step the initial
oxide and the photoresist act as a mask to prevent the
29
ions from reaching the surface of the wafer except in
those areas where the n-well area is to be formed. A
12 2 dose of 5 x 10 phosphorus atoms/cm is implanted with
an energy of 100 keV. The cross-section after this step
is shown in Figure 3-11.
Photo- Phosphorus Ion Implantation resist
SiO
p-substrate
Figure 3-11. Cross-section after second photolithography.
11. Photoresist Strip: The process outlined in procedure 6
was followed.
12. Drive-In of n-well: Before putting wafers into the
furnace, the wafers were cleaned, following the first
three steps of procedure 2. Then the wafers were put
into the furnace for the drive-in process. The cross-
section after this step is shown in Figure 3-12.
30
Si02
Figure 3-12. Cross-section of n-well.
after drive-in
Procedure:
Step Temperature Time Gas Flow
In tube entrance 5 min N2, 5 1/min
Push 1200°C 3 min N2, 5 1/min
Drive-in 1200°C 14 h N2, 5 1/min
Pull 1200°C 3 min N2, 5 1 /min
Grooving and staining are sequential procedures to
measure the junction depth (Xj) [12]. The test wafer is
grooved and stained with the solution (4 drops of HNO^
in 25 ml HF). Then the wafer is put under the Reichert
microscope and the Watson Interferometer is used to
count the number of interference lines between the sur
face and the junction. By using this interference method,
the junction depth was measured to be 7 +0.5 ym. Also
the sheet resistance was measured to be 1000 fi/n by using
the four-point probe [13].
LOCOS
n-well
31
13. Third Photolithography for Ion Implant for V ^ Adjust
ment. Positive photoresist is applied in this step.
Procedure:
Chemicals Temperature Time
110°C
Step
Clean
Rinse
Spin dry
Prebake
H202:H2S04 (1:4)
D.I. running water 25°C
N, 25°C
Blue M oven with 135 + 5°C No
Apply photo- KTI (positive II) 25°C resist
Soft bake
Expose
Develop
Rinse
Spin dry
Oven 85 + 5 °C
Using Kasper A-17 25°C aligner
KTI positive developer
D.I. water
No
25°C
25°C
25°C
5 min
15 min
3 min
25 min
20 s 6000 rpm
15 min
12 s
30 s
10 min
3 min
14. Adjustment of Threshold Voltages: The threshold volt
age of the p- and n-channel transistors (Vtn and )
and the parasitic field transistors (V^) were adjusted
by this common implantation step. This is possible
because these three thresholds must be shifted to a more
positive value. By using the SUPREM program simulation,
the desired values of Vtn, Vt and can be determined.
The value of Vtn is IV, that of Vfc is -IV, and Vt£ is
32
10V. The threshold voltage adjustment was accomplished
12 utilizing a boron implantation. The dose was 1.3 x 10
- 2 cm at an energy of 90 keV.
15. Positive Photoresist Strip and Oxide Removal: The
photoresist and thin oxide were removed prior to the gate
oxide growth. Photoresist was stripped off using acetone
in an ultrasonic generator for 15 minutes. The oxide was
etched by following procedure 4 and etching for three
minutes.
16. Gate Oxide Growth: The gate oxide growth is the most
critical of all the processes. It is sensitive to con
tamination. Several runs of wafers produced no working
devices because of pinholes in the gate oxide resulting
from contamination. In order to reduce the contamination
to a minimum, the quartz furnace tube was cleaned and
flushed with HC1 gas for three hours before this process
was started. Before growing the gate oxide, the wafers
were cleaned again by using the normal cleaning proce
dures. Then the oxide was grown. The cross-section
after this procedure is shown in Figure 3-13.
33
Procedure:
Step
Tube cleaning
Tube entrance
Push
Oxide growth
Oxide growth
Anneal
Pull
Temperature
1000°C
1000°C
1000°C
1000°C
1000°C
1000°C
Time
3 h
5 min
1 min
Gas Flow
HCl, 0.096 1/min
Dry O2, 3.2 1/min
Dry O2, 3.2 1/min
40 min Dry O2, 3.2 1/min
60 min Dry 09, 3.2 1/min + HClf 0.196 1/min
30 min N2, 5 1/min
3 min
Thickness was measured to be 60 + 5 nm.
LOCOS
n-well
gate oxide
Figure 3-13. Cross-section after gate oxide growth.
17. Polycrystalline Silicon Deposition: In order to form
the polysilicon gate, a low-pressure chemical vapor
deposition (LPCVD) method was used to deposit the poly
silicon. The temperature was set to 700°C, as measured
34
by optical pyrometer and the pressure was 22.5 Torr.
Measurements showed a thickness' of 265 nm. This process
was implemented with Mr. Leonard Raymond's assistance.
Figure 3-14 shows the cross-section after this proce
dure .
polysilicon
gate oxide
n-well
Figure 3-14. Cross-section after polysilicon deposition.
18. Fourth Photolithography for Polysilicon Etching: The
process used was the same as procedure 13.
19. Polysilicon Etching: A wet etch, consisting of HF,
HNOg and l^O was used to etch the polysilicon into the
desired pattern. It was found that the ratio of the
components was quite critical. Several runs were lost
because the mixture was not of the correct ratio.
Because the etch rate of the polysilicon in this mixture
is about 800 nm/min, careful observation during etching
35
is necessary. The best ratio of solution is 15:15:1
of I^ChHNO^HF. The cross-section after photoresist
removal is shown in Figure 3-15.
Procedure:
Step
Etch
Rinse
Blow dry-
Strip
Rinse
Spin dry
Chemicals
H20:HN03:HF
(15:15:1)
D.I. running water
N,
H2S04:H202 (4:1)
Temperature
25°C
25°C
25 °C
110°C
D.I. running water 25°C
N,
polysilicon gate
25 °C
n-well
Time
30 s
10 min
10 min
15 min
3 min
LOCOS
gate oxide
Figure 3-15. Cross-section after polysilicon etching.
Fifth Photolithography for n+ Polysilicon Doping and
n+ Drain and Source Formation: Negative photoresist was
used, following the process outlined in procedure 2,
36
except the spin speed was changed to 4,000 rpm during
photoresist spin-on. This makes the film thicker so that
it can easily be stripped off after a heavy ion-implant
dose.
21. Polysilicon Doping and n+ Source and Drain Formation:
A phosphorus source was used for ion-implantation with
15 -2 a dose of 3 x 10 cm and an energy of 110 keV. The
cross-section of this procedure is shown in Figure 3-16.
photoresist phosphorus ion implantation
gate oxide
n-well
Figure 3-16. Cross-section after phosphorus implantation for source and drain.
22. Photoresist Stripping: Because the ion-implantation
lasts about 3 hours, the photoresist becomes acelated
due to the high-energy bombardment. Thus, the photo
resist was very difficult to remove using only the
piranha for stripping. Therefore, the wafers were put
into boiling piranha solution for 15 minutes, then were
37
scrubbed with a cotton pad containing trichloroethylene
(TCE).
23. Sixth Photolithography for p Source and Drain Forma
tion: The process outlined in procedure 2 was followed.
24. Formation of p+ Source and Drain: A source of boron was
IS - 2 used for this implantation with a dose of 3 x 10 J cm
and an energy of 100 keV.
25. Implant Anneal, Drive-in and Polysilicon Oxidation: Both
steps are implemented simultaneously. Because of the
ion-implantation, the silicon was left in a damaged con
dition and the implanted ions were not in substitutional
lattice sites. It was therefore necessary to anneal the
material to remove the crystal damage and activate the
implanted impurities. At the same time, the boron and
phosphorus ions which were implanted under the surface
are driven in deeper.
Procedure:
Step Temperature Time Gas Flow
Tube entrance 5 min Dry , 3.2 1/min
Push 1000°C 3 min Dry C>2, 3.2 1/min
Anneal 1000°C 20 min Dry 0£, 3.2 1/min
Pull 1000°C 3 min Dry O2, 3.2 1/min
38
The oxide thickness was measured to be 20 + 5 nm. The
sheet resistance of the polycrystalline silicon was meas
ured to be 200 fi/D. This value seems too high compared
with the specified value of 50 ft/n. One reason for this
is that the thickness of the polysilicon was only 265 nm,
in contrast to the design value of 470 nm. This increases
the expected sheet resistance to about 90 fi/n.
. Phosphosilicate Glass Deposition: In any MOS process
schedule, it is usual to include procedures to restrict
the motion of ionic charges. To this end, phosphosili
cate glass (PSG) was deposited as follows using a Silox
reactor. The resulting cross-section is shown in Figure
3-7.
Procedure
Step Temperature Time
5 min
Gas Flow
Preheat
Deposit undoped 420°C
Deposit doped 420°C 6.5 min N£ = 30 1/min
C>2 - 8.37 1/min
4% SiH4 in N£
= 3.88 1/min
1 min
100 ppm pHo in N2
= 3.88 1/min
39
n-well
PSG
gate oxide
Figure 3-17. Cross-section after phospho-silicate glass deposition.
27. Phosphosilicate Glass Densification: The layer of PSG
is densified in a high-temperature densification process
This was done at 900°C for 10 minutes.
Procedure:
Step Temperature Time Gas Flow
Push 900°C
Densification 900°C
Pull 900°C
1 min
10 min
1 min
Dry ©2, 3.2 1/min
Dry O2, 3.2 1/min
Dry O2, 3.2 1/min
28. Seventh Photolithography for Contact Holes: The process
outlined in procedure 2 was followed.
40
29. Contact Etching and Photoresist Stripping:
Procedure:
Chemicals STEP
Etch oxide
Rinse
Blow dry
Strip
Rinse
Blow dry
H20:HF (10:1)
D.I. running water
N2
H2S0,:H202 (4:1)
D.I. running water
No
Temperature
25°C
25°C
25°C
110°C
25°C
Time
10 min
15 min
10 min
15 min
30. Aluminum Deposition: An aluminum film with a thickness
of 1000 nm is deposited for the wiring pattern.
Procedure:
Step Chemicals (or set-up) Time Pressure
Clean HF:H20 (1:10)
D.I. running water
N,
Rinse
Blow dry
Pump-down Vacuum
Deposit E-beam
10 s
15 min
30 min 6 x 10"7 Torr
5 min 6 x 10"7 Torr
31. Eighth Photolithography for Metallization Definition:
The process outlined in procedure 2 was followed.
41
32. Aluminum Etching and Photoresist Stripping:
Procedure:
Step Chemicals Temperature Time
Etch HN03:H20:H3P04 (4:18:20) 70 + 5°C 10 min
Rinse D.I. running water 25°C 15 min
Blow dry N2
Strip KTI microstrip
Rinse D.I. running water
Blow dry
25°C
90 + 5°C 10 min
15 min
The cross-section after this procedure is shown in
Figure 3-18.
metal
SB
n-well
PSG
gate oxide
Figure 3-18. Cross-section after aluminum etching and photoresist stripping,
33. Metal alloying: In order to obtain low contact resis
tance, an alloying heat treatment is required after the
42
metal deposition. This is done at 450°C for 1.5 minutes
in an atmosphere of N2 with 10% H2.
CHAPTER 4
• EVALUATION AND DISCUSSION OF RESULTS
Processing Experience
This process was implemented based on the results of
simulations with the SUPREM program. The parameters of the
process steps were designed by using SUPREM for several
trials. For example, the dose of ion-implantation for
threshold voltage adjustment was adjusted until the results
of SUPREM showed almost the same magnitude of Vtn and Tt of
NMOS transistors and PMOS transistors, respectively.
Six runs of the process were made. Due to the lim
ited experience of the people doing the processing, much time
was lost with individual process steps, such as plasma
etching, ion-implantation, local oxidation and some special
chemical treatments. By the fifth run, the n-channel tran
sistors were working. However, all of the p-channel transis
tors failed. The problem was traced to unsuccessful ion-
implantation of p-channel drains and sources. More work was
done for this step. Unfortunately, during the n-channel
drain and source implantation the implanter broke down and
caused this step to fail. Finally, the sixth run produced
working p-channel transistors only.
43
44
Although the last two process runs produced either
working n-channel or p-channel transistors separately, it
can be inferred that the n-well CMOS process described in
Chapter 3 is feasible and can be carried out in the Micro
electronics Laboratory of the University of Arizona.
Process and Transistor Characteristics
Comparison Between SUPREM Results and Measured Parameters
The main design consideration (other than the value
of doping density N under the gate) is that the junction depth
of the n-well, x^ , must be deep enough such that for any
operating voltage the depletion layer under the drain does
not overlap the depletion region of the junction of the n-well.
The main design considerations are listed in Table 4-1.
Figure 4-1 shows the corresponding parameters described in
Table 4-1.
The process design followed that described by
Chwang and Yu [1]. The test structures consisted of NMOS and
PMOS transistors with 4 ym channel length (L) and 24 ym
channel with (W), an n diffusion resistor with the aspect
ratio L/W = 30 mil/2 mil and a doped polysilicon resistor
with the same surface geometry (30 mil/2 mil). Table 4-2
lists the comparisons of the parameters between the SUPREM
results and experimental measurements. The experimental
results are relatively close to the simulation results.
45
Figure 4-1. Cross-sectional view of the PMOS transistor of the n-well CMOS process, illustrating the design parameters.
46
Table 4-1. Design considerations affecting n-well junction depth for the n-well CMOS structure.
Parameter Comments
X q:Drain junction depth Must be deep enough to support VDD
Np.-Dopant concentration of n-well under gate
Surface concentration sets threshold voltage. The profile of affects Xq,
XD1, and X^
N^:Dopant concentration of wafer
Should be relatively light for NMOS and to facilitate a deep X^
Xn1:Depletion layer under drain
Function of and
: Depletion layer at junction of n-well
Function of N^, and Vgg
Xg0:Source junction depth Must be deep enough to support VDD
Xq:Depletion layer under gate
Function of ND and VDD
Xg-^: Depletion layer under source
Function of and
Xyp:The width of substrate (excluding the depletion layer)
Function of substrate bias <vss>
Table 4-2. Comparison of SUPREM-generated and experimentally measured process parameters.
Parameter SUPREM Measured
n-well junction depth 6.4 ym 7.0 ym
Sheet resistance of n-well 1379 Q / D 1200 n/n
Thickness of LOCOS 1000 nm 850 nm
Thickness of gate 72 nm 60 nm
Thickness of polysilicon 470 nm 265 nm
Sheet resistance of polysilicon 200 Q / a
n+ source and drain junction depth
0.97 ym 0.75 ym
p+ source and drain junction depth
0.87 ym 0.75 ym
Sheet resistance of n+ source and drain junction
30 Q / D 40 Q/•
Sheet resistance of p+ source and drain junction
39 n/n 49 fi/ •
Threshold voltage of NMOS transistor (Vtn)
0.72 V -0.7 V
Threshold voltage of PMOS transistor (Vt )
-0.87 V -0.2 V
Field threshold voltage (VTp) > 10 V
48
I-V Characteristic Curves
Due to the long implantation time for drains and
sources, only one wafer was completely processed and tested.
Ten devices which were close to the center of the wafer were
probed. A 1000 0, resistor was connected from the base term
inal to the emitter terminal of the Tektronix type 575 curve
tracer, in order to convert the base drive durrent to gate
drive voltage. The I-V characteristic curves of NMOS tran
sistors were measured by connecting the source to ground and
connecting the drain to the positive "collector" voltage
supply. Similarly, the I-V characteristic curves of PMOS
transistors were measured by connecting the source and n-well
to ground and supplying the negative "collector" voltage to
the drain. Figures 4-2 and 4-3 show the families of typical
measured 1jjs~^DS curves °f a p-channel and an n-channel tran
sistor, respectively.
Observing Figure 4-2, we see that the knees of the
curves are very sharp and that the spacing between curves
shrinks as the gate to source voltage (V^g) grows larger.
This is opposite to the predictions of the field effect
transistor theory.
Testing the p-n junctions between drain and well,
and between source and well of ten devices, showed junc
tions with normal diode characteristics. Also, the terminals
between gate and well were probed and show infinite resis-
v -+ DS
0 +
49
II --u-- --~!I- .. ____ .,~.-n'l!""'!ll ~ ...:·~11 n, .... - .... - "~
-r rJ
.. ,I ~
r ~'!!,
-~
Figure 4-2.
0
t 0
Figure 4-3.
=-= ""'
I :::::::::1 -- !!!!"'!
I
II
~ I. II !j.r II' n
.
~
--- I u I II
..... ., ;I
::::::11- -~-·· =
I ll I· ii ==~- !!!!!!!! ! IJ
i II n u; :
n Di'J!
m Iii, ~-- - II 1. _, J
+-0
iiiiiiiiiii
Horizontal 2 V/DIV
Vertical = 0.5 mA/DIV
Step = 1 V/Step
I-V curve for PMOS transistor.
v -+ DS
Horizontal = 5 V/DIV
. Vertical = 1 mA/DIV
Step = 1 V/Step
I-V curve for NMOS transistor.
50
tance. Based on these results, one would expect to have
normal MOS-field-effect transistors. However, the charac
teristic curves of Figure 4-2 are abnormal. The character
istics are most likely due to a short from the gate to the
substrate.
Observing Figure 4-3, we find that the knees of the
curves are smooth and consistent with typical NMOS transistor
Ips " Vj-jg curves. However, the bottom line of these curves,
which corresponds to Vgg = 0, is tilted. That means that
even for Vgg = 0 a fair amount of current is still flowing
from drain to source. Possible reasons for this will be
discussed in the Threshold Voltage section below.
Applicable Theory
Preview
In the fabrication of MOS devices, threshold voltage
is the most difficult parameter to control. It is very
process-dependent. Due to improper threshold voltage, the
circuits may not behave as originally designed. For example,
in the simple inverter in digital circuits, if the threshold
voltages of the load transistor (PMOS) and drive transistor
(NMOS) are not symmetrical with respect to zero, the voltage
swing would be reduced and at the same time the drive capa
bility would be lower.
Body effect and channel length modulation factors are
also involved in the considerations of circuit design in
51
order to optimize the circuit performance under diverse
conditions.
Threshold Voltage
Because threshold voltage is such an important para
meter, as described in the above section, it is worthwhile to
investigate it in more detail in this section. The following
theoretical calculation for an n-channel transistor follows
Hodges [14].
When a positive gate potential is applied, the holes
(in the p-substrate) are repelled and the surface is depleted.
With a further increase in gate potential, the surface con
centration changes from intrinsic to inversion, where the
surface becomes n-type. The onset of strong inversion is
defined by the condition <f>g = 2cp , where <j>g is the surface
electrostatic potential and <j>j,p is the equilibrium Fermi
potential of the p-type substrate. With further increasing
gate bias, the electron concentration at the surface in
creases while the potential difference across the depletion
region between the surface inversion layer and the semicon
ductor body remains equal to 2 <i>Fp. With no body bias, i.e.,
with Vgg (voltage between source and substrate) equal to
zero, the fixed negative charge in the depletion region
underneath the gate is at the onset of strong inversion
= 2<J)FP* Thus>
52
QbO = 'V 2c%esi |-2*Fpl
where
Qgo = depletion charge at Vgg = 0
q = charge of the proton
Na = doping density of the p-type substrate
eg = dielectric permitivity of the silicon
" <7r ) lnSI
n^ = intrinsic concentration of silicon
K = Boltzmann's constant
T = temperature in degree Kelvin
When Vgg f 0 (Vgg is normally positive for n-channel devices
and negative for p-channel devices), the depleted charge, Og,
is
% =/ Wsi l-^FP + VSB1 <4"2)
The value of gate voltage V^g (voltage between gate elec
trode and substrate) required to produce strong inversion,
called the threshold voltate V^, can be calculated. It
consists of several components [14]:
• A gate voltage term equal to -24>Fp - Qg/cox nee ed
to raise the surface potential to 2cf>p.
• A voltage term,c}>p, representing the difference in
work functions between the gate electrode and the
53
p-type substrate in the channel region must be
added.
• There is always positive oxide interface charge Q OX
This makes a negative contribution to the threshold
voltage by an amount -Q /C,„ . & J ox ox
Thus, for the threshold voltage, Vtn, of the n-channel tran
sistor, we have the equation,
Vtn - <*p - + <2*FP - <r-> <4"3> ox ox
Similarly, the threshold voltage, V. of the p-channel tran-up,
sistor is,
- \p - <*H " C25* + (2^N " IT* A ov r>-v
where ox ox
$p = the work function difference between gate elec
trode and p-substrate and is negative
= the work function difference between gate elec-N
trode and n-substrate and is negative except for
highly doped substrates (e.g., for aluminum and
20 silicon this work function is positive for 10 _ O
cm substrate doping)
<|>Fp = (-—)ln(^i) = the Fermi potential for p-A
substrates and is negative
54
N KT T ) ^FN = = t* i e irerm^- potential for n-
" i
substrates and is positive
C_„ = the gate capacitance per unit area OX
Thus p-channel transistors always have a negative
Vt and so will always be enhancement-mode devices. However,
for n-channel transistors the situation is not as clear
because whereas the first two terms in parentheses are always
negative as before, the last two terms are positive. Thus an
n-channel transistor can be enhancement (positive V ) or
depletion (negative Vtn) according to the relative magnitude
of the various quantities. It is possible to change $p and
modify Qg to predictably make an n-channel transistor either
operate as a depletion or enhancement mode device. An n-
channel transistor is slightly depletion mode with a Vtn *
-0.5 V because of the oxide interface charge, Q [15],
unless it is deliberately processed with an additional step
(e.g., ion-implantation) to increase Qg at the interface and
thus make Vtn positive.
The transistor threshold voltage can be obtained
experimentally from a transistor with a long and wide channel
operated in saturation, by using the square law dependence of
the drain current, Ipg, on the gate-source voltage, Vgg.
This current is given by the equation,
55
h» ' vCox<^l<VGS " Vth>2 • <4"5>
where
y = the mobility of the majority carriers
W = the width of the channel
L = the length of the channel
If we plot versus V^g, the threshold voltage
can be determined graphically. Figures 4-4 and 4-5 show the
relation between /I^g and Vgg of PMOS and NMOS transistors
at V^g equal to -10 V and 22 V, respectively. The intersec
tions of the extrapolated straight-line-fits of the data
with the horizontal axes are the threshold voltages. The
triangle points in Figures 4-4 and 4-5 are the magnitudes of
/Ijjg from Figures 4-2 and 4-3, mapped to corresponding gate-
source voltages.
From Figure 4-4, Vtp was determined to be -0.2 V.
It deviates considerably from the value of -0.9 V predicted
by the SUPREM simulation.
From Figure 4-5 we obtain -0.2 V for V • Thus, this
device is a depletion NMOS transistor. The reason for this
negative value is perhaps a large concentration of fixed
positive oxide charges [16] which shift the threshold volt
age (Vtn) to a more negative value. Another reason may be
that the dose of the ion-implantation of the threshold volt
age adjustment was not high enough.
~2*l/2
-1
GS
-1.0
Figure 4-4. /lDS as a function of VGg for PMOS transistor.
57
DS
-1 0 1 2 4 3 5 6 GS
Figure 4-5. ^ds as a function of V^g for NMOS transistor.
58
From Equations (4-3) and (4-4), we can calculate the
threshold voltage Vt and Vtn as follows. At room tempera
ture, with = 8 x 10"^ cm~^ and = 10^ cm~^, one obtains
<f>FN = 0.35V
and
<}>Fp = -0.28V
For a thickness of the gate oxide of 60 nm and with eQx =
3.9 e0> one obtains:
= 5. 80 x 10~8 F/cm2 ux
From Equation (4-1), the depletion charges for n-
channel transistors (QBqn an< or P-channel transistors
(Qgop) can be calculated:
^BON " 2< A£Si I ~2< FN I ) "
= -1.94 x 10"8 C/cm2
^BOP ~ (2qNDeSil "2(f)FP^ ^
= 6.10 x 10"8 C/cm2
The oxide interface charges depend on oxidation rate
and subsequent heat treatment, and also on crystal orienta
tion. For carefully treated Si-Si02 interfaces, typical sur-
10 2 face charge densities are about 2 x 10 charges/cm (i.e.,
Q = 2 x 10^® q) for <100> surfaces. Also, assuming the OX
channel length is equal to the polygate width, and $N
are typically -0.6V and 0V, which are based on the Fermi
potential difference from n+ doped polygate to p-type sub
strate and to n-well, respectively. From the above numerical
values, we can obtain
Vtn = (-°-60 " °-05) + ("0-56 - 0.33) = -1.03V
V = (0 - 0.05) + (0.70 - 1.05) = -0.40V
These calculations do not accurately predict actual
threshold voltages. Reasons for this include body doping
near the oxide interface; oxide thickness variations due to
process variations; and poor control of oxide charges.
Calculations of threshold voltage are most useful for pre
dicting relative changes of V.^ with doping and geometrical
parameters. In circuit design, statistical distributions are
often used.
Body Effect
From Equation (4-3),
Qox Vtn C ^ + (2t()FP " C ^
ox ox
. . • QB0 °OX % ' %0 = *p + 2 Fp - j, j J
OX ox ox
60
- Vton + y ( / | ^ fp|+ vSB -
(4-6)
where VtQn is the threshold voltage at VgB = 0
The coefficient y in Equation (4-6) is called the
body-effect coefficient or the body factor because it origin
ates from the effect of the additional voltage between source
and body. It is given by:
_ 1 ,o „ \1/2 Yn c (2clesiV
ox Similarly,
1 ( n n m 1/2 Yp c (2cl£siND^
ox
For the data of this process, the body factors for n- and
p-channel transistors are, respectively:
yN = 0.27 V1/2
yp = 0.98 V1/2
Mobility
The channel mobility, yc , is given by the relation
[17]:
®m
y°h V c A DS ox'L
is the transconductance which is defined as — . From GS
Figures 4-2 and 4-3, g^, gmn, were extracted for the PMOS tran
61
sistor with VGg between 5V and 6V at VDg equal to 8V and for
the NMOS transistor with VGS between 3V and 4V at VDg equal
to 3V. The results are:
"chn = 555 cm2/Vs
ychp = 186 cm2/Vs
Channel-Length Modulation Parameter
The drain-to-source current of an MOS transistor in
the saturated region is not completely independent of V^g
because the depletion layer of the drain junction widens as
Vjjg increases. As the drain voltage is increased, the chan
nel will pinch off and shorten the electrically effective
value of L. For a long channel length (> 10 ym), the distance
between pinch-off point and drain is not comparable to the
channel length and results in an insignificant increase in
the drain-source current. However, for a short channel
length, the distance between pinch-off and drain is compar
able to the channel length and results in a noticeable
increase in the drain-source current and the saturation
current in the I-V characteristic is noticeably dependent
on the channel length. This variation of the drain-source
saturation current in the short channel transistor can be
described by the channel length modulation parameter, A,
which is a function of the channel length (L). An empiri
62
cal approximation to the actual drain-source saturation
current is given by:
rD " <!><VGS " + AVDS>
To avoid discontinuities in the IDS - V^g characteristic,
the term (1 + V^g) may be included for both saturated and
linear regions with negligible error. Usually X has little
effect on the operating characteristics of digital MOS
circuits, but it is important for linear circuits. The value
of X can be calculated from the I-V characteristic curves.
The reciprocal value of X is the Early voltage, V^. Typical
values of X range from 0.01 V-1 to 0.2 V"^. From Figures 4-2
and 4-3 we determine V^ for PMOS and NMOS transistors, respec
tively, as:
X„ = = J* = -0.026 V"1 (NMOS) w AN ~JO
Xp = ^ = 0.023 V"1 (PMOS)
The I-V curves of NMOS and PMOS transistors are redrawn in
Figures 4-6 and 4-7 to illustrate the graphic determination
of the Early Voltage.
63
hs
Figure 4-6. NMOS transistor output characteristics, showing the Early voltage, V^.
Figure 4-7. PMOS transistor output characterist showing the Early voltage, V^.
CHAPTER 5
CONCLUSIONS
1. Both Figures 4-2 and 4-3 in Chapter 4 show atypical I-V
characteristic curves for field-effect transistors. The
curves of Figure 4-2 are, in fact, not PMOS transistor
I-V characteristics. This is attributed to processing
problems, particularly with ion implantation. A further
process run was performed recently by Mr. Ying Zhao using
a more modern implanter operating with 80 times higher
beam current to implant drain and source, but leaving all
the process steps the same. The resulting I-V character
istic curves of the PMOS transistor, which are shown in
Figure 5-1, are much more reasonable.
Although the curves displayed in Figure 4-3 are those
of a field effect transistor, the graphically determined
threshold voltage is by 1.4 V too negative. Potential
causes for this shift have been discussed in Chapter 4.
For this run, Mr. Zhao has increased the implant dose from
1.3 x 10"^ cm"^ to 2.0 x 10"^ cm"^. This resulted in a
shift of V^. of the NMOS transistor to a positive value tn
of 0.7 V, which suggests that the implant dose for the
transistors discussed in Chapter 4 may indeed have been
too low.
65
Figure 5-l.
0-+
+0
Horizontal = 2 V/DIV
Vertical = 0.5 mA/DIV
Step = -2V/Step
I-V curves for PMOS transistor (reproduced by permission of Mr. Ying Zhao).
Horizontal 2V/DIV
Vertical = 1 mA/DIV
Step = lV/Step
Figure 5-2. I-V curve for N110S transistor (reproduced by permission of Mr. Ying Zhao).
66
67
The I-V characteristic curves of an NMOS transistor of
Mr. Zhao's run are shown in Figure 5-2.
We conclude from Figures 5-1 and 5-2 that the process
design of n-well CMOS devices discussed in Chapter 3 is
feasible for the Microelectronics Laboratory of the
University of Arizona.
2. The proponents of the n-well approach, most notably Intel
and Matsushita, claim that the n-well process is the best
approach to a CMOS process because of its compatibility
with their existing NMOS processes. The ri-well CMOS
process uses approximately 20% more process steps than
does the NMOS process. However, many of these process
steps are identical. The two processes can be run on the
same process line with fewer perturbations than would be
required for a p-well CMOS process and an NMOS process,
although it is certainly feasible to run a p-well CMOS
process and an NMOS process on the same line. The n-well
process uses the same substrate as does the NMOS process,
namely p-type, while the p-well process uses an n-type
substrate. The common p-type substrate offers a logis
tics advantage, if both CMOS and NMOS process are run
on the same process line. It can also lead to lower
substrate material cost, due to higher volume purchasing
of the same substrate type.
68
Although several companies have built excellent n-
channel transistors in a p-well, it is also claimed that
the n-well approach naturally optimizes the n-channel
transistors. In addition, many CMOS designs today are
not truly complementary, because they contain more
n-channel devices than p-channel devices. The n-well
approach may have an advantage here, where optimum device
characteristics are required for the n-channel transis
tors but not for the p-channel devices.
Also, latch-up is a common problem in CMOS integrated
circuits and is defined as a state of high excess current
through the lateral or vertical pn junction. Latch-up
usually disrupts the functional capability of the inte
grated circuit and, in some cases, the excess currents
are large enough to cause permanent damage. In CMOS
integrated circuits latch-up is almost always due to
regenerative switching in a four-layer p-n-p-n path. If
fewer p-channel devices are used, the opportunity for
latch-up to occur should also be reduced, although this
problem may be solved by using epitaxial starting mater
ial or low-resistance material to reduce the voltage
drops to avoid initiating the current paths that lead to
latch-up [5].
REFERENCES
1. R. Chwang and K. Yu, "C-HMOS--An N-Well Bulk Technology for VLSI," VLSI Design, pp. 43-46, Fourth Quarter (1981).
2. 0. Takahashi, J. Yashi, T. Ishihara and S. Horiochi, "An 8K x 8 bit static MOS RAM Fabricated by N-MOS/' N-Well CMOS Technology," IEEE Journal of Solid-State Circuits, Vol. SL-15, No. 5, pp. 854-861 (1980).
3. R. L. Maddox, "Reverse CMOS Processing," Solid State Technology, pp. 128-131, February (1981).
4. M. R. Gulett, "The CMOS Technology," VLSI Design, pp. 51-52, Fourth Quarter (1981).
5. D. B. Estreich and R. W. Dutton, "Modeling Latch-Up in CMOS Integrated Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. CAD-1, No. October (1982).
6. T. Ohozene, H. Shimora, K. Tsuji and T. Hirao, "Silicon-Gate N-Well CMOS Process by Full Ion-Implantation Technology," IEEE Transactions on Electron Devices, Vol. ED-27, No. 9, pp. 1789-1795, September (1980).
7. G. Zimmer, B. Hoefflinger and J. Schneider, "A Fully Implanted NMOS, CMOS, Bipolar Technology for VLSI of Analog-Digital Systems," IEEE Transactions on Electron Devices, Vol. EE-26, No. 4, pp. 390-396, April (1979) .
8. J. A. Apples, E. Koor and M. M. Paffen, "Local Oxidation of Silicon and Its Application in Semiconductor Device Technology," Philips Res. Rev., 25, pp. 118-132 (1970).
9. N. K. Wang and D. Maydan, "Dry Etching Technology for Fine Line Devices," Solid State Technology, pp. 121-125, May (1981).
69
70
10. G. Zimmer, H. Fielder, B. Hoefflinger, E. Neubert and H. Vogt, "Performance of a Scaled Si Gate N-well CMOS Technology," Electronics Letters, Vol. 17, pp. 666-667, September (1981).
11. D. A. Antoniadis, S. E. Hansen and R. W. Ducton, "SUPREM II-A Program for IC Process Modeling and Simulation," Stanford University Department of Electrical Engineering (1978).
12. J. N. Fordemwalt, "Laboratory Manual for Integrated Circuit Technology," pp. II-1-II-4, University of Arizona, Department of Electrical Engineering (1981).
13. J. N. Fordemwalt, "Laboratory Manual for Integrated Circuit Technology," pp. II-8, University of Arizona, Department of Electrical Engineering (1981).
14. D. A. Hodges, "Analysis and Design of Digital Integrated Circuits," ppT 43-48, McGraw-Hill Book Company (1983),
15. M. J. Howes and D. V. Morgan, "Large Scale Integration," pp. 60-71, John Wiley and Sons (1981).
16. P. Richman, "MPS Field-Effect Transistors and Integrated Circuits," John Wiley and Sons (1973).
17. M. E. Motamedi and A. J. Steckl, "Design and Evaluation of Ion-Implanted CMOS Structures," IEEE Transactions on Electron Devices, Vol. ED-27, No" 3, March (1980).