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Penn ESE370 Fall 2014 -- Townley & DeHon
ESE370:Circuit-Level
Modeling, Design, and Optimization for Digital Systems
Day 14: October 1, 2014
Layout and AreaMidterm 1 Average: 79.7 (of 85) Std. Dev.: 4.4
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Problem 4 • Failure – my fault
– Should be: min(max(3*(Va-Vb),0),1)
• Failed to provide good diagnosis of restoration understanding– Noisy measurement
• Result– Exam not provide very high precision
assessment of students• Cannot distinguish A from B students
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Exam Successes (not fail)
• Does provide enough information to diagnose anyone ein big trouble and should drop – separate the DF from AB
• Diagnose a few R C items– Need that down cold will use heavily
• Did focus you on understanding these items, including restoration
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Today
• Layout– Transistors– Gates
• Design rules
• Standard cells
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Layout
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Transistor
Side view
Perspective view
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Layout
• Sizing & positioning of transistors
• Designer controls W,L
• tox fixed for process– Sometimes
thick/thin oxide “flavors”
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NMOS Geometry
Top view Perspective view
L
W
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NMOS Geometry
Top view
L
W
• Color scheme– Red: gate– Green: source and drain
areas (n type diffusion)S DG
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NMOS vs PMOS
Rabaey text, Fig 2.1Penn ESE370 Fall 2014 -- Townley & DeHon
• NMOS built on p substrate
• PMOS built on n substrate– Needs an N-well
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PMOS Geometry
n well
L
W
• Color scheme– Red: gate– Orange: source and drain
areas (p type)– Green: n well
• NMOS built on p wafer– Must add n material to
build PMOS
S DG
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Body Contact
• “Fourth terminal”• Needed to set
voltage around device– PMOS: Vb = Vdd
– NMOS: Vb = GND
• At right: PMOS (orange) with body contact (dark green)
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Body Contact
• Needed to set voltage around device– PMOS: Vb = Vdd
– NMOS: Vb = GND
• What happens if NMOS body contact is Vdd?
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Body Contact
• Needed to set voltage around device– PMOS: Vb = Vdd
– NMOS: Vb = GND
• What happens if NMOS body contact is Vdd?– Polarity of field wrong– Won’t invert channel
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Body Contact
• Needed to set voltage around device– PMOS: Vb = Vdd
– NMOS: Vb = GND
• Always to same supply as the transistor might be connected in CMOS
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Penn ESE370 Fall 2014 -- Townley & DeHon
Rotate All butPMOS Transistor90 degrees
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Interconnect• Connect transistors
– Different layers of metal• “Contact” - metal to transistor• “Via” - metal to metal
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Interconnect• Connect transistors
– Different layers of metal• “Contact” - metal to transistor• “Via” - metal to metal
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Interconnect Cross Section
ITRS 2007Penn ESE370 Fall 2014 -- Townley & DeHon
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Masks
• Define areas want to see in layer– Think of “stencil” for material deposition
• Use photoresist (PR) to form the “stencil”– Expose PR through mask– PR dissolves in exposed area– Material is deposited
• Only “sticks” in area w/ dissolved PR
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Masking Process
• Goal: draw a shape on the substrate– Simplest example: draw a rectangle
Silicon wafer
Mask
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Masking Process
• First: deposit photoresist
photoresist
Mask
Silicon wafer
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Masking Process
• Expose through mask– UV light
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Masking Process• Remove mask and
develop PR– Exposed area
dissolves– This is “positive
photoresist”
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Masking Process• Deposit metal through PR
window– Then dissolve remaining PR
• Why not just use mask?– Masks are expensive– Shine light through mask to
etch PR– Can reuse mask
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Reverse EngineerInverter Layout
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Layout Revisited
• How to “decode” circuit from layout?
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Reverse EngineerInverter Layout
Penn ESE370 Fall 2014 -- Townley & DeHon
Power (Vdd)
GND
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Reverse EngineerInverter Layout
• Where is PMOS transistor?
• NMOS?
Penn ESE370 Fall 2014 -- Townley & DeHon
Power (Vdd)
GND
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Penn ESE370 Fall2010 -- DeHon30
Layout to Circuit
• 1. Identify transistors
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Inverter Layout
• Where is Input?
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Inverter Layout
• Where is Output?
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Layout to Circuit
• 2. Add wires
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Layout to Circuit
• 2. Add wires
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Inverter Layout
• What is structure at top and bottom?
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Layout to Circuit
• 2. Add wires
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Layout to Circuit
• 2. Add wires
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Design Rules• Why not adjacent
transistors?– Plenty of empty
space– If area is money,
pack in as much as possible
• Recall: processing imprecise– Margin of error for
process variation
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Design Rules• Contract between process engineer &
designer– Minimum width/spacing– Can be (often are) process specific
• Lambda rules: scalable design rules– In terms of = 0.5 Lmin (Ldrawn)– Can migrate designs from similar process– Limited scope: 22nm process != 1m
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Design Rules: Some Examples
Penn ESE370 Fall 2014 -- Townley & DeHon
2
66
3
2
2
1.5
n doping
p doping
gate
contact
metal 1
metal 2
via
Legend
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Layout #2 (practice)
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Layout #2 (practice)
• How many transistors?– PMOS?– NMOS?
• How connected?– PMOS, NMOS?
• Inputs connected?• Outputs?• What is it?
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Standard Cells• Lay out gates so that heights match
– Rows of adjacent cells– Standardized sizes
• Motivation: automated place and route– EDA tools convert HDL to layout
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Penn ESE370 Fall 2014 -- Townley & DeHon
Standard Cell Area
inv nand3
All cellsuniformheight
Width ofchanneldeterminedby routing
Cell area
Identify the full custom and standard cell regions on 386DX diehttp://microscope.fsu.edu/chipshots/intel/386dxlarge.html
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Standard Cell Layout Example
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http://www.laytools.com/images/StandardCells.jpg
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ALU in Standard Cell
Penn ESE370 Fall 2014 -- Townley & DeHon
http://www.erc.msstate.edu/mpl/distributions/scmos/images/alu_yongchen.gif
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Penn ESE370 Fall 2014 -- Townley & DeHon
Standard Cell Area
inv nand3
All cellsuniformheight
Width ofchanneldeterminedby routing
Cell area
Identify the full custom and standard cell regions on 386DX diehttp://microscope.fsu.edu/chipshots/intel/386dxlarge.html
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Big Idea
• Layouts are physical realization of circuit– Geometry tradeoff
• Can decrease spacing at the cost of yield• Design rules
• Can go from circuit to layout or layout to circuit by inspection
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Admin
• HW5 out– Due Tuesday – (Thursday next week is Fall Break)
• Here on Friday
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