PicoNode II Timing RecoveryJosie Ammer, Mike Sheets, Bora Nikolic, Jan Rabaey

Problem Statement

Design a 1.6 Mbps DSSS timing recovery unitModulationLength 31 PN codeQPSK symbol constellationSystem specificationsMaximum frequency offset of +/- 200 KHzMinimum input SNR of +1 dBInput is in-phase & quadrature samples at 200 MHz with 7 bits eachPrimary design criterion is power minimizationImplementation using SSHAFT design flowDatapath blocks designed in Simulink, implemented in Module Compiler, verified through VHDL simulationsControl designed in StateflowDatapath and Control composed in Simulink

Algorithm

Input: 8 pre-interpolated data streams from ADCCoarse timing and code acquisitionfeed forward, non-data-aided algorithm based on a matched filterJoint carrier offset and fine timingfeedforward and data-aided; synthesized directly from ML equations Phase estimation using phase-locked loop (PLL)Data-aided acquisition using known pilot symbols to estimate phase offset Decision-directed data reception using detected symbols to calculate error

Coarse Timing Block

Expected match filter magnitude squared output

Coarse Timing Block Diagram

Coarse Timing Datapath Simulation

Possible pilot matches

Blocks verified separately in Simulink

VHDL and Simulink outputs match exactly

Fine Timing Block Diagram

Estimate frequency offset within 2.5 KHz (3-sigma)Choose stream with maximum likelihood timingMaximum likelihood frequency estimation operating with known timing and data (algorithm: Meyr, et. al.)Goal: Lowest power implementation that meets timing specs

Frequency offset < 200 KHz

Frequency estimate within 2.5 KHz

Stream with maximum likelihood timing

CORDIC Angle Find

Freq. Offset

an

bn

cn

Stream {1,2,3} or {3,4,5} or {6,7,8}

Symbol Start

INDEX = SEL

1*sint(16) I and Q

3*sint(7) @25MHz I and Q

MAXMag.Sq.

MF Correlator

MF Correlator

MF Correlator

Phase Diff. an*-an+1

Phase Diff. bn*-bn+1

Phase Diff. cn*-cn+1

S

S

S

1*sint(12) @806KHz I and Q

1*sint(12) @806KHz I and Q

MUX

1*sint(16) @806KHz I and Q

Shift/Truncate

Shift/Truncate

Shift/Truncate

RSSI

1*sint(6) @806KHz I and Q

CORDIC

Slice implemented in Module CompilerInstantiated 29 timesStructureFullPipelinedHigh speedRecursiveShared sliceSignificantly less areaUsed 3 timesRectangular to Polar conversion (x1)Angle rotation (x2)

CORDIC slice

CORDIC stage0 slice

Recursive CORDIC structure

shift

sel neg

+

+

+

+

shift

sel neg

X

Y

A

g

-/+

-/+

+/-

sel neg

t

sel

+

+

X

Y

A

{t=tan-1(2-i)}

{g=i}

Fixed clock

kTs

Matched Filter

Inter- polator

PhaseRotator

Timing independent feedforward carrier sync

Phase independent feedforward symbol sync

Phase independent feedback symbol sync

Timing dependent feedforward carrier sync

Timing dependent feedback carrier sync

{timing, phase} dependent data detector

sel neg

sel neg

X

Y

A

-/+

-/+

+/-

sel neg

t

sel

+

+

X

Y

A

{t=pi/2}

Fixed clock

kTs

Matched Filter

Inter- polator

PhaseRotator

Timing independent feedforward carrier sync

Phase independent feedforward symbol sync

Phase independent feedback symbol sync

Timing dependent feedforward carrier sync

Timing dependent feedback carrier sync

{timing, phase} dependent data detector

shift

sel neg

+

+

+

+

shift

sel neg

X

Y

A

g

-/+

-/+

+/-

sel neg

t

sel

+

+

X

Y

A

{t=tan-1(2-i)}

{g=i}

PLL Block Diagram and Simulation

Phase error (goes to zero in

rotator

OUT

{soft symbols}

IN

phase detector

loop filter

VCO

PILOT_MODE

Fixed clock

kTs

Matched Filter

Inter- polator

PhaseRotator

Timing independent feedforward carrier sync

Phase independent feedforward symbol sync

Phase independent feedback symbol sync

Timing dependent feedforward carrier sync

Timing dependent feedback carrier sync

{timing, phase} dependent data detector

shift

sel neg

+

+

+

+

shift

sel neg

X

Y

A

g

-/+

-/+

+/-

sel neg

t

sel

+

+

X

Y

A

{t=tan-1(2-i)}

{g=i}

sel neg

sel neg

X

Y

A

-/+

-/+

+/-

sel neg

t

sel

+

+

X

Y

A

{t=pi/2}

System Controller Block Diagram

Timing and synchronizationControls gated clocks to the other blocksCounts the chip offset into a symbolMode controllerIdle, Carrier Search, Acquisition, Data Reception

Results

Nominal clock rate is 25 MHzEstimated power consumptionCarrier search mode: 7.6 mWAcquisition mode: 0.47 mWData reception: 1 mW

Chip floorplan estimated die area: 2.2 mm2