piconode ii timing recovery josie ammer, mike sheets, bora nikolic, jan rabaey

PicoNode II Timing Recovery Josie Ammer, Mike Sheets, Bora Nikolic, Jan Rabaey Problem Statement • D esign a 1.6 M bps D SSS tim ing recovery unit •Modulation – Length 31 PN code – Q PSK sym bol constellation • System specifications – M axim um frequency offsetof+/-200 KH z – M inim um inputSN R of+1 dB – Inputis in-phase & quadrature sam ples at200 M H z w ith 7 bits each • Prim ary design criterion is pow erm inim ization • Im plem entation using SSH AFT design flow – D atapath blocks designed in Sim ulink,im plem ented in M odule C om piler,verified through V H D L sim ulations – C ontroldesigned in Stateflow – D atapath and C ontrol com posed in Sim ulink A lgo rithm • In p u t: 8 p re -in te rp o la te d d a ta stre a m s fro m ADC • C o a rs e tim in g a n d c o d e acq uisitio n – fe e d fo rw a rd , n o n -d a ta -a id e d a lg o rith m b a se d o n a m a tch e d filter • Jo in t c a rrie r o ffse t a n d fin e tim ing – fe e d fo rw a rd a n d d a ta -a id e d ; syn th e size d d ire c tly fro m M L equations • P h a se e stim a tio n u sin g p h a s e -lo cke d lo o p (P LL ) – D a ta -a id e d a cq u isitio n u sin g kn o w n p ilo t s ym b o ls to e stim a te p h a se o ffse t – D e cis io n -d ire cte d d a ta re ce p tio n u sin g d e te cte d sym b o ls to ca lcu la te erro r MUX CONTROLLER Coarse Timing Acquisition PLL MUX Frequency Offset Estimation and Fine Timing Acquisition Rotate and Correlate streams PN_PILOT PN_DATA SOFT SYMB HARD SYMB en start clk pilot det sym strobe sel en clk PN s_start s_end clear sel freq est en clk en clk pilot mode correction sel1 sel2 PN correction s_start s_end 8*14 3*14 3*14 1*14 1*24 2 2 CONTROL C o a rs e T im in g B lo c k Ideal Multipath effects 31 chips 31 chips between peaks 24 chips in trough 3 chips ignored before and after peak due to multipath 30 chips in trough E x p e c te d m a tc h filte r m a g n itu d e s q u a re d o u tp u t Match Filter & Adaptive Threshold Datapath Pilot Sequence Detection State Machine pass_thresh low_thresh delay_gtr sel low_accum sel pilot_detected symbol_strobe rssi streams reset_n Chip counter chip31_strobe spread C o a rs e T im in g B lo c k D ia g ra m C oarse Tim ing D atapath Sim ulation Possiblepilot matches BlocksverifiedseparatelyinSimulink Intermediateoutputsavailablefor debugging (terminatedinfinal version) VHDL and Sim ulinkoutputsm atchexactly Fine Tim ing Block D iagram a n b n c n Stream {1,2,3} or {3,4,5} or {6,7,8} Symbol Start INDEX=SEL 1*sint(16) I andQ 3*sint(7) @ 25MHz I andQ MAX Mag. Sq. MF Correlator MF Correlator MF Correlator PhaseDiff. a n *-a n+1 PhaseDiff. b n *-b n+1 PhaseDiff. c n *-c n+1 1*sint(12) @ 806KHz I andQ 1*sint(12) @ 806KHz I andQ MUX 1*sint(16) @ 806KHz I andQ Shift/ Truncate Shift/ Truncate Shift/ Truncate RSSI 1*sint(6) @ 806KHz I andQ C O R D IC lic e im p le m e n te d in o d u le C o m p ile r In s ta n t ia te d 2 9 t im e s tru c tu re F u ll • P ip e lin e d • H ig h s p e e d – R e c u rs iv e • S h a re d s lic e • S ig n ific a n tly le s s a re a • U s e d 3 tim e s – R e c ta n g u la r to P o la r c o n v e rs io n (x 1 ) – A n g le ro ta t io n (x 2 ) s h if t s e l n e g + + + + s h if t s e l n e g X Y A g -/+ -/+ + /- s e l n e g t s e l + + X Y A {t= ta n -1 (2 -i )} {g = i} s e l n e g s e l n e g X Y A -/+ -/+ + /- s e l n e g t s e l + + X Y A {t= p i/ 2 } C O R D IC L o c a tio n T Y P E S tr u c tu r e X ,Y b it w id th A b it w id th D e la y (n s ) A r e a (u m ^ 2 ) P o w e r (m W @ 1 G H z ) F re q E s t B lo c k R e c ta n g u la r to P o la r R e c u rs iv e 1 8 1 0 1 4 .1 1 0 1 0 2 5 1 .8 P L L (ro ta to r a n d c o rre la to r) A n g le -ro ta tio n F u ll 1 2 1 2 1 0 .6 1 7 5 0 1 4 2 .1 P L L ( in s id e lo o p ) A n g le -ro ta to r R e c u rs iv e 1 4 1 2 1 3 .3 8 5 0 3 2 2 .0 O R D IC s lic e R e c u rs iv e C O R D IC s tru c tu re PLL Block D iagram and Sim ulation rotator OUT {soft symbols} IN phase detector loop filter VCO PILOT_M ODE S y s te m C o n tro lle r B lo c k D iagram • T im in g a n d s y n ch ro n iza tio n – C o n tro ls g a te d c lo c k s to th e o th e r b locks – C o u n ts th e c h ip o ffs e t in to a sym bol • M o d e co n tro lle r – Id le , C a rrie r S e a rc h , A c q u is itio n , D a ta R eception Controller FSM Chip counter Symbol counter roll-over reset reset count count Carrier offset estimation timing Rotate and correlate timing look rc_s_start rc_s_end rc_PN fe_s_start fe_s_end fe_PN fe_clear ct_sel_out fe_latch_angle ft_sel_out fe_latch_sel pll_enable ct_reset pll_pilotmode ct_pilot_detect ct_sym_strobe ct_sel ft_sel Results • N om inal clock rate is 25 M Hz • Estim ated pow er consumption – Carriersearch m ode:7.6 m W –Acquisition m ode:0.47 m W – D ata reception: 1 m W Coarse Timing and Carrier Detect (1.2 mm^2) Controller Muxes 1.7 mm 1.3 mm 14 14 14 14 14 14 14 14 10 12 2 Wiring Channel Freq Est and angle finder (0.37 mm^2) Ang Accum and Rotate (0.2 mm^2) PLL (0.2 mm^2) Chipfloorplan estimateddiearea: 2.2 m m 2

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PicoNode II Timing RecoveryJosie Ammer, Mike Sheets, Bora Nikolic, Jan Rabaey
Problem Statement

Design a 1.6 Mbps DSSS timing recovery unitModulationLength 31 PN codeQPSK symbol constellationSystem specificationsMaximum frequency offset of +/- 200 KHzMinimum input SNR of +1 dBInput is in-phase & quadrature samples at 200 MHz with 7 bits eachPrimary design criterion is power minimizationImplementation using SSHAFT design flowDatapath blocks designed in Simulink, implemented in Module Compiler, verified through VHDL simulationsControl designed in StateflowDatapath and Control composed in Simulink
Algorithm

Input: 8 pre-interpolated data streams from ADCCoarse timing and code acquisitionfeed forward, non-data-aided algorithm based on a matched filterJoint carrier offset and fine timingfeedforward and data-aided; synthesized directly from ML equations Phase estimation using phase-locked loop (PLL)Data-aided acquisition using known pilot symbols to estimate phase offset Decision-directed data reception using detected symbols to calculate error
Coarse Timing Block

Expected match filter magnitude squared output

Coarse Timing Block Diagram
Coarse Timing Datapath Simulation

Possible pilot matches

Blocks verified separately in Simulink

VHDL and Simulink outputs match exactly
Fine Timing Block Diagram

Estimate frequency offset within 2.5 KHz (3-sigma)Choose stream with maximum likelihood timingMaximum likelihood frequency estimation operating with known timing and data (algorithm: Meyr, et. al.)Goal: Lowest power implementation that meets timing specs

Frequency offset < 200 KHz

Frequency estimate within 2.5 KHz

Stream with maximum likelihood timing

CORDIC Angle Find

Freq. Offset
an

bn

cn

Stream {1,2,3} or {3,4,5} or {6,7,8}

Symbol Start

INDEX = SEL

1*sint(16) I and Q

3*sint(7) @25MHz I and Q

MAXMag.Sq.

MF Correlator

MF Correlator

MF Correlator

Phase Diff. an*-an+1

Phase Diff. bn*-bn+1

Phase Diff. cn*-cn+1

S

S

S

1*sint(12) @806KHz I and Q

1*sint(12) @806KHz I and Q

MUX

1*sint(16) @806KHz I and Q

Shift/Truncate

Shift/Truncate

Shift/Truncate

RSSI

1*sint(6) @806KHz I and Q
CORDIC

Slice implemented in Module CompilerInstantiated 29 timesStructureFullPipelinedHigh speedRecursiveShared sliceSignificantly less areaUsed 3 timesRectangular to Polar conversion (x1)Angle rotation (x2)

CORDIC slice

CORDIC stage0 slice

Recursive CORDIC structure
shift

sel neg

+

+

+

+

shift

sel neg

X

Y

A

g

-/+

-/+

+/-

sel neg

t

sel

+

+

X

Y

A

{t=tan-1(2-i)}

{g=i}
Fixed clock

kTs

Matched Filter

Inter- polator

PhaseRotator

Timing independent feedforward carrier sync

Phase independent feedforward symbol sync

Phase independent feedback symbol sync

Timing dependent feedforward carrier sync

Timing dependent feedback carrier sync

{timing, phase} dependent data detector
sel neg

sel neg

X

Y

A

-/+

-/+

+/-

sel neg

t

sel

+

+

X

Y

A

{t=pi/2}
Fixed clock

kTs

Matched Filter

Inter- polator

PhaseRotator

Timing independent feedforward carrier sync

Phase independent feedforward symbol sync

Phase independent feedback symbol sync

Timing dependent feedforward carrier sync

Timing dependent feedback carrier sync

{timing, phase} dependent data detector
shift

sel neg

+

+

+

+

shift

sel neg

X

Y

A

g

-/+

-/+

+/-

sel neg

t

sel

+

+

X

Y

A

{t=tan-1(2-i)}

{g=i}
PLL Block Diagram and Simulation

Phase error (goes to zero in
rotator

OUT

{soft symbols}

IN

phase detector

loop filter

VCO

PILOT_MODE
Fixed clock

kTs

Matched Filter

Inter- polator

PhaseRotator

Timing independent feedforward carrier sync

Phase independent feedforward symbol sync

Phase independent feedback symbol sync

Timing dependent feedforward carrier sync

Timing dependent feedback carrier sync

{timing, phase} dependent data detector
shift

sel neg

+

+

+

+

shift

sel neg

X

Y

A

g

-/+

-/+

+/-

sel neg

t

sel

+

+

X

Y

A

{t=tan-1(2-i)}

{g=i}
sel neg

sel neg

X

Y

A

-/+

-/+

+/-

sel neg

t

sel

+

+

X

Y

A

{t=pi/2}
System Controller Block Diagram

Timing and synchronizationControls gated clocks to the other blocksCounts the chip offset into a symbolMode controllerIdle, Carrier Search, Acquisition, Data Reception
Results

Nominal clock rate is 25 MHzEstimated power consumptionCarrier search mode: 7.6 mWAcquisition mode: 0.47 mWData reception: 1 mW

Chip floorplan estimated die area: 2.2 mm2