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Power and Performance Analysis of PDA Architectures
6.893 Advanced VLSI Computer ArchitectureFall 2000
Robert LeeRipal Nathuji
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Power and Performance Analysis of PDA Architectures
Motivation
• Provide standard performance and power benchmarks for PDA architectures
• Run benchmarks on existing platforms and hypothesize areas of weakness
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• Performance Benchmarks– Task switching– GUI window operations– JVM (SPECjvm98)– MPEG playback
• Power Analysis code sequences– Simple ALU operations– Memory Loads/Stores– Procedure call overhead– Branch Prediction
Power and Performance Analysis of PDA Architectures
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Power and Performance Analysis of PDA Architectures
• Task Switching-
Enumerate through top ten window handles in the operating system queue.
Cycle 1000 times activating each handle and measure time to completion.
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Power and Performance Analysis of PDA Architectures
• GUI window operations-
Creation of single window with multiple MFC elements (command bar, text fields, label…etc).
Repositioned window forcing system to redraw 1000 times and measured time to completion.
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Power and Performance Analysis of PDA Architectures
• JVM (SPECjvm98)
-jess: LISP like expert shell system
-jack: parser generator modeled after yac
-mpeg: MPEG layer-3 decoding
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Power and Performance Analysis of PDA Architectures
• MPEG playback
Used PocketTV to play an MPEG clip (1.06MB).
Measured power and subjectively judged quality of playback.
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Power and Performance Analysis of PDA Architectures
• ALU Test-
Chose two distinct registers and performed addition, subtraction, and multiplication operations.
Measured power during loop of instructions.
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Power and Performance Analysis of PDA Architectures
• Memory Loads/Stores-
Read value from memory and write value back to same address. Ensures 100% cache hit.
Measured power during loop of instructions.
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Power and Performance Analysis of PDA Architectures
• Procedure Call Overhead-
Motivation: After looking at assembly code generated by GUI benchmarks, large percentage of instructions were related to operating system level or shared library call outs.
Called a procedure with four arguments. Action of procedure was to simply return.
Measured power during loop.
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Power and Performance Analysis of PDA Architectures
• Branch Prediction-
Randomly jump between 8 lines of code. After jumping program moves back to initial position through an unconditional branch.
Measured power during loop.
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Power and Performance Analysis of PDA Architectures
• Methodology for Power Measurement:-Used lab power supply of 5.5 V-Placed 1.26 ohm resistor in series with power supply, and measured
voltage drop across it.
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Power and Performance Analysis of PDA Architectures
• PDA Overviews:-Aero 2100 series:
MIPS4K Family, 70 Mhz16 MB RAM32 GP registers8K direct mapped data cache (WB)32-entry TLB (fully associative)
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Power and Performance Analysis of PDA Architectures
• PDA Overviews:-Casio E-115:
MIPS4K Family, 131 Mhz32 MB RAM32 GP registers8K direct mapped data cache (WB)32-entry TLB (fully associative)
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Power and Performance Analysis of PDA Architectures
• PDA Overviews:-iPAQ H3600:
Intel StrongARM SA-1100 series, 206Mhz
32 MB RAM27 GP registers8K 2-way set associative data cache
(WB)2 32 entry fully associative TLB’s
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Power and Performance Analysis of PDA Architectures
• PDA Overviews:-Jornada 540 Series:
SH3 Processor, 133 Mhz16 MB RAM16 GP registers8K 2-way set associative data cache
(WB)128 entry TLB (4-way set associative)
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Power and Performance Analysis of PDA Architectures
• Results- Performance Tests- General Power Measurements- Runtime Power Measurements- Architecture Power Measurements
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Power and Performance Analysis of PDA Architectures
Performance
0.00
50.00
100.00
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Aero Casio iPAQ Jornada
Runt
ime
(s) moving windows
task switch
SPECJVM-jess
SPECJVM-jack
SPECJVM-mpeg
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Power and Performance Analysis of PDA Architectures
Poor performance on jack & mpeg:- Require access to large input files
- Both performance tests scale proportionally per platform
- We therefore believe poor performance is due to slow
memory access
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Power and Performance Analysis of PDA Architectures
Poor performance on task switching:Possible causes:
- Proportionally smaller data cache as compared to other consumer level CPU’s such as desktop machines and laptops, which forces memory access.
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Power and Performance Analysis of PDA Architectures
General Power Measurements
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3.5
Aero Casio iPAQ Jornada
Pow
er C
onsu
med
(W)
Idle w/backlight
Idle w/o backlight
bootup peak
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Power and Performance Analysis of PDA Architectures
Runtime Power Measurements
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1
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2.5
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Aero Casio iPAQ Jornada
Pow
er C
onsu
med
(W)
moving windows
task switch
MPEG playback
jess
jack
mpeg
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Power and Performance Analysis of PDA Architectures
General trends between platforms seem similar. Interesting observation:
Aero and Jornada peak more on memory intensive tests.
Both have 16 MB of RAM as opposed to 32 MB of iPAQ and Casio. Could
be due to memory fragmentation.
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Power and Performance Analysis of PDA Architectures
Architecture Power Measurements
0
0.5
1
1.5
2
2.5
3
Aero Casio iPAQ Jornada
Pow
er C
onsu
med
(W)
ALU
Memory
Procedure Invocation
Branch mispredict
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Power and Performance Analysis of PDA Architectures
Conclusions• Current PDAs suffer issues similar to issues
in desktop and laptop computers (memory latency, data caching…)
• Particularly weak areas seem to be task switching and file I/O