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11 차시
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Chapter 7
1~7
Memory and Programmable Logic
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Ch. 7 Memory and Programmable Logic
7.1 Introduction
memory unit : collection of cells capable of storing a large quantity of binary information
random-access memory (RAM) read-only memory: programmable logic device programmable logic device • read-only memory (ROM) • programmable logic array (PLA) • programmable array logic (PAL) • field-programmable gate array (FPGA)
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programming : removing the fuses
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7.2 Random Access Memory(RAM)
stores binary information in groups of bits words k address bits 2k words K (kilo) : 210, M (mega) : 220, G (giga) : 230
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Write and Read operation
write operation
• apply the binary address • apply the binary data bits • activate the write input
read operation
• apply the binary address • activate the read input
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commercial memory provide two control inputs
• to select the unit, and • to determine the operation
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timing waveforms
access time : time required to to select a word and read it cycle time : time required to complete a write operation
not necessarily the same
Ex) CPU of 50MHz clock & memory with 50ns maximum cycle time
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The CPU transfer data into one of its internal register during negative edge of T3.
Address and data must remain stable for a short time after the control signal are deactivated
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Types of memories
random-access vs. sequential access (constant access time vs. varying access time) static vs. dynamic (SRAM vs. DRAM) (stored in latches vs. electric charges on capacitor) needs refreshing with DRAM volatile vs. nonvolatile
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7.3 Memory decoding
Memory cell has three inputs
select input read/write input data input
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coincident decoding
decoder with k inputs and 2k outputs : requires 2k AND gates with k inputs per gate two-dimensional selection pattern decreases drastically the required AND gates
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address multiplexing
six transistor for a cell of SRAM vs. one MOS transistor and a capacitor DRAM has four times density of SRAM lower power consumption with DRAM to reduce the number of pins in the IC package, use address multiplexing (row address first, and then column address)
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7.4 Error detection and correction
Parity check cannot correct it Correctable parity check?
Hamming code
n –bit data + k parity bits = n+k bits positions numbered as a power of 2 are reserved for the parity bits the remaining bits are the data bits used with words of any length
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ex) 8-bit data word 11000100
Bit position 1 2 3 4 5 6 7 8 9 10 11 12
P1 P2 1 P4 1 0 0 P8 0 1 0 0
P1 = XOR of bits (3,5,7,9,11)=0 P2 = XOR of bits (3,6,7,10,11)=0 P4 = XOR of bits (5,6,7,12)=1 P8 = XOR of bits (9,10,11,12)=1
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Bit position 1 2 3 4 5 6 7 8 9 10 11 12
0 0 1 1 1 0 0 1 0 1 0 0
In the reading process, parity is checked including the Parity bits.
C1 = XOR of bits (1,3,5,7,9,11) C2 = XOR of bits (2,3,6,7,10,11) C4 = XOR of bits (4,5,6,7,12) C8 = XOR of bits (8,9,10,11,12)
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If C=C8C4C2C1 0, C8C4C2C1 gives the position of the erroneous bit.
Ex)
Bit position 1 2 3 4 5 6 7 8 9 10 11 12
0 0 1 1 1 0 0 1 0 1 0 0 no error 1 0 1 1 1 0 0 1 0 1 0 0 error in bit 1 0 0 1 1 0 0 0 1 0 1 0 0 error in bit 5
C8C4C2C1
no error 0 0 0 0 error in bit 1 0 0 0 1 error in bit 5 0 1 0 1
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Hamming code = k check bits + n data bits = n+k bits
With k check bits, 2k-1 positions can indicate the error position. 2k-1 n+k 2k-1-k n
Ex) with n=8, k 5
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grouping of bits for parity generation and checking?
For P1, all binary numbers which has the LSB of 1. For P2, all binary numbers which has the second LSB of 1. : : For Pn, all binary numbers which has the n-th LSB of 1.
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single error correction, double-error detection
Hamming code can detect and correct only a single error. By adding another parity bit, such as 0 0 1 1 1 0 0 1 0 1 0 0 P13
XOR the other 12 bits
In read process, P(=XOR of all 13bits) is 0 with no error, 1 with error
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If C = 0, and P=0 no error If C 0, and P=1 a single error occurred, and can be corrected If C 0, and P=0, a double error detectable, but not correctable If C = 0, and P=1, P13 bit is error
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에러 정정 코드 : 해밍(hamming code)코드
에러를 정정할 수 있는 코드
추가적으로 많은 비트가 필요하므로 많은 양의 데이터 전달이 필요
추가되는 패리티 비트의 수
p는 패리티 비트의 수, d는 데이터 비트의 수
해밍코드에서는 짝수 패리티를 사용
12 pdp
비트위치 1 2 3 4 5 6 7 8 9 10 11 12
기호 P1 P2 D3 P4 D5 D6 D7 P8 D9 D10 D11 D12
P1 영역
P2 영역
P4 영역
P8 영역
![Page 27: PowerPoint 프레젠테이션 - KOCWelearning.kocw.net/KOCW/document/2016/hufs/hanhyungoo/11.pdf · 7.2 Random Access Memory(RAM) ... 7.3 Memory decoding Memory cell has three inputs](https://reader034.vdocument.in/reader034/viewer/2022042217/5ec0ea48800e9475652763cf/html5/thumbnails/27.jpg)
8비트 데이터의 에러 정정 코드
for example
12111098
127654
11107632
1197531
DDDDP
DDDDP
DDDDDP
DDDDDP
D3 D5 D6 D7 D9 D10 D11 D12
0 0 1 0 1 1 1 0
10111
10010
111010
011000
12111098
127654
11107632
1197531
DDDDP
DDDDP
DDDDDP
DDDDDP
![Page 28: PowerPoint 프레젠테이션 - KOCWelearning.kocw.net/KOCW/document/2016/hufs/hanhyungoo/11.pdf · 7.2 Random Access Memory(RAM) ... 7.3 Memory decoding Memory cell has three inputs](https://reader034.vdocument.in/reader034/viewer/2022042217/5ec0ea48800e9475652763cf/html5/thumbnails/28.jpg)
해밍코드에서 패리티 비트 생성 과정
비트위치 1 2 3 4 5 6 7 8 9 10 11 12
기호 P1 P2 D3 P4 D5 D6 D7 P8 D9 D10 D11 D12
원본 데이터 0 0 1 0 1 1 1 0
P1 영역 0 0 0 0 1 1
P2 영역 1 0 1 0 1 1
P4 영역 1 0 1 0 0
P8 영역 1 1 1 1 0
생성된 코드 0 1 0 1 0 1 0 1 1 1 1 0
생성된 패리티
![Page 29: PowerPoint 프레젠테이션 - KOCWelearning.kocw.net/KOCW/document/2016/hufs/hanhyungoo/11.pdf · 7.2 Random Access Memory(RAM) ... 7.3 Memory decoding Memory cell has three inputs](https://reader034.vdocument.in/reader034/viewer/2022042217/5ec0ea48800e9475652763cf/html5/thumbnails/29.jpg)
해밍코드에서 패리티 비트 검사 과정
전송된 데이터 : 010111011110
패리티들을 포함하여 검사
검사된 패리티를 C8 C4 C2 C1 순서대로 정렬한다.
모든 패리티가 0이면 에러가 없는 것이고, 그렇지 않으면 에러가 발생한 것이다.
결과가 0101이므로 에러가 있으며, 이것을 10진수로 바꾸면 5가 된다. 즉, 수신된 데이터 01011101110에서 앞에서 5번째 비트 1이 에러가 발생한 것이므로 01010101110으로 바꾸어 주면 에러가 정정된다.
P1 P2 D3 P4 D5 D6 D7 P8 D9 D10 D11 D12
0 1 0 1 1 1 0 1 1 1 1 0
001111
100111
0110101
1110100
121110988
1276544
111076322
11975311
DDDDPC
DDDDPC
DDDDDPC
DDDDDPC
![Page 30: PowerPoint 프레젠테이션 - KOCWelearning.kocw.net/KOCW/document/2016/hufs/hanhyungoo/11.pdf · 7.2 Random Access Memory(RAM) ... 7.3 Memory decoding Memory cell has three inputs](https://reader034.vdocument.in/reader034/viewer/2022042217/5ec0ea48800e9475652763cf/html5/thumbnails/30.jpg)
해밍코드에서 에러가 발생한 경우 교정
비트위치 1 2 3 4 5 6 7 8 9 10 11 12
기호 P1 P2 D3 P4 D5 D6 D7 P8 D9 D10 D11 D12
Error 해밍코드 0 1 0 1 1 1 0 1 1 1 1 0
P1 계산 1 0 0 1 0 1 1
P2 계산 0 1 0 1 0 1 1
P4 계산 1 1 1 1 0 0
P8 계산 0 1 1 1 1 0
P8 P4 P2 P1 =0101= 5 : 5번 비트에 에러가 발생. 1 → 0으로 교정
![Page 31: PowerPoint 프레젠테이션 - KOCWelearning.kocw.net/KOCW/document/2016/hufs/hanhyungoo/11.pdf · 7.2 Random Access Memory(RAM) ... 7.3 Memory decoding Memory cell has three inputs](https://reader034.vdocument.in/reader034/viewer/2022042217/5ec0ea48800e9475652763cf/html5/thumbnails/31.jpg)
에러 정정 코드 : 해밍(hamming code)코드
에러를 정정할 수 있는 코드
추가적으로 많은 비트가 필요하므로 많은 양의 데이터 전달이 필요
추가되는 패리티 비트의 수
p는 패리티 비트의 수, d는 데이터 비트의 수
해밍코드에서는 짝수 패리티를 사용
12 pdp
비트위치 1 2 3 4 5 6 7 8 9 10 11 12
기호 P1 P2 D3 P4 D5 D6 D7 P8 D9 D10 D11 D12
P1 영역
P2 영역
P4 영역
P8 영역
![Page 32: PowerPoint 프레젠테이션 - KOCWelearning.kocw.net/KOCW/document/2016/hufs/hanhyungoo/11.pdf · 7.2 Random Access Memory(RAM) ... 7.3 Memory decoding Memory cell has three inputs](https://reader034.vdocument.in/reader034/viewer/2022042217/5ec0ea48800e9475652763cf/html5/thumbnails/32.jpg)
8비트 데이터의 에러 정정 코드
for example
12111098
127654
11107632
1197531
DDDDP
DDDDP
DDDDDP
DDDDDP
D3 D5 D6 D7 D9 D10 D11 D12
0 0 1 0 1 1 1 0
10111
10010
111010
011000
12111098
127654
11107632
1197531
DDDDP
DDDDP
DDDDDP
DDDDDP
![Page 33: PowerPoint 프레젠테이션 - KOCWelearning.kocw.net/KOCW/document/2016/hufs/hanhyungoo/11.pdf · 7.2 Random Access Memory(RAM) ... 7.3 Memory decoding Memory cell has three inputs](https://reader034.vdocument.in/reader034/viewer/2022042217/5ec0ea48800e9475652763cf/html5/thumbnails/33.jpg)
해밍코드에서 패리티 비트 생성 과정
비트위치 1 2 3 4 5 6 7 8 9 10 11 12
기호 P1 P2 D3 P4 D5 D6 D7 P8 D9 D10 D11 D12
원본 데이터 0 0 1 0 1 1 1 0
P1 영역 0 0 0 0 1 1
P2 영역 1 0 1 0 1 1
P4 영역 1 0 1 0 0
P8 영역 1 1 1 1 0
생성된 코드 0 1 0 1 0 1 0 1 1 1 1 0
생성된 패리티
![Page 34: PowerPoint 프레젠테이션 - KOCWelearning.kocw.net/KOCW/document/2016/hufs/hanhyungoo/11.pdf · 7.2 Random Access Memory(RAM) ... 7.3 Memory decoding Memory cell has three inputs](https://reader034.vdocument.in/reader034/viewer/2022042217/5ec0ea48800e9475652763cf/html5/thumbnails/34.jpg)
해밍코드에서 패리티 비트 검사 과정
전송된 데이터 : 010111011110
패리티들을 포함하여 검사
검사된 패리티를 C8 C4 C2 C1 순서대로 정렬한다.
모든 패리티가 0이면 에러가 없는 것이고, 그렇지 않으면 에러가 발생한 것이다.
결과가 0101이므로 에러가 있으며, 이것을 10진수로 바꾸면 5가 된다. 즉, 수신된 데이터 01011101110에서 앞에서 5번째 비트 1이 에러가 발생한 것이므로 01010101110으로 바꾸어 주면 에러가 정정된다.
P1 P2 D3 P4 D5 D6 D7 P8 D9 D10 D11 D12
0 1 0 1 1 1 0 1 1 1 1 0
001111
100111
0110101
1110100
121110988
1276544
111076322
11975311
DDDDPC
DDDDPC
DDDDDPC
DDDDDPC
![Page 35: PowerPoint 프레젠테이션 - KOCWelearning.kocw.net/KOCW/document/2016/hufs/hanhyungoo/11.pdf · 7.2 Random Access Memory(RAM) ... 7.3 Memory decoding Memory cell has three inputs](https://reader034.vdocument.in/reader034/viewer/2022042217/5ec0ea48800e9475652763cf/html5/thumbnails/35.jpg)
해밍코드에서 에러가 발생한 경우 교정
비트위치 1 2 3 4 5 6 7 8 9 10 11 12
기호 P1 P2 D3 P4 D5 D6 D7 P8 D9 D10 D11 D12
Error 해밍코드 0 1 0 1 1 1 0 1 1 1 1 0
P1 계산 1 0 0 1 0 1 1
P2 계산 0 1 0 1 0 1 1
P4 계산 1 1 1 1 0 0
P8 계산 0 1 1 1 1 0
P8 P4 P2 P1 =0101= 5 : 5번 비트에 에러가 발생. 1 → 0으로 교정