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Projecto para a testabilidade © J. Machado da Silva, J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 1
The IEEE 1149.4 std for mixed-signal testProjecto para a Testabilidade
J. Machado da Silva
FEUP / DEEC - Rua Dr. Roberto Frias4200-537 Porto - PORTUGAL
Tel. 351 225 081 748 / Fax: 351 225 081 443
([email protected] / http://www.fe.up.pt/~jms)
[text adapted from the course by José Martins Ferreira]
Projecto para a testabilidade © J. Machado da Silva, J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 2
The IEEE 1149.4 standard for mixed signal test
IC 2
Core
TBIC
SH
SL
VH
SB1 SB2
-+ c
c
cc
TDO
TDI
IC 1
AB1AB2
VL
TBIC
ATAP
SGVG
CoreR
AT1
AT2
TDI
TDO
TMSTCK
ABM
AT 2
AT 1
ATAP
VTH
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Projecto para a testabilidade © J. Machado da Silva, J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 3
The IEEE 1149.4 standard for mixed signal test
SB1 SB2
SD CORE
IC
TBICAT1
Stimulusgenerator
SB1 SB2
SDCORE
IC
Observer/Test instrument
AT 2
Control Observation
TBIC
Projecto para a testabilidade © J. Machado da Silva, J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 4
The IEEE 1149.4 standard for mixed signal test
• Test of Simple Interconnects
SD
VH
CORESD
CORE
IC 1 IC 2
AB1AB2 TBIC TBIC
SH
SL
VL
VH
VL
SH
SL
AT1AT2
-+ c
c
cc
TDI
Thresholdvoltage
TDO
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Projecto para a testabilidade © J. Machado da Silva, J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 5
The IEEE 1149.4 standard for mixed signal test
• Discrete Component Testing (Two line method)
Parker, McDermid, Oresjo“Structure and Metrology for an Analog Testability Bus”, ITC 93
V1- V2I
R =
SB1 SB2
SD
SB1 SB2
CORESD
CORE
R
IC 1 IC 2
AB1AB2
I V1
TBIC TBIC
VH
VL
SH
SL
AT1
AT2
V2
V1 V2
Projecto para a testabilidade © J. Machado da Silva, J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 6
The IEEE 1149.4 standard for mixed signal test
• Discrete Component Testing (Single line method)
Lu, Mao, Dandapani, Gulati“Structure and Metrology for a Single-wire Analog Testability Bus”, ITC 94
SB1 SB2
SD
SB1 SB2
SD R
IC 1 IC 2
AB
IV11V12
SH
VL
VH
SL
R
IC 1 IC 2
AB
IV21
SB2
SD
SB2SB1
SH
SLSB1
SD
VH
VL
V22
2V12-V11-2V22+V21I
R =
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Projecto para a testabilidade © J. Machado da Silva, J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 7
The IEEE 1149.4 standard for mixed signal test
• The power supply based method
R
IC 1 IC 2
AT
V2
VL
VDDIDDT=IDD0+∆I
S L SL
S HSDSD
SB2
SD R
IC 1 IC 2
AT
V1
VDDIDDT=IDD0+∆I
SL
S H S HSD
SB2
V1-V2∆I
R =J. Machado da Silva, J. S. Matos“Implementation of Mixed Current/VoltageTesting Using the IEEEP1149.4 Infrastructure”, ITC 97
Projecto para a testabilidade © J. Machado da Silva, J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 8
The IEEE 1149.4 standard for mixed signal test
BST infrastructure (except the BST register)
TBIC
ABM
DBM
(AB1, AB2)
AT1 AT2
TDI
TMS
TCK
TDO
• The 1149.4 std defines an extension to 1149.1, to which it adds:– An analogue test port (ATAP )
with two pins (AT1, AT2)– An internal analogue test bus
(AB1, AB2)– A test bus interface circuit
(TBIC)– The analogue boundary
modules (ABM )
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Projecto para a testabilidade © J. Machado da Silva, J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 9
IEEE 1149.4: The TBIC and the ABMs
• Interconnect and parametrictests can be carried out through the ABMs
• Analogue test signals may be routed from / to the analogue pins to / from the ATAP through the TBIC and the ABMs
• The TBIC and the ABM comprise a switching structure and a control structure
BST infrastructure (except the BST register)
TBIC
ABM
DBM
(AB1, AB2)
AT1 AT2
TDI
TMS
TCK
TDO
Projecto para a testabilidade © J. Machado da Silva, J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 10
The test bus interface circuit (TBIC)
• The TBIC defines the interconnections between the ATAP (AT1 and AT2) and the internal analogue test bus (at least two lines, AB1 and AB2)
• The TBIC comprises a switching structure and a control structure
BST infrastructure (except the BST register)
TBIC
ABM
DBM
(AB1, AB2)
AT1 AT2
TDI
TMS
TCK
TDO
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Projecto para a testabilidade © J. Machado da Silva, J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 11
TBIC: The switching structure
AT1
AT2
AB1 AB2
VH
VL
VTH
Vclamp S1
S3
S2
S4 S9 S10
S8 S7 S5 S6
BST infrastructure (except the BST register)
TBIC
ABM
DBM
(AB1, AB2)
AT1 AT2
TDI
TMS
TCK
TDO
Projecto para a testabilidade © J. Machado da Silva, J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 12
TBIC: Switching structure patterns
AT1
AT2
AB1 AB2
VH
VL
VTH
Vclamp
S1
S3
S2
S4 S9 S10
S8 S7S5 S6
Main testing conditions
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Projecto para a testabilidade © J. Machado da Silva, J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 13
Switching assignments for defined instructions (TBIC)
AT1
AT2
AB1 AB2
VH
VL
VTH
Vclamp
S1
S3
S2
S4 S9 S10
S8 S7S5 S6
AT1
AT2
AB1 AB2
VH
VL
VTH
Vclamp
S1
S3
S2
S4 S9 S10
S8 S7S5 S6
Projecto para a testabilidade © J. Machado da Silva, J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 14
TBIC: Control structure
BST infrastructure (except the BST register)
TBIC
ABM
DBM
(AB1, AB2)
AT1 AT2
TDI
TMS
TCK
TDO
Serial input
mux
C/S
L
Parallel input
Parallel output
Serial output
Parallel input
Serial input
Serial output
Parallel input
Parallel input
Parallel input
S1 S2 S10
Control logic
Parallel output
Mode
Inputs available to the user VTH VTH
AT1 AT2 Switching structure comparators
Switching structure
Parallel output
Parallel output
Parallel output
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Projecto para a testabilidade © J. Machado da Silva, J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 15
The analogue boundary modules (ABM)
• The ABMs in the analogue pins extend the test functions made available by the DBMs
• All test operations combine digital (via TAP) and analogue test “vectors” (via ATAP)
• Each ABM comprises a switching structure and a control structure
BST infrastructure (except the BST register)
TBIC
ABM
DBM
(AB1, AB2)
AT1 AT2
TDI
TMS
TCK
TDO
Projecto para a testabilidade © J. Machado da Silva, J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 16
ABMs: Switching structure
SH SL SG
SB1 SB2
Analog pin
AB2
AB1 VH VL VG VTH
SD
Internal analog block
BST infrastructure (except the BST register)
TBIC
ABM
DBM
(AB1, AB2)
AT1 AT2
TDI
TMS
TCK
TDO
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Projecto para a testabilidade © J. Machado da Silva, J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 17
ABMs: Switching structure patterns (1)
SH SL SG
SB1 SB2
Analog pin
AB2
AB1 VH VL VG VTH
SD
Internal analog block
Main testing conditions for analogue
measurements
Projecto para a testabilidade © J. Machado da Silva, J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 18
ABMs: Switching structure patterns (2)
SH SL SG
SB1 SB2
Analog pin
AB2
AB1 VH VL VG VTH
SD
Internal analog block
Normal mission mode; pin connected
to core only.
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Projecto para a testabilidade © J. Machado da Silva, J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 19
ABMs: Switching pattern requirements
SH SL SG
SB1 SB2
Analog pin
AB2
AB1 VH VL VG VTH
SD
Internal analog block
SH SL SG
SB1 SB2
Analog pin
AB2
AB1 VH VL VG VTH
SD
Internal analog block
Projecto para a testabilidade © J. Machado da Silva, J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 20
BST infrastructure (except the BST register)
TBIC
ABM
DBM
(AB1, AB2)
AT1 AT2
TDI
TMS
TCK
TDO
Serial input
mux
C/S
L
Parallel input
Parallel output
Serial output
Parallel input
Serial input
Serial output
Parallel input
Parallel input
Parallel input
SD SH SB2
Control logic
Parallel output
Mode
Inputs available to the user
VTH
Pin
Switching structure comparator
Switching structure
Parallel output
Parallel output
Parallel output
ABMs: Controlstructure
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Projecto para a testabilidade © J. Machado da Silva, J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 21
The 1149.4 register structure
• The 1149.4 register structure is entirely digital and identical to the corresponding1149.1 structure
User registers
Identification register
Reg. BP
Decoder
Instruction reg.
Data mux
Data / instruction mux
TAP contr.
TDI
/TRST TMS TCK
TDO
BST register
TBIC cells
ABM cells
DBM (BST cells in 1149.1)
Projecto para a testabilidade © J. Machado da Silva, J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 22
The PROBE instruction
• The IEEE 1149.4 std defines a fourth mandatory instruction called PROBE:– The selected data register is the BS register– One or both of the ATAP pins connect to the
corresponding AB1/AB2 internal test bus lines– Analog pins connect to the core and to AB1/AB2
as defined by the ABM 4-bit control word– Each DBM operates in transparent mode
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Projecto para a testabilidade © J. Machado da Silva, J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 23
Analog test operations
• Principle of operation:– The analog signal is applied
to AT1 and the analog response is observed in AT2
– With AT1 connected to AB1, the analog signal may be routed to the internal circuitry or to an analog output pin
– Analog responses from the internal circuitry or from an analog input pin are routed to AB2, and observed in AT2
BST infrastructure (except the BST register)
TBIC
ABM
DBM
(AB1, AB2)
AT1 AT2
TDI
TMS
TCK
TDO
Projecto para a testabilidade © J. Machado da Silva, J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 24
SH SL SG
SB1 SB2 Analog pin
AB2 AB1
VH VL VG VTH
SD
AT1
AT2
AB1 AB2
VH
VL
VTH
Vclamp
S1
S3
S2
S4 S9 S10
S8 S7S5 S6
Observability of analog (input / output) pins
• The signal present at any analog (input / output) pin may be observed at AT2, with (or without) the core connected to the pin
BST infrastructure (except the BST register)
ABM
DBM
AT1 AT2
TDI
TMS
TCK
TDO
ABM
DBM
TBIC
(AB1, AB2)
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Projecto para a testabilidade © J. Machado da Silva, J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 25
SH SL SG
SB1 SB2 Analog pin
AB2 AB1
VH VL VG VTH
SD
AT1
AT2
AB1 AB2
VH
VL
VTH
Vclamp
S1
S3
S2
S4 S9 S10
S8 S7S5 S6
Controllability of analog (input / output) pins
• The signal present at any analog (input / output) pin may be driven from AT1, regardless of the signal present at the analog input
BST infrastructure (except the BST register)
ABM
DBM
AT1 AT2
TDI
TMS
TCK
TDO
ABM
DBM
TBIC
(AB1, AB2)
Projecto para a testabilidade © J. Machado da Silva, J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 26
SH SL SG
SB1 SB2 Analog pin
AB2 AB1
VH VL VG VTH
SD
AT1
AT2
AB1 AB2
VH
VL
VTH
Vclamp
S1
S3
S2
S4 S9 S10
S8 S7S5 S6
Impedance measurement between pin and ground
BST infrastructure (except the BST register)
TBIC
ABM
DBM
(AB1, AB2)
AT1 AT2
TDI
TMS
TCK
TDO
IT
VVT
ZD = VT / IT if:
• ZV >> ZS6 + ZSB2• ZV + ZS6 + ZSB2 >> ZD
ZD
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Projecto para a testabilidade © J. Machado da Silva, J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 27
Interconnect testing with 1149.4
SH SL SG
SB1 SB2 Analog output
AB2
AB1 VH VL VG VTH
SD
Internal analog block
SH SL SG
SB1 SB2
Analog input
AB2
AB1 VH VL VG VTH
SD
Internal analog block
SH SL SG
SB1 SB2 Analog output
AB2
AB1 VH VL VG VTH
SD
Internal analog block
SH SL SG
SB1 SB2
Analog input
AB2
AB1 VH VL VG VTH
SD
Internal analog block
VVVVHHHH
VVVVLLLL
????
DBM
TDO
ABM
DBM
(AB1, AB2)
DBM
TDO
ABM
DBM
(AB1, AB2)
DBM
TDO
ABM
DBM
(AB1, AB2)
DBM
TDO
ABM
DBM
(AB1, AB2)
VVVVHHHH
VVVVLLLL
????
Projecto para a testabilidade © J. Machado da Silva, J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 28
Functional description of a basic “1149.4 component”
• The core circuitry is restricted to– A voltage follower– A logic inverter
• The required 1149.4 infrastructure should only support the mandatory instructions
BST infrastructure (except the BST register)
ABM
DBM (AB1, AB2)
AT1 AT2
TDI
TMS
TCK
TDO
ABM
DBM
TBIC
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Projecto para a testabilidade © J. Machado da Silva, J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 29
Summary description of the 1149.4 infrastructure
• Instruction codes (8-bit):– EXTEST: $00– SAMPLE / PRELOAD: $02– PROBE: $01– BYPASS: $FF
• Boundary scan register (TDI-TDO, 14-bit):– TBIC (4-bit), ABM analog input (4-bit), ABM
analog output (4-bit), DBM digital input (1-bit), DBM digital output (1-bit)