the ieee 1149.4 std for mixed-signal testjms/ppt/aula6_mst07.pdf · 1 projecto para a testabilidade...

1

Projecto para a testabilidade © J. Machado da Silva, J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 1

The IEEE 1149.4 std for mixed-signal testProjecto para a Testabilidade

J. Machado da Silva

FEUP / DEEC - Rua Dr. Roberto Frias4200-537 Porto - PORTUGAL

Tel. 351 225 081 748 / Fax: 351 225 081 443

([email protected] / http://www.fe.up.pt/~jms)

[text adapted from the course by José Martins Ferreira]


The IEEE 1149.4 standard for mixed signal test

IC 2

Core

TBIC

SH

SL

VH

SB1 SB2

-+ c

c

cc

TDO

TDI

IC 1

AB1AB2

VL

TBIC

ATAP

SGVG

CoreR

AT1

AT2

TDI

TDO

TMSTCK

ABM

AT 2

AT 1

ATAP

VTH

2



SB1 SB2

SD CORE

IC

TBICAT1

Stimulusgenerator

SB1 SB2

SDCORE

IC

Observer/Test instrument

AT 2

Control Observation

TBIC



• Test of Simple Interconnects

SD

VH

CORESD

CORE

IC 1 IC 2

AB1AB2 TBIC TBIC

SH

SL

VL

VH

VL

SH

SL

AT1AT2

-+ c

c

cc

TDI

Thresholdvoltage

TDO

3



• Discrete Component Testing (Two line method)

Parker, McDermid, Oresjo“Structure and Metrology for an Analog Testability Bus”, ITC 93

V1- V2I

R =

SB1 SB2

SD

SB1 SB2

CORESD

CORE

R

IC 1 IC 2

AB1AB2

I V1

TBIC TBIC

VH

VL

SH

SL

AT1

AT2

V2

V1 V2



• Discrete Component Testing (Single line method)

Lu, Mao, Dandapani, Gulati“Structure and Metrology for a Single-wire Analog Testability Bus”, ITC 94

SB1 SB2

SD

SB1 SB2

SD R

IC 1 IC 2

AB

IV11V12

SH

VL

VH

SL

R

IC 1 IC 2

AB

IV21

SB2

SD

SB2SB1

SH

SLSB1

SD

VH

VL

V22

2V12-V11-2V22+V21I

R =

4



• The power supply based method

R

IC 1 IC 2

AT

V2

VL

VDDIDDT=IDD0+∆I

S L SL

S HSDSD

SB2

SD R

IC 1 IC 2

AT

V1

VDDIDDT=IDD0+∆I

SL

S H S HSD

SB2

V1-V2∆I

R =J. Machado da Silva, J. S. Matos“Implementation of Mixed Current/VoltageTesting Using the IEEEP1149.4 Infrastructure”, ITC 97



BST infrastructure (except the BST register)

TBIC

ABM

DBM

(AB1, AB2)

AT1 AT2

TDI

TMS

TCK

TDO

• The 1149.4 std defines an extension to 1149.1, to which it adds:– An analogue test port (ATAP )

with two pins (AT1, AT2)– An internal analogue test bus

(AB1, AB2)– A test bus interface circuit

(TBIC)– The analogue boundary

modules (ABM )

5


IEEE 1149.4: The TBIC and the ABMs

• Interconnect and parametrictests can be carried out through the ABMs

• Analogue test signals may be routed from / to the analogue pins to / from the ATAP through the TBIC and the ABMs

• The TBIC and the ABM comprise a switching structure and a control structure


TBIC

ABM

DBM

(AB1, AB2)

AT1 AT2

TDI

TMS

TCK

TDO


The test bus interface circuit (TBIC)

• The TBIC defines the interconnections between the ATAP (AT1 and AT2) and the internal analogue test bus (at least two lines, AB1 and AB2)

• The TBIC comprises a switching structure and a control structure


TBIC

ABM

DBM

(AB1, AB2)

AT1 AT2

TDI

TMS

TCK

TDO

6


TBIC: The switching structure

AT1

AT2

AB1 AB2

VH

VL

VTH

Vclamp S1

S3

S2

S4 S9 S10

S8 S7 S5 S6


TBIC

ABM

DBM

(AB1, AB2)

AT1 AT2

TDI

TMS

TCK

TDO


TBIC: Switching structure patterns

AT1

AT2

AB1 AB2

VH

VL

VTH

Vclamp

S1

S3

S2

S4 S9 S10

S8 S7S5 S6

Main testing conditions

7


Switching assignments for defined instructions (TBIC)

AT1

AT2

AB1 AB2

VH

VL

VTH

Vclamp

S1

S3

S2

S4 S9 S10

S8 S7S5 S6

AT1

AT2

AB1 AB2

VH

VL

VTH

Vclamp

S1

S3

S2

S4 S9 S10

S8 S7S5 S6


TBIC: Control structure


TBIC

ABM

DBM

(AB1, AB2)

AT1 AT2

TDI

TMS

TCK

TDO

Serial input

mux

C/S

L

Parallel input

Parallel output

Serial output

Parallel input

Serial input

Serial output

Parallel input

Parallel input

Parallel input

S1 S2 S10

Control logic

Parallel output

Mode

Inputs available to the user VTH VTH

AT1 AT2 Switching structure comparators

Switching structure

Parallel output

Parallel output

Parallel output

8


The analogue boundary modules (ABM)

• The ABMs in the analogue pins extend the test functions made available by the DBMs

• All test operations combine digital (via TAP) and analogue test “vectors” (via ATAP)

• Each ABM comprises a switching structure and a control structure


TBIC

ABM

DBM

(AB1, AB2)

AT1 AT2

TDI

TMS

TCK

TDO


ABMs: Switching structure

SH SL SG

SB1 SB2

Analog pin

AB2

AB1 VH VL VG VTH

SD

Internal analog block


TBIC

ABM

DBM

(AB1, AB2)

AT1 AT2

TDI

TMS

TCK

TDO

9


ABMs: Switching structure patterns (1)

SH SL SG

SB1 SB2

Analog pin

AB2

AB1 VH VL VG VTH

SD


Main testing conditions for analogue

measurements


ABMs: Switching structure patterns (2)

SH SL SG

SB1 SB2

Analog pin

AB2

AB1 VH VL VG VTH

SD


Normal mission mode; pin connected

to core only.

10


ABMs: Switching pattern requirements

SH SL SG

SB1 SB2

Analog pin

AB2

AB1 VH VL VG VTH

SD


SH SL SG

SB1 SB2

Analog pin

AB2

AB1 VH VL VG VTH

SD




TBIC

ABM

DBM

(AB1, AB2)

AT1 AT2

TDI

TMS

TCK

TDO

Serial input

mux

C/S

L

Parallel input

Parallel output

Serial output

Parallel input

Serial input

Serial output

Parallel input

Parallel input

Parallel input

SD SH SB2

Control logic

Parallel output

Mode

Inputs available to the user

VTH

Pin

Switching structure comparator

Switching structure

Parallel output

Parallel output

Parallel output

ABMs: Controlstructure

11


The 1149.4 register structure

• The 1149.4 register structure is entirely digital and identical to the corresponding1149.1 structure

User registers

Identification register

Reg. BP

Decoder

Instruction reg.

Data mux

Data / instruction mux

TAP contr.

TDI

/TRST TMS TCK

TDO

BST register

TBIC cells

ABM cells

DBM (BST cells in 1149.1)


The PROBE instruction

• The IEEE 1149.4 std defines a fourth mandatory instruction called PROBE:– The selected data register is the BS register– One or both of the ATAP pins connect to the

corresponding AB1/AB2 internal test bus lines– Analog pins connect to the core and to AB1/AB2

as defined by the ABM 4-bit control word– Each DBM operates in transparent mode

12


Analog test operations

• Principle of operation:– The analog signal is applied

to AT1 and the analog response is observed in AT2

– With AT1 connected to AB1, the analog signal may be routed to the internal circuitry or to an analog output pin

– Analog responses from the internal circuitry or from an analog input pin are routed to AB2, and observed in AT2


TBIC

ABM

DBM

(AB1, AB2)

AT1 AT2

TDI

TMS

TCK

TDO


SH SL SG

SB1 SB2 Analog pin

AB2 AB1

VH VL VG VTH

SD

AT1

AT2

AB1 AB2

VH

VL

VTH

Vclamp

S1

S3

S2

S4 S9 S10

S8 S7S5 S6

Observability of analog (input / output) pins

• The signal present at any analog (input / output) pin may be observed at AT2, with (or without) the core connected to the pin


ABM

DBM

AT1 AT2

TDI

TMS

TCK

TDO

ABM

DBM

TBIC

(AB1, AB2)

13


SH SL SG

SB1 SB2 Analog pin

AB2 AB1

VH VL VG VTH

SD

AT1

AT2

AB1 AB2

VH

VL

VTH

Vclamp

S1

S3

S2

S4 S9 S10

S8 S7S5 S6

Controllability of analog (input / output) pins

• The signal present at any analog (input / output) pin may be driven from AT1, regardless of the signal present at the analog input


ABM

DBM

AT1 AT2

TDI

TMS

TCK

TDO

ABM

DBM

TBIC

(AB1, AB2)


SH SL SG

SB1 SB2 Analog pin

AB2 AB1

VH VL VG VTH

SD

AT1

AT2

AB1 AB2

VH

VL

VTH

Vclamp

S1

S3

S2

S4 S9 S10

S8 S7S5 S6

Impedance measurement between pin and ground


TBIC

ABM

DBM

(AB1, AB2)

AT1 AT2

TDI

TMS

TCK

TDO

IT

VVT

ZD = VT / IT if:

• ZV >> ZS6 + ZSB2• ZV + ZS6 + ZSB2 >> ZD

ZD

14


Interconnect testing with 1149.4

SH SL SG

SB1 SB2 Analog output

AB2

AB1 VH VL VG VTH

SD


SH SL SG

SB1 SB2

Analog input

AB2

AB1 VH VL VG VTH

SD


SH SL SG

SB1 SB2 Analog output

AB2

AB1 VH VL VG VTH

SD


SH SL SG

SB1 SB2

Analog input

AB2

AB1 VH VL VG VTH

SD


VVVVHHHH

VVVVLLLL

????

DBM

TDO

ABM

DBM

(AB1, AB2)

DBM

TDO

ABM

DBM

(AB1, AB2)

DBM

TDO

ABM

DBM

(AB1, AB2)

DBM

TDO

ABM

DBM

(AB1, AB2)

VVVVHHHH

VVVVLLLL

????


Functional description of a basic “1149.4 component”

• The core circuitry is restricted to– A voltage follower– A logic inverter

• The required 1149.4 infrastructure should only support the mandatory instructions


ABM

DBM (AB1, AB2)

AT1 AT2

TDI

TMS

TCK

TDO

ABM

DBM

TBIC

15


Summary description of the 1149.4 infrastructure

• Instruction codes (8-bit):– EXTEST: $00– SAMPLE / PRELOAD: $02– PROBE: $01– BYPASS: $FF

• Boundary scan register (TDI-TDO, 14-bit):– TBIC (4-bit), ABM analog input (4-bit), ABM

analog output (4-bit), DBM digital input (1-bit), DBM digital output (1-bit)

the ieee 1149.4 std for mixed-signal testjms/ppt/aula6_mst07.pdf · 1 projecto para a testabilidade...

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