leonardo da vinci allegro © j. m. martins ferreira - university of porto (feup / deec)1 scan design...

Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)

1

Scan design techniquesJ. M. Martins Ferreira

FEUP / DEEC - Rua Dr. Roberto Frias

4200-537 Porto - PORTUGAL

Tel. 351 225 081 748 / Fax: 351 225 081 443

([email protected] / http://www.fe.up.pt/~jmf)


2

Objectives

• To introduce the basic concepts in design for test

• To prepare the introduction of the standard boundary-scan test architecture


3

Outline

• Testability and test generation in sequential circuits

• Testability improvement via ad hoc solutions

• Structured approaches to design for testability


4

Test generation for sequential circuits• Direct application

of the D-algorithm leads to the combinational circuit inputs and outputs, not necessarily to primary inputs or outputs

VCC_BAR

VCC_BAR

VCC_BAR

X s@0(1/0)

0

11

0X

Combinational block

Nextstateoutput

Circuitprimaryoutput

Nextstateoutput

Y

U?A

7408

1

23

U?A

7408

1

23

U?A7474

D2

CLK3

Q5

Q6

PR4

CL1

U?A7474

D2

CLK3

Q5

Q6

PR4

CL1

U?A

7432

1

23

A

CLK

F=1/0


5

Test generation - step 1

V C C _ B A R

V C C _ B A R

V C C _ B A R

X s@0(0/0)

1

00

11

Combinational block

Nextstateoutput


Nextstateoutput

0

1

1

0

U ? A

7 4 0 8

1

23

U ? A

7 4 0 8

1

23

U ? A7 4 7 4

D2

C L K3

Q5

Q6

PR

4C

L1

U ? A7 4 7 4

D2

C L K3

Q5

Q6

PR

4C

L1

U ? A

7 4 3 2

1

23

A=1

CLK

F=1

This is the initial circuit state,

where we assume that both flip-

flops are at 0. Fault detection is

not possible because neither fault

activation nor fault propagation

take place.

F

CLK

A


6


V C C _ B A R

V C C _ B A R

V C C _ B A R

X s@0(0/0)

0

01

10

Combinational block

Nextstateoutput


Nextstateoutput

0

1

0

1

1

U ? A

7 4 0 8

1

23

U ? A

7 4 0 8

1

23

U ? A7 4 7 4

D2

C L K3

Q5

Q6

PR

4C

L1

U ? A7 4 7 4

D2

C L K3

Q5

Q6

PR

4C

L1

U ? A

7 4 3 2

1

23

A=1

CLK

F=0

The first clock cycle is applied with

A=1, leading the circuit to a new state

which is still not capable of activating

the fault. Fault propagation would

however be possible, since the other

OR input is now at 0.

CLK

A

F


7


VCC_BAR

VCC_BAR

VCC_BAR

X s@0(1/0)

0

11

00

Combinational block

Nextstateoutput


Nextstateoutput

1

0

0

1

1

U?A

7408

1

23

U?A

7408

1

23

U?A7474

D2

CLK3

Q5

Q6

PR

4C

L1

U?A7474

D2

CLK3

Q5

Q6

PR

4C

L1

U?A

7432

1

23

A=1

CLK

F=1/0

The second clock cycle is applied with

A=1 and guarantees fault detection,

because the circuit is now brought to a

state where fault activation and fault

propagation are simultaneously

possible.

F

CLK

A

fault-free

X s@0


8

The general case is however much more complex...• The D-algorithm does not necessarily lead

to circuit primary inputs and outputs

• Knowledge of the state transition diagram is required

• It may happen that the fault affects the state transition diagram, in which case the required sequence at the circuit primary inputs becomes even harder to find


9

The case of Y s@0

VCC_BAR

VCC_BAR

VCC_BAR

X s@0(1/0)

0

11

0X

Combinational block

Nextstateoutput


Nextstateoutput

Y

U?A

7408

1

23

U?A

7408

1

23

U?A7474

D2

CLK3

Q5

Q6

PR4

CL1

U?A7474

D2

CLK3

Q5

Q6

PR4

CL1

U?A

7432

1

23

A

CLK

F=1/0

• Test vector generation for a fault that affects the state transition diagram will help us to understand the problem


10

The case of Y s@0 (cont.)

0

1

1

3

2

1

0

0

0

0 1

Q1,Q0=00

1

01

10

11

• Modification in the state transition diagram:

VCC_BAR

VCC_BAR

VCC_BAR

X s@0(1/0)

0

11

0X

Combinational block

Nextstateoutput


Nextstateoutput

Y

U?A

7408

1

23

U?A

7408

1

23

U?A7474

D2

CLK3

Q5

Q6

PR4

CL1

U?A7474

D2

CLK3

Q5

Q6

PR4

CL1

U?A

7432

1

23

A

CLK

F=1/0

0,1

3

2

1

0

0,1

Q1,Q0=00

States 1 and 3(Q0=1) are nolonger accessible

01

10

11

Q1

Q0


11

Ad hoc testability improvements• Design rules or amendments to avoid or

minimise test vector generation problems

• Major drawbacks:– Not always reusable– Testability depends largely on the type of

circuit


12

Some ad hoc testability rules• Split counters to avoid high numbers of

clock cycles until the required output combination is achieved

• Include reset and preset lines (synchronous or asynchronous)

• Partition large circuits and add extra inputs and outputs for direct controllability and observability of internal nodes


13

Structured Design for Testability (DfT)• Structured DfT methodologies enable a

simple way to drive the circuit to any given state in a fixed (and short) number of clock cycles

• Does structured DfT have drawbacks?– Design rules (design styles) have to accepted– Additional silicon area, more pins and higher

propagation delays… but is this an additional cost?


14

The scan design principle

VCC_BAR

VCC_BAR

VCC_BAR

VCC_BAR

VCC_BAR

VCC_BAR

2:1 mux

Test Mode10

0

1Test Mode

2:1 mux

0

1

Test Mode

2:1 mux

Presentstate Next

state

Nextstate

Nextstate

Presentstate

Presentstate

SCAN OUT

CLOCKSCAN INTEST MODE

U?A7474

D2

CLK3

Q5

Q6

PR4

CL1

U?A7474

D2

CLK3

Q5

Q6

PR4

CL1

U?A7474

D2

CLK3

Q5

Q6

PR4

CL1

• The scan design principle consists of inserting a 2:1 multiplexer between the input of every D flip-flop and its driving logic


15

Scan design advantages (1)

• Problem: Part of the combinational circuit inputs are not directly controllable, since they come from the D-FF outputs (these nodes define the present state of the circuit)

• Solution: Scan flip-flops enable direct controllability of the D-FF outputs through a simple procedure with a fixed number of clock cycles


16

Better controllability through scan design (1)

VCC_BAR

VCC_BAR

VCC_BAR

VCC_BAR

VCC_BAR

VCC_BAR

1

1

Test Mode

1Nextstate

0

02:1 mux

1

0

Test Mode

1

0

0

Nextstate

Test Mode

Presentstate

Presentstate

Nextstate

2:1 mux

Presentstate

1

0

1

0

2:1 mux

0

U?A7474

D2

CLK3

Q5

Q6

PR4

CL1

U?A7474

D2

CLK3

Q5

Q6

PR4

CL1

U?A7474

D2

CLK3

Q5

Q6

PR4

CL1

TEST MODE CLOCKSCAN IN

SCAN OUT

Since the Test Mode control signal is at 0,

each clock cycle will transfer to the D-FF

outputs the values present at the next

state nodes.

ExampleTake the circuit to state 110, starting from state 100 (intrusive)


17


VCC_ BAR

VCC_ BAR

VCC_ BAR

VCC_ BAR

VCC_ BAR

VCC_ BAR

Presentstate

Test Mode

1?

Nextstate

2:1 mux

Presentstate

Nextstate

1

?

2:1 mux

10

0

0Nextstate

Test Mode

1

0

0

1 1

0

Test Mode

2:1 mux?

Presentstate

TEST MODE CL OCK

SCAN OUT

SCAN IN

U? A7 4 7 4

D2

CL K3

Q5

Q6

PR4

CL1

U? A7 4 7 4

D2

CL K3

Q5

Q6

PR4

CL1

U? A7 4 7 4

D2

CL K3

Q5

Q6

PR4

CL1

The Test Mode control signal is now at 1

and the D-FFs are connected as a shift-

register. The first clock cycle applied will

shift the D-FFs one bit position “up” and

transfer the value present at the Scan In

input to the output of the first D-FF in the

chain.

The values shown at each node are those

following the application of the first clock

cycle with Scan In at 1.


18


VCC_ BAR

VCC_ BAR

VCC_ BAR

VCC_ BAR

VCC_ BAR

VCC_ BAR

Presentstate

Test Mode

1?

Nextstate

2:1 mux

Presentstate

Nextstate

1

?

2:1 mux

10

0

0Nextstate

Test Mode

1

1

0

1 1

0

Test Mode

2:1 mux?

Presentstate

U? A7 4 7 4

D2

CL K3

Q5

Q6

PR4

CL1

U? A7 4 7 4

D2

CL K3

Q5

Q6

PR4

CL1

U? A7 4 7 4

D2

CL K3

Q5

Q6

PR4

CL1

TEST MODE CL OCK

SCAN OUT

SCAN IN

The values shown at each node are now

those following the application of the

second clock cycle, keeping Scan In at 1.

Notice that the initial present state

values are being shifted out

simultaneously as the new present state

is being shifted in.


19


VCC_ BAR

VCC_ BAR

VCC_ BAR

VCC_ BAR

VCC_ BAR

VCC_ BAR

1

2:1 mux

1

1Nextstate

Presentstate

Test Mode

Nextstate

0

2:1 mux0

Test Mode

02:1 mux

Presentstate

1

Nextstate

1

?

?

Test Mode

Presentstate

1

0

0

?

1

U? A7 4 7 4

D2

CL K3

Q5

Q6

PR4

CL1

U? A7 4 7 4

D2

CL K3

Q5

Q6

PR4

CL1

U? A7 4 7 4

D2

CL K3

Q5

Q6

PR4

CL1

SCAN IN CL OCKTEST MODE

SCAN OUT

The last clock cycle has now been applied

with the Scan In input set at 0, so the new

present state is 110 as requested.

Three clock cycles were therefore

necessary to take the circuit to its new

present state, the general rule being that

the number of clock cycles required is

equal to the number of D-FFs.


20


VCC_ BAR

VCC_ BAR

VCC_ BAR

VCC_ BAR

VCC_ BAR

VCC_ BAR

1

1

Test Mode

1Nextstate

0

02:1 mux

?

?

Test Mode

1

0

1

Nextstate

Test Mode

Presentstate

Presentstate

Nextstate

2:1 mux

Presentstate

1

0

X

?

2:1 mux

0

U? A7 4 7 4

D2

CL K3

Q5

Q6

PR4

CL1

U? A7 4 7 4

D2

CL K3

Q5

Q6

PR4

CL1

U? A7 4 7 4

D2

CL K3

Q5

Q6

PR4

CL1

TEST MODE SCAN IN

SCAN OUT

CL OCK

The requested present state has been

loaded and the Test Mode control signal

has been taken back to 0.

Each next state node is now connected to

the respective D-FF input and is defined

by the combinational logic block

according to present state 110 and to the

current values at the (external) circuit

primary inputs.


21

Scan design advantages (2)

• Problem: Part of the combinational circuit outputs are not directly observable, since they go to the D-FF inputs (these nodes define the circuit next state)

• Solution: Scan flip-flops enable direct observability of the D-FF inputs through a simple procedure with a fixed number of clock cycles


22

Better observability through scan design (1)

VCC_ BAR

VCC_ BAR

VCC_ BAR

VCC_ BAR

VCC_ BAR

VCC_ BAR

1

1

Test Mode

1Nextstate

0

02:1 mux

1

0

Test Mode

1

0

0

Nextstate

Test Mode

Presentstate

Presentstate

Nextstate

2:1 mux

Presentstate

1

0

1

0

2:1 mux

0

U? A7 4 7 4

D2

CL K3

Q5

Q6

PR4

CL1

U? A7 4 7 4

D2

CL K3

Q5

Q6

PR4

CL1

U? A7 4 7 4

D2

CL K3

Q5

Q6

PR4

CL1

TEST MODE CL OCKSCAN IN

SCAN OUT

The initial circuit conditions are the same

as in the previous example, the present

state being 100.

The 2:1 multiplexers have their Test

Mode control signal at 0 and are therefore

in “transparent” mode.

ExampleObserve the next state (eventually non-intrusive)


23


VCC_ BAR

VCC_ BAR

VCC_ BAR

VCC_ BAR

VCC_ BAR

VCC_ BAR

?

X

Presentstate

0

1

2:1 mux

Test Mode

Presentstate

?

0

0

Presentstate

1

1

Test Mode10

Nextstate

Test Mode

0?

Nextstate

Nextstate

2:1 mux0

0

2:1 mux

U? A7 4 7 4

D2

CL K3

Q5

Q6

PR4

CL1

U? A7 4 7 4

D2

CL K3

Q5

Q6

PR4

CL1

U? A7 4 7 4

D2

CL K3

Q5

Q6

PR4

CL1

SCAN OUT

SCAN IN CL OCKTEST MODE

The values shown at each node are those

following the application of the first clock

cycle. Since the Test Mode control signal

was kept at 0, the values transferred to

the D-FF outputs were those present in

the next state nodes, defined by the

(internal) outputs of the combinational

logic block. Notice that the value present

at the Scan Out output is now the first bit

to be shifted out.


24


VCC_BAR

VCC_BAR

VCC_BAR

VCC_BAR

VCC_BAR

VCC_BAR

Presentstate

Test Mode

X?

Nextstate

2:1 mux

Presentstate

Nextstate

1

?

2:1 mux

10

0

0Nextstate

Test Mode

1

1

0

1 X

0

Test Mode

2:1 mux?

Presentstate

TEST MODE CLOCK

SCAN OUT

SCAN IN

U?A7474

D2

CLK3

Q5

Q6

PR4

CL1

U?A7474

D2

CLK3

Q5

Q6

PR4

CL1

U?A7474

D2

CLK3

Q5

Q6

PR4

CL1

The Test Mode control signal was now set

to 1 and the values shown at each node

are those following the application of the

second clock cycle. Since the D-FFs are

now connected as a shift-register, the

present state nodes were shifted one bit

position “up” and the second bit was

shifted out.


25


VCC_ BAR

VCC_ BAR

VCC_ BAR

VCC_ BAR

VCC_ BAR

VCC_ BAR

Presentstate

Test Mode

X?

Nextstate

2:1 mux

Presentstate

Nextstate

1

?

2:1 mux

10

1

0Nextstate

Test Mode

1

X

0

1 X

Test Mode

2:1 mux?

Presentstate

1

TEST MODE CL OCK

SCAN OUT

SCAN IN

U? A7 4 7 4

D2

CL K3

Q5

Q6

PR4

CL1

U? A7 4 7 4

D2

CL K3

Q5

Q6

PR4

CL1

U? A7 4 7 4

D2

CL K3

Q5

Q6

PR4

CL1

The values now shown are those following

the application of the third (and last)

clock cycle. The last bit (the rightmost bit

in the initial 001 next state) was now

shifted out.

Notice that only two clock cycles were

required after the Test Mode control

signal was set to 1, since the first bit is

immediately present at the Scan Out

output.


26


VCC_ BAR

VCC_ BAR

VCC_ BAR

VCC_ BAR

VCC_ BAR

VCC_ BAR

1

1

Test Mode

1Nextstate

0

02:1 mux

?

?

Test Mode

1

X

X

Nextstate

Test Mode

Presentstate

Presentstate

Nextstate

2:1 mux

Presentstate

1

0

X

?

2:1 mux

0

U? A7 4 7 4

D2

CL K3

Q5

Q6

PR4

CL1

U? A7 4 7 4

D2

CL K3

Q5

Q6

PR4

CL1

U? A7 4 7 4

D2

CL K3

Q5

Q6

PR4

CL1

TEST MODE CL OCKSCAN IN

SCAN OUT Setting the Test Mode control signal to 0

brings the circuit back to the normal

operation mode.

The present state was modified as defined

by the values shifted in and the next

state values were modified accordingly.

Notice however that the initial present

state might have been kept…how?


27

DfT: Eventually an overhead

• The 2:1 muxs increase the propagation delay and require additional silicon area and pins, but will this increase cost?

• How do we quantify the benefits of easier test vector generation and application?

• Design freedom was traded for higher testability, but partial scan design might be a preferred intermediate solution

leonardo da vinci allegro © j. m. martins ferreira - university of porto (feup / deec)1 scan design...

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