dr a sahu dept of comp sc & engg. iit guwahati. i/o port addressing uart port basic – 16500...
TRANSCRIPT
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Serial Port / UART of Modern Desktop Board & its Linux
programming
Dr A SahuDept of Comp Sc & Engg.
IIT Guwahati
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Outline• I/O Port Addressing • UART Port Basic –16500 Standardized UART
• UART Programming in C• Loop back program
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IO Port Addressing
• Standardized • Use command – $ cat /proc/ioports
0170-0177 : 0000:00:14.1 0170-0177 : pata_atiixp01f0-01f7 : 0000:00:14.1 01f0-01f7 : pata_atiixp0200-020f : pnp 00:090220-0233 : pnp 00:090240-0253 : pnp 00:090260-0273 : pnp 00:090280-0293 : pnp 00:09
02f8-02ff : serial
0000-001f : dma10020-0021 : pic10040-0043 : timer00050-0053 : timer10060-0060 : keyboard0064-0064 : keyboard0070-0071 : rtc00080-008f : dma page reg00a0-00a1 : pic200c0-00df : dma200f0-00ff : fpu
0376-0376 : 0000:00:14.1 0376-0376 : pata_atiixp0378-037a : parport00388-0389 : pnp 00:0903c0-03df : vga+03f6-03f6 : 0000:00:14.1 03f6-03f6 : pata_atiixp
03f8-03ff : serial040b-040b : pnp 00:0904d0-04d1 : pnp 00:09
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IOPL
• IO Privilege level– Can be set by root
• If set user can RW to Ios• Loopback user C/C++ program can access
Modem/UART at address 03F8
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Type of Serial Communication• Synchronous – Sender and receiver must synchronize • Done in hardware using phase locked loops (PLLs)
– Block of data can be sent – More efficient : Less overhead than asynchronous
transmission – Expensive
• Asynchronous – Each byte is encoded for transmission • Start and stop bits
– No need for sender and receiver synchronization
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Type of Serial Communication
Sender
Sender
Receiver
ReceiverData Data Data Data Data
Data Data Dataa
Transmission Gaps
Asynchronous transmission
Synchronous transmission
CLK
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Framing in Asynchronous
• Character oriented • Each character carried start bit and stop bits • When No data are being transmitted – Receiver stay at logic 1 called mark, logic 0 is Space
• Framing: – Transmission begins with one start bit (low/0)– Followed by DATA (8bit) and – Stop bits (1 or 2 bits of logic high)
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Type of Serial CommunicationAsynchronous transmission
8 bit Data
Start Bit Start Bits
1 0 0 0 1 1 1 0 LSB MSB
Time
1 startbit
1 or 2 StopbitSource data
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Using ‘echo’ and ‘cat’
• Your device-driver module (named ‘uart.c’) is intended to allow unprivileged programs that are running on a pair of adjacent PCs to communicate via a “null-modem” cable
$ echo Hello > /dev/uart$ _ $ cat /dev/uart
Hello _
Receiving…Transmitting…
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Tx and Rx
• The UART has a transmission-engine, and also a reception-engine, which are able to operate simultaneously (i.e., “full-duplex”)
• Software controls the UART’s operations by accessing several registers, using the x86 processor’s ‘in’ and ‘out’ instructions
• Linux provides some convenient ‘macros’ that ‘hide’ the x86 machine-code details
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Linux char-driver components
init
exit
fops
function
function
function
. . .
Device-driver LKM layout
registers the ‘fops’
unregisters the ‘fops’
module’s ‘payload’ is a collection of callback-functions having prescribed prototypes AND
a ‘package’ of function-pointers
the usual pair of module-administration functions
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Requires a device-file node
• Our System Administrator has created the device-file needed for your driver-module:root# mknod /dev/uart c 84 0 root# chmod a+w /dev/uart
• Your driver-module needs to ‘register’ your package of driver-methods (i.e., functions) in its initialization routine (and ‘unregister’ them later in its cleanup routine)
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Serial data-transmission
0 1 1 0 0 0 0 1
The Transmitter Holding Register (8-bits)
0 1 1 0 0 0 0 1
The transmitter’s internal ‘shift’ register
clock
Software outputs a byte of data to the THR
The bits are immediately copied into an internal ‘shift’-register
The bits are shifted out, one-at-a-time, in sync with a clock-pulse
1-0-1-1-0-0-0-0-1-0
start bit
stop bit
data-bits
clock-pulses trigger bit-shifts
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‘write()’ and ‘read()’
• Obviously your driver-module’s ‘payload’ will have to include ‘methods’ (functions) which perform the ‘write()’ and ‘read()’ operations that applications will invoke
• You may decide your driver needs also to implement certain additional ‘methods’
• A little history is helpful for understanding some of the UART device’s terminology
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Serial data reception
clock
input voltage
clock-pulses trigger voltage-sampling and bit-shifts at regular intervals
0 1 1 0 0 0 0 1
The receiver’s internal ‘shift’ register
1-0-1-1-0-0-0-0-1-0
start bit
stop bit
data-bits
0 1 1 0 0 0 0 1
The Receiver Buffer Register (8-bits)
Software can input the received byte from the RBR
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8251 Block Diagram
Data Bus Buffer
TransmitBuffer
Receive Buffer
TransmitControl
Receive Control
R/W Control
Logic
Modem Control
Internal
Line
D7-D0
RESETCLKC/Db
RDb
WRb
CSb
DSRb
DTRb
CTSb
RTSb
TXD
TXRDYTXETXC
RXD
RXRDYRXCSYBDET/BD
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Transmitter and Receiver
Data Buffer
Register
D0
D7
Internal
Data Bus
Transmitter Buffer
Register
Receiver Buffer
Register
Out put Register
InputRegister
Transmitter Control Logic
Receiver Control Logic
TxD
TxCb
TxRDYTxE
RxD
RxCb
RxRDY
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Command Register(Command Word Format)
EH IR RTS ER SBRK RxE DTR TxE
TxE: transmit enable (0/1 Enable Disable)DTR: data terminal ready (1=ENABLE DTR)RxE: receiver enable (1/0=EN/DISABLE)SBPRK: send break character 1= force TxD lowER: error reset (Reset Flags: Parity ,Over run,
Framing Error of Status Word)RTS: request to send (1= Enable Request to send)IR: internal reset (Reset 8251 to mode)EH: enter hunt mode (1=search for Sync Character)
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8251: Status Regsiter
DSR SYNDET FE OE PE Tx
EMPTYRxRDY TxRDY
TxRDY transmit ready (DB Buffer is empty)RxRDY receiver ready TxEMPTY transmitter emptyPE parity error (1=when PE detected)OE overrun errorFE framing error (Aynsc only, Valid stop bit
not detected)SYNDET sync. character detectedDSR data set ready (DSR set at 0 level)
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PC Standard UART (16550) Registers
Transmit Data Register
Received Data Register
Interrupt Enable Register
Interrupt Identification Register
FIFO Control Register
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register
Scratch Pad Register
Divisor Latch Register 16-bits (R/W)
8-bits (Write-only)
8-bits (Read-only)
8-bits (Read/Write)
8-bits (Read-only)
8-bits (Write-only)
8-bits (Read/Write)
8-bits (Read/Write)
8-bits (Read-only)
8-bits (Read-only)
8-bits (Read/Write)
Base+0
Base+0
Base+1
Base+2
Base+2
Base+3
Base+4
Base+5
Base+6
Base+7
Base+0
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Rate of data-transfer
• The standard UART clock-frequency for PCs equals 1,843,200 cycles-per-second
• Each data-bit consumes 16 clock-cycles • So the fastest serial bit-rate in PCs would be
1843200/16 = 115200 bits-per-second• With one ‘start’ bit and one ‘stop’ bit, ten bits
are required for each ‘byte’ of data• Rate is too fast for ‘teletype’ terminals
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Divisor Latch
• The ‘Divisor Latch’ may be used to slow down the UART’s rate of data-transfer
• Clock-frequency gets divided by the value programmed in the ‘Divisor Latch’ register
• Older terminals often were operated at a ‘baud rate’ of 300 bits-per-second (which translates into 30 characters-per-second)
• So Divisor-Latch set to 0x0180
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How timing works
Transmitter clock (bit-rate times 16)
DATA OUT
start-bit data-bit 0 data-bit 1 …
receiver detects this high-to-low transition, so it waits 24 clock-cycles, then samples the data-line’s voltage every 16 clock-cycles afterward
24 clock-cycles 16 clock-cycles 16 clock-cycles
Receiver clock (bit-rate times 16)
sample sample
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Programming interface
RxD/TxD IER IIR/FCR LCR MCR LSR MSR SCR
The PC uses eight consecutive I/O-ports to access the UART’s registers
0x03F8 0x03F9 0x03FA 0x03FB 0x03FC 0s03FD 0x03FE 0x03FF
scratchpad register
modem statusregister
line statusregister
modem controlregister
line controlregister
interrupt enableregister
interrupt identification register and FIFO control register
receive buffer register and transmitter holding register(also Divisor Latch register)
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Modem Control Register
0 0 0 LOOPBACK OUT2 OUT1 RTS DTR
7 6 5 4 3 2 1 0
Legend: DTR = Data Terminal Ready (1=yes, 0=no) RTS = Request To Send (1=yes, 0=no) OUT1 = not used (except in loopback mode) OUT2 = enables the UART to issue interrupts LOOPBACK-mode (1=enabled, 0=disabled)
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Modem Status Register
DCD RI DSR CTS deltaDCD
deltaRI
deltaDSR
deltaCTS
7 6 5 4 3 2 1 0
set if the corresponding bit has changed since the last time this register was read
Legend: [---- loopback-mode ----] CTS = Clear To Send (1=yes, 0=no) [bit 0 in Modem Control] DSR = Data Set Ready (1=yes, 0=no) [bit 1 in Modem Control] RI = Ring Indicator (1=yes,0=no) [bit 2 in Modem Control] DCD = Data Carrier Detected (1=yes,0=no) [bit 3 in Modem Control]
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Line Status Register
Error inRx FIFO
TXmitteridle
THRempty
Breakinterrupt
Framingerror
Parityerror
Overrunerror
ReceivedData
Ready
7 6 5 4 3 2 1 0
These status-bits indicate errors in the received data
This status-bit indicates that a new byte of data has arrived(or, in FIFO-mode, that the receiver-FIFO has reached its threshold)
This status-bitindicates that thedata-transmission has been completed
This status-bit indicates that the Transmitter Holding Register is ready to accept a new data byte
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Line Control Register
DivisorLatchaccess
setbreak
stickparity
even parityselect
parityenable
numberof stop
bits
word lengthselection
7 6 5 4 3 2 1 0
00 = 5 bits01 = 6 bits10 = 7 bits11 = 8 bits
0 = 1 stop bit1 = 2 stop bits
0 = no parity bits1 = one parity bit
1 = even parity0 = ‘odd’ parity
0 = not accessible1 = assessible
0 = normal1 = ‘break’
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Interrupt Enable Register
0 0 0 0ModemStatuschange
Rx LineStatuschange
THRis
empty
Receiveddata is
available
7 6 5 4 3 2 1 0
If enabled (by setting the bit to 1),the UART will generate an interrupt:(bit 3) whenever modem status changes(bit 2) whenever a receive-error is detected (bit 1) whenever the transmit-buffer is empty(bit 0) whenever the receive-buffer is nonempty
Also, in FIFO mode, a ‘timeout’ interrupt will be generated if neither FIFO has been ‘serviced’ for at least four character-clock times
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FIFO Control Register
RCVR FIFOtrigger-level
reserved reservedDMAModeselect
XMITFIFOreset
RCVRFIFOreset
FIFOenable
7 6 5 4 3 2 1 0
Writing 0 will disable the UART’s FIFO-mode, writing 1 will enable FIFO-mode
Writing 1 empties the FIFO, writing 0 has no effect
00 = 1 byte01 = 4 bytes10 = 8 bytes11 = 14 bytes
Mode: If supported DMA
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Interrupt Identification Register
0 0
7 6 5 4 3 2 1 0
00 = FIFO-mode has not been enabled 11 = FIFO-mode is currently enabled
1 = No UART interrupts are pending0 = At least one UART interrupt is pending
‘highest priority’ UART Interrupt still pending
highest 011 = receiver line-status 010 = received data ready 100 = character timeout 001 = Tx Holding Reg empty 000 = modem-status changelowest
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Responding to interrupts
• You need to ‘clear’ a reported interrupt by taking some action -- depending on which condition was the cause of the interrupt:– Line-Status: read the Line Status Register– Rx Data Ready: read Receiver Data Register – Timeout: read from Receiver Data Register– THRE: read Interrupt Identification Register or
write to Transmitter Data Register (or both)– Modem-Status: read Modem Status Register
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Usage flexibility
• A UART can be programmed to operate in “polled” mode or in “interrupt-driven” mode
• While “Polled Mode” is simple to program• It does not make efficient use of the CPU in
situations that require ‘multitasking’ (as the CPU is kept busy doing “polling” of the UART’s status instead of useful work
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How to transmit a byte
Read the Line Status Register
Write byte to the Transmitter Data Register
Transmit Holding Registeris Empty?NO
YES
DONE
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How to receive a byte
Read the Line Status Register
Read byte from the Receiver Data Register
Received Datais Ready?NO
YES
DONE
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How to implement in C/C++// declare the program’s variables and constantschar inch, outch = ‘A’;// --------------------- Transmitting a byte -------------------// wait until the Transmitter Holding Register is empty, // then output the byte to the Transmit Data Register do { } while ( (inb( LINE_STATUS) & 0x20) == 0 );outb( outch, TRANSMIT_DATA_REGISTER );
// ---------------------- Receiving a byte ------------------------// wait until the Received Data Ready bit becomes true, // then input a byte from the Received Data Registerdo { } while ( (inb( LINE_STATUS ) & 0x01 ) == 0 );inch = inb( RECEIVED_DATA_REGISTER );
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How to initialize ‘loopback’ mode
Set the Divisor Latch Access Bitin the Line Control Register
Write a nonzero value to the Divisor Latch Register
Clear the Divisor Latch Access Bitand specify the desired data-format
in the Line Control Register
Set the Loopback bitin the Modem Control Register
DONE
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How to adjust the cpu’s IOPL • IO Privilege Level• Linux provides a system-call to privileged
programs which need to access I/O ports• The <sys/io.h> header-file prototypes it, and
the ‘iopl()’ library-function invokes it • The kernel will modify the CPU’s current I/O
Permission Level in cpu’s EFLAGS (if the program’s owner has ‘root’ privileges)
• First execute our ‘iopl3’ command • Use Root mode to do this
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Loop-Back Experiment
• Download and run our ‘testuart.cpp’ demo• It uses the UART’s ‘loopback’ test mode to
‘receive’ each character that it ‘transmits’
TxData
RxData
TxShiftReg
RxShiftReg
UART ‘loopback’ mode
The external signal-lines are bypasedOutput loops back to become input
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Loop Back Program: uarttest.cpp#define UART_PORT 0x03F8 // base port-address for the UART#define DIVISOR_LATCH (UART_PORT + 0)#define TX_DATA_REG (UART_PORT + 0)#define RX_DATA_REG (UART_PORT + 0)#define LINE_CONTROL (UART_PORT + 3)#define MODEM_CONTROL (UART_PORT + 4)#define LINE_STATUS (UART_PORT + 5)char msg[] = "\n\tThis is a test of the UART's loopback mode\n";int main( int argc, char **argv ) {
// set the CPU's I/O Permission-Level to allow port-accessif ( iopl( 3 ) ) { perror( "iopl" ); exit(1); }
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Loop Back Program// establish the UART's operational parametersoutb( 0x80, LINE_CONTROL ); // set DLAB=1outw( 0x0001, DIVISOR_LATCH ); // set 11520 baudoutb( 0x03, LINE_CONTROL ); // set data-format: 8-N-1outb( 0x10, MODEM_CONTROL ); // turn on 'loopback' mode // write each message-character, read it back, and display itfor (int i = 0; i < sizeof( msg ); i++) {
do { } while ( (inb( LINE_STATUS )&0x20) == 0x00 );outb( msg[i], TX_DATA_REG );do { } while ( (inb( LINE_STATUS )&0x01) == 0x00 );int data = inb( RX_DATA_REG );printf( "%c", data );}
outb( 0x00, MODEM_CONTROL );// turn off 'loopback' mode printf( "\n" );
}
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Thanks