dsp board data bus timing
DESCRIPTION
DSP Board data bus timing. There are two types of data transfer within the DSP board: Lead by the DSP Lead by the VME master. A dedicated FPGA interfaces the VME bus and the DSP board. The signals used for Data transfer on the daughter cards are: Address, Data, Acknowledge, Read, Write - PowerPoint PPT PresentationTRANSCRIPT
22/11/2005 A. Blas 1
DSP Board data bus timing
There are two types of data transfer within the DSP board:• Lead by the DSP• Lead by the VME master. A dedicated FPGA interfaces the VME
bus and the DSP board.
The signals used for Data transfer on the daughter cards are:• Address, Data, Acknowledge, Read, Write
From the daughter card viewpoint, the address is decoded in two stages. The base address is decoded on a dedicated FPGA on the motherboard that supplies the SELN bit. The offset address is decoded on the daughter card FPGA. The SELN bit is thus delayed (T1) with respect to the offset address change.
22/11/2005 A. Blas 2
DSP Board data bus timing
VALIDOFFSET
ADDRESS
VALIDBASE ADDRESS
OR SELN
VALIDGLOBAL
ADDRESSDECODER
Delay of SELN decoder onmother board (18 ns?)
DSP RDH-L
DSP WRH-LDSP READING
BUS
DSP RDH-L
DSP WRH-LDSP WRITINGONTO BUS
DATA VALID
RELEASE DATA + ACKN ON BUS
ACQUIRE DATARELEASE ACKN
DSP RDH-L
DSP WRH-L
VME READINGBUS
25 ns - 2 Tpd inVME interface
RELEASE DATA + ACKN ON BUS
DSP RDH-L
DSP WRH-LVME WRITINGONTO BUS
25 ns - 2 Tpd inVME interface
RELEASE ACKN ON BUSACQUIRE DATA
NON VALID
VALID
VALIDFALSE
NON VALID
VALID
VALIDFALSE
NON VALIDNON VALID
22/11/2005 A. Blas 3
PROBLEM: As the base address is delayed (T1) with respect to offset address, what tells us when the address is really valid?
Making the product of the 2 decoders (base and offset) might give false information before and after the actual addressing (see p.2)
Enabling the decoder output when both base and offset addresses are decoded for longer than T1 gives a valuable result at the beginning of the cycle, but can be fooled at the end.
Using the read/write signals to gate the address decoding doesn’t help as they might be active when the decoding is fooled.
Using the rising edge of read/write to reset the decoder at the end of the cycle could be ok if we knew how long to apply this reset. When the DSP is mastering the bus, only do we know that this time should be greater than 2.125ns+h*Tck, and when the VME is leading, either should it be negative! (VME reading) or not specified (DSP writing) (address pipelining mode should be taken into account; i.e.: the next address is sent before the end of the cycle.
Address decoding
22/11/2005 A. Blas 4
Attempt solution: use the falling edge of either read or write to start a timer. After a time T2 >T1 memorize the address decoder output to use it as bus-access-enable. Use then the leading edge of read/write to reset the bus access register.This method requires to program the DSP wait register such as to have W*25ns > T2.To make the circuit compatible with the present VME interface circuit, one needs also to fulfill T2 < 3*Tclk (Tclk being the clock used in the VME interface circuit = 25 ns)
Downside of this solution: with the present VME interface, the rising edge of RDH comes 2*Tpd (propagation time within the VME interface = 6 ns?) after the change of address when the VME is leading the bus. This might cause some conflicts on the bus.
Conclusion: I didn’t find yet a really proof solution with this addressing in two delayed parts. In the next revision of the mother board, this topic should be tackled.This easiest, may be, being to have all the bus components following the same track (delayed in the same way).
Address decoding
22/11/2005 A. Blas 5
Address Decoding circuit
CLRN
DPRN
Q
DFF
inst1
NOT
inst551
AND2
inst15
VALID ADDRESS DETECTOR
BUS_ACCESS_EN
OFFSET_ADDR_DECODED
BASE_ADDRESS_SELN_DLY
DELAY_COMPLETED
END_RW_CYCLE
NOT
inst543
PRN
CLRN
D
ENA
Q
DFFE
inst4
TRI
inst371
AND2
inst544
TRI
inst372
VC
C
or the data can be acquired on the rising edge of WRN (in DSP or VME write mode)
ACK
DSP_DATA[63..32]
RDN
DSP_DATA[63..32]
WRN
DATA_OUT[31..0]
BUS_ACCESS_EN
When the address is considered as validthe data can be launched (in Read mode) on the bus together with the acknowledge
I/O REGISTER
22/11/2005 A. Blas 6
Output register circuit
VCC
VCC
NOT
inst547
CLRN
DPRN
Q
DFF
inst9
CLRN
DPRN
Q
DFF
inst11
NOT
inst548
up counterclock
clk_en
aclr
q[1..0]
lpm_counter1
inst6
NOT
inst7
NOR2
inst16
WIRE
inst10
R/W FALLING EDGE DETECTOR
RDN
WRN
END_RW_CYCLE
END_RW_CYCLE
FAST_REF_CLK
COUNT_I[1]
COUNT_I[1] DELAY_COMPLETED
COUNT_I[1..0]
OU
T_R
W_C
YC
LEBASE ADDRESS DELAY COMPENSATION
The wait register in the DSP should take into account this delay by setting its wait register accordinglyW * Tclk-dsp > max delay = 2 * Tfast_ref_clk in this context
22/11/2005 A. Blas 7
Output I/Q register circuit
TRI
inst188
NOT
inst189
AND2
inst190
AND2
inst233
TRI
inst231
TRI
inst18
OR
2
inst
20
PRN
CLRN
D
ENA
Q
DFFE
inst19
PRN
CLRN
D
ENA
Q
DFFE
inst21
NOT
inst3
CLRN
DPRN
Q
DFF
inst11
NOT
inst191
CLRN
DPRN
Q
DFF
inst14
GN
D
CLRN
DPRN
Q
DFF
inst16CLRN
DPRN
Q
DFF
inst12NOT
inst192
RDN
ACK
DSP_DATA[63..32]
DSP_DATA[63..32]
DATA_SAMPLING_CLK
DATA_SAMPLING_CLK
I_IN[31..0]
DATA_SAMPLING_CLK
Q_IN[31..0]
DATA_SAMPLING_CLK
RDN
RDN
THE I AND Q VALUES RECORDED BY THE DSP SHOULD BELONG TO THE SAME TIME SAMPLE
THIS CIRCUIT PROVIDES THE VERY FIRST I-Q SAMPLE THAT FOLLOWS THE DSP READ REQUEST
AS THE RECORDING IS MADE IN TWO STAGES, FIRST I THEN Q, THE VALUE OF Q SHOULD BE MEMORIZED BEFORE BEING READ
AS SOON AS THE ADDRESS IS VALID, ACK IS SET TO ZERO (DATA NOT READY), BUT AT THE FOLLOWING SAMPLING CLOCK EDGE
WHERE THE I-Q DATA ARE FROZEN, THEN IS IT ACTIVATED.
I-Q SYNCHRONISATION CIRCUIT
BUS_ACCESS_EN_I
BUS_ACCESS_EN_Q
22/11/2005 A. Blas 8
DSP reading bus
> 0.25 TCORE CLOCK - 3ns> 0.125 ns
VALID
DSP /RDH-L
DSP input data
> TCK - 0.5 TCORE CLOCK - 1ns + W TCK> 17.8 ns + 25ns . W
< TCK - 0.5 TCORE CLOCK + W . TCK< 18.7 ns + 25 ns . W
< TCK - 0.25 TCORE CLOCK - 11ns + W TCK< 10.87 ns + 25 ns . W
> 0.25 TCORE CLOCK - 1ns + H TCK> 2.125 ns + (0/1) . 25 ns
> 0.5 TCORE CLOCK - 1ns + HI . TCK> 5.25 ns + 25 ns . (0/1)
> 8ns
> 1ns
> 0ns
DSP /WRH-L
ACK
DSP CLK INPUT40 MHz typ.
<10ns
High if OK
> 0.5 TCORE CLOCK + 3ns> 9.25 ns
> 1ns
< TCK - 0.5 TCORE CLOCK - 12ns + W . TCK< 6.75 ns + 25 ns . W
= 2 Tpd (on mother board FPGA) +3 ns= 18 nsSELN
decoding ofDSPADDR [31..15]
DSP ADDR [14..0]
22/11/2005 A. Blas 9
DSP writing onto bus
> 0.25 TCORE CLOCK - 3ns> 0.125 ns
VALID
DSP /WRH-L
DSP output data
> TCK - 0.5 TCORE CLOCK - 1ns + W TCK> 17.8 ns + 25ns . W
> 0.25 TCORE CLOCK + 1ns> 4.13 ns
> TCK - 0.5 TCORE CLOCK - 1ns + W TCK> 17.8 ns + 25 ns . W
> 0.25 TCORE CLOCK - 1ns + H TCK> 2.125 ns + (0/1) . 25 ns
> 0.5 TCORE CLOCK - 1ns + HI . TCK> 5.25 ns + 25 ns . (0/1)
> TCK - 0.25 TCORE CLOCK - 3ns + W TCK> 18.87 ns + 25 ns . W
> 0.25 TCORE CLOCK - 2ns + H TCK> 1.125 ns + (0/1) . 25 ns< 0.25 TCORE CLOCK + 2ns + H TCK< 5.125 ns + (0/1) . 25 ns
> 0.25 TCORE CLOCK - 1ns + H TCK> 2.125 ns + (0/1) . 25 ns
> 0.25 TCORE CLOCK - 1ns + I.TCK> 2.125 ns + (0/1) . 25 ns
DSP /RDH-L
ACK
<10ns
High if OK
> 0.5 TCORE CLOCK + 3ns> 9.25 ns
> 1ns
< TCK - 0.5 TCORE CLOCK - 12ns + W . TCK< 6.75 ns + 25 ns . W
SELNdecoding of
DSPADDR [31..15]
= 2 Tpd (on mother board FPGA) +3 ns= 18 ns
DSP CLK INPUT40 MHz typ.
DSP ADDR [14..0]
22/11/2005 A. Blas 10
VME reading Bus
VALID VALID
A01-A31AM0-AM5LWORD*
IACK*
AS*
WRITE*
DS0*
DS1*
VALIDD00-D31
DTACK*BERR*
RETRY*
> 10 ns
MASTER’sACTION
EXPECTEDSLAVES’sACTION
VALID
2 * Tpd in VME interface
Within 1 Tck
DSP RDH
> 0 ns
2 * Tpd in VME interface3 * Tck
DTACKcreate by
VME interface
DSP ADDR [31..0]
The Master drives A01-A31, AM0-AM5, LWORD*. These are qualified by the falling edge of the address strobe AS*.He also negates WRITE* and asserts DS0* and DS1*
The Slave places the data onto D00-D31 and asserts Data Transfer Acknowledge DTACKN*When the Master has latched the data, it informs the Slave by negating DS0* and DS1*.
The Slave then negates DTACK* and the cycle is terminated.
22/11/2005 A. Blas 11
VME writing onto bus
VALID VALID
A01-A31AM0-AM5LWORD*
IACK*
AS*
WRITE*
DS0*
DS1*
VALIDD00-D31
DTACK*BERR*
RETRY*
MASTER’sACTION
EXPECTEDSLAVES’sACTION
VALIDDSP ADDR [31..0]
2 * Tpd in VME interface
1 Tck = 25 ns
DSP WRH
> 10 ns
> 0 ns
2 * Tpd in VME interface
3 * Tck = 75 ns
DTACKcreate by
VME interface
The Master drives A01-A31, AM0-AM5, LWORD*. These are qualified by the falling edge of the address strobe AS*.He also asserts WRITE* and places the data onto D00-D31 before asserting DS0* and DS1*
Once the Slave asserts the Data Transfer Acknowledge DTACK* to show that the data are latched, the Master can reset WRITE* and change the address.
The Slave can assert DTACKN*, or BERR* (Bus Error in case of an abnormal cycle), or RETRY* in case the slave is busy.