dynamic current mirror active pixel image sharpness sensor by

Dynamic Current Mirror Active Pixel Image Sharpness Sensor

BY

PULLA REDDY AILURI, B.E.

A technical report submitted to the Graduate School

in partial fulfillment of the requirements

for the degree

Master of Science in Electrical Engineering

New Mexico State University

Las Cruces, New Mexico

December 2008

“Dynamic Current Mirror Active Pixel Image Sharpness Sensor,” a technical report

prepared by PULLA REDDY AILURI in partial fulfillment of the requirements for

the degree, Master of Science in Electrical Engineering, has been approved and

accepted by the following:

Linda LaceyDean of the Graduate School

Paul M. FurthChair of the Examining Committee

Date

Committee in charge:

Dr. Paul M. Furth, Chair

Dr. Steven Stochaj

Dr. Jeffrey S. Beasley

ii

DEDICATION

Dedicated to Dr Paul M. Furth and Aditya Rayankula.

iii

ACKNOWLEDGMENTS

First of all, I should thank God for all his blessings and guidance throughout

my life. I would like to thank and pay my regards to my advisor Dr. Paul M. Furth

for his constant support, guidance, encouragement and faith in me throughout my

graduate studies. I have learnt a lot from him both technically and professionally.

I would like to acknowledge Dr. Steven Stochaj and Dr. Jeffrey S. Beasley

for agreeing to be on my defense committee. I also want to thank RASEM -Squared

for supporting me with a graduate research assistantship for four semesters.

I want to say special thanks to Dr. David Voelz, Dr. Sang-Yeon Cho and

Glory Swathi for helping me in optical testing of the sensor. I appreciate all their

time and support. I feel fortunate to have made many good friends, too many to

mention here, during my stay in Las Cruces.

Finally, my deepest gratitude goes to my parents, my sisters, my brothers-

in-law and ever caring Deepu who have been a constant source of unconditional

love, patience and understanding.

iv

VITA

2001-2005 B. E. in Electronics and Communication,Osmania University, India

2006-2008 Graduate Research Assistant, Regional Alliance for Science, Engineering,& Mathematics - Squared, NMSU, Las Cruces, NM.

2008 Graduate teaching assistant, Klipsch Schoolof Electrical Engineering, NMSU, Las Cruces, NM.

Field of Study

Major Field: Electrical EngineeringMicroelectronics/VLSI

v

ABSTRACT

Dynamic Current Mirror Active Pixel Image Sharpness Sensor

BY

PULLA REDDY AILURI, B.E.

Master of Science in Electrical Engineering

New Mexico State University

Las Cruces, New Mexico, 2008

Dr. Paul M. Furth, Chair

Date and Time: December 8th, 2008 at 1:00pm

Location: Goddard Annex Room 148

In real-time adaptive optics systems, model-free optimization is a commonly-

used technique to compensate for the optical wavefront aberrations that are induced

by atmospheric turbulences. In this type of adaptive optics system, a scalar system

performance metric is optimized for wavefront correction. One of the most widely

used system performance metrics is image sharpness. A sharpness sensor that gives

an accurate and instantaneous estimation of image sharpness is vital to compensate

for wavefront aberrations in real time. A new image sharpness sensor, the CMOS

vi

dynamic current mirror active pixel sharpness sensor, that can provide the system

performance metric accurately and instantaneously is implemented in this project.

A novel active pixel structure is used in the design of this sensor. The sensor

output is charge integration time. From the integration time, image sharpness can

be estimated. Because of active pixel technology, the sensor can operate at low

illumination levels and high speeds. The integration time is a 10-bit digital number,

which makes off-chip image processing faster. The sensor is designed in the AMI

0.5-µm process and the total area of the chip is 1.5mm by 1.5mm. The power

supply used is 3.0V. The clock rate is 1MHz and the frame rate is 100kHz.

vii

TABLE OF CONTENTS

LIST OF FIGURES xi

1 INTRODUCTION 1

2 FUNDAMENTALS OF ADAPTIVE OPTICS AND IMAGE SENS-ING 3

2.1 Adaptive Optics Systems . . . . . . . . . . . . . . . . . . . . . . . . 4

2.2 Performance Metrics . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2.1 Square-Law Image Sharpness Metric (SLISM) . . . . . . . . 7

2.3 CMOS Image Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.3.1 Image Sensor Technology . . . . . . . . . . . . . . . . . . . . 8

2.3.2 Solid-State Phototransconduction . . . . . . . . . . . . . . . 12

2.3.3 Photodiode: Charge Integration Voltage Mode . . . . . . . . 16

2.3.4 CMOS Photodiodes . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.5 CMOS Image Sensors . . . . . . . . . . . . . . . . . . . . . . 19

2.4 CMOS Active Pixel Image Sharpness Sensor . . . . . . . . . . . . . 23

2.4.1 Dynamic Current Mirrors . . . . . . . . . . . . . . . . . . . 26

3 IMAGE SHARPNESS SENSOR VLSI IMPLEMENTATIONS: AR-CHITECTURE, DESIGN AND SIMULATION 28

3.1 Dynamic Current Mirror Active Pixel Image Sharpness Sensor . . . 28

viii

3.1.1 Pixel Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.1.2 Bias Voltage Circuit . . . . . . . . . . . . . . . . . . . . . . 36

3.1.3 Current Comparator . . . . . . . . . . . . . . . . . . . . . . 36

3.1.4 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.1.5 Output Register . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.1.6 Control Circuitry . . . . . . . . . . . . . . . . . . . . . . . . 45

3.1.7 Dynamic current mirror Active Pixel Image Sharpness SensorMetric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.1.8 4x4 Array Simulation Responses . . . . . . . . . . . . . . . . 52

4 ELECTRICAL AND OPTICAL TESTING 58

4.1 Electrical Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4.1.1 Single Pixel Response . . . . . . . . . . . . . . . . . . . . . . 59

4.1.2 Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . 62

4.1.3 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

4.2 Optical Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

4.3 Diagnostic Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

4.3.1 Light Sensitivity of Test Pixel . . . . . . . . . . . . . . . . . 72

4.3.2 Charge injection in a single pixel . . . . . . . . . . . . . . . 72

4.3.3 LVS of the GDS file and the chip schematic . . . . . . . . . 76

4.3.4 Verification of bulk VSS and VDD connections by flattening . 76

4.3.5 Simulation of 40x40 pixel array with current comparator . . 79

5 CONCLUSIONS, APPLICATIONS AND RECOMMENDATIONS 83

5.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

5.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

5.3 Recommendations and Future Work . . . . . . . . . . . . . . . . . . 84

ix

REFERENCES 93

x

LIST OF FIGURES

2.1 Adaptive Optics Imaging System . . . . . . . . . . . . . . . . . . . 5

2.2 History of solid state image sensors . . . . . . . . . . . . . . . . . . 10

2.3 Carrer drift and diffusionin a p-n+ junction photodiode . . . . . . . 14

2.4 Photodiode model for simulations . . . . . . . . . . . . . . . . . . . 15

2.5 Photodiode in charge integration mode . . . . . . . . . . . . . . . . 17

2.6 Vd(t) as a function of time . . . . . . . . . . . . . . . . . . . . . . . 17

2.7 CMOS Photodiodes: (a) p-substrate/ n+ photodiode, (b) p+/n-wellphotodiode, (c) p-substrate/n-well photodiode. . . . . . . . . . . . . 18

2.8 3-T Active pixel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.9 CAPIS sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.10 CAPIS sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.11 Dynamic Current Mirror Principle. . . . . . . . . . . . . . . . . . . 27

3.1 DCM-APIS sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.2 Pixel Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.3 Pixel Circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . 33

3.4 Pixel Circuit in charge integration mode . . . . . . . . . . . . . . . 33

3.5 Pixel Circuit response for Iph = 15nA . . . . . . . . . . . . . . . . . 35

3.6 Variation of output current with sense node voltage . . . . . . . . . 36

3.7 Pixel response for IPH = 10nA and integration time of 3.5µs . . . . 37

xi

3.8 Pixel response for IPH = 10nA and integration time of 3.5µs . . . . 38

3.9 Bias Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.10 Current Comparator Circuit . . . . . . . . . . . . . . . . . . . . . . 39

3.11 Comparator response for Iref = 150µA as Ioutarray is varied . . . . 40

3.12 Comparator response for Iref = 70µA as Ioutarray is varied . . . . . 41

3.13 Circuit for synchronization of comparator output with clock . . . . 41

3.14 Single block of counter . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.15 Counter outputs Q9, Q8, Q7, Q6, Q5 at 65 MHz . . . . . . . . . . 43

3.16 Counter outputs Q4, Q3, Q2, Q1, Q0 at 65 MHz . . . . . . . . . . . 44



3.19 D flip-flop circuit diagram . . . . . . . . . . . . . . . . . . . . . . . 47

3.20 AND gate and XOR gate . . . . . . . . . . . . . . . . . . . . . . . . 47

3.21 Frequency divider circuit . . . . . . . . . . . . . . . . . . . . . . . . 49

3.22 Frequency divider circuit response . . . . . . . . . . . . . . . . . . . 49

3.23 4x1 Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.24 Pixel photocurrents for defocused beam . . . . . . . . . . . . . . . 54

3.25 Output register data for defocused beam . . . . . . . . . . . . . . . 55

3.26 Pixel photocurrents for focused beam . . . . . . . . . . . . . . . . 55

3.27 Output register data for focused beam . . . . . . . . . . . . . . . . 56

3.28 Pixel photocurrents for no light conditions . . . . . . . . . . . . . . 56

3.29 Output register data for no light conditions . . . . . . . . . . . . . 57

4.1 Photomicrograph of CDAPIS sensor . . . . . . . . . . . . . . . . . . 60

4.2 Electrical Test setup for CDAPIS sensor . . . . . . . . . . . . . . . 61

4.3 Circuit for virtual ground generation . . . . . . . . . . . . . . . . . 61

xii

4.4 Current generation and measurement circuit for NMOS device . . . 62

4.5 Current generation and measurement circuit for PMOS device . . . 63

4.6 Electrical Test setup for CDAPIS sensor pixel . . . . . . . . . . . . 64

4.7 CDAPIS pixel circuit test response . . . . . . . . . . . . . . . . . . 65

4.8 Clock divider circuit response for 1MHz Clock . . . . . . . . . . . . 66




4.12 Counter circuit response, LSB bit . . . . . . . . . . . . . . . . . . . 69

4.13 Counter circuit response, MSB bit . . . . . . . . . . . . . . . . . . . 70

4.14 Optical test setup for static illumination conditions . . . . . . . . . 70

4.15 CDAPIS sensor test response . . . . . . . . . . . . . . . . . . . . . 71

4.16 CDAPIS sensor test response . . . . . . . . . . . . . . . . . . . . . 71

4.17 CDAPIS sensor test pixel response in static conditions . . . . . . . 73


4.19 DCM-APIS sensor test pixel response in static conditions . . . . . . 74


4.21 Metal-2 connected between sense node and bonding pad . . . . . . 75

4.22 The layout of GDS file . . . . . . . . . . . . . . . . . . . . . . . . . 76

4.23 The layout of GDS file after flattening . . . . . . . . . . . . . . . . 77

4.24 The layout of GDS file after flattening, highlighting array VSS . . . 77

4.25 The layout of GDS file after flattening, highlighting Digital VSS . . 78

4.26 The layout of GDS file after flattening, highlighting pads VSS . . . . 78

4.27 The layout of GDS file after flattening, highlighting test pixel VSS . 79

4.28 The layout of GDS file after flattening, highlighting array VDD . . . 80

xiii

4.29 The layout of GDS file after flattening, highlighting digital VDD . . 80

4.30 The layout of GDS file after flattening, highlighting test pixel VDD . 81

4.31 The layout of GDS file after flattening, highlighting pads VDD . . . 82

4.32 The response of 40x40 pixel array with current comparator . . . . . 82

1 LVS report of GDS file and Schematic . . . . . . . . . . . . . . . . 85

2 LVS report of GDS file and Schematic continuation . . . . . . . . . 86

3 Control circuitry and counter-register schematic . . . . . . . . . . . 87

4 Control circuitry and counter-register schematic . . . . . . . . . . . 88

5 Reset SIgnal(RS) generation circuit . . . . . . . . . . . . . . . . . . 89

6 Counter and Register . . . . . . . . . . . . . . . . . . . . . . . . . . 90

7 Register clock generation schematic . . . . . . . . . . . . . . . . . . 91

8 Register clock generation schematic . . . . . . . . . . . . . . . . . . 92

xiv

Chapter 1

INTRODUCTION

The quality of the image obtained in astronomy and laser communication applica-

tions is deteriorated by wavefront aberrations that are caused by turbulence in the

atmosphere. To correct such temporally and spatially varying optical wavefront

aberrations in real time, adaptive optics systems with model free optimization are

widely used. In this type of adaptive optics system, a scalar system performance

metric is optimized for wavefront correction. One of the most widely used system

performance metrics is image sharpness. A sharpness sensor that gives an accu-

rate and instantaneous estimation of image sharpness is vital to compensate for

wavefront aberrations in real time.

The continuous growth in CMOS technologies encourages the development

of new wavefront sensors that can operate at low illumination levels and high speeds

and offer advantages such as high resolution, high dynamic range, and high spatial

resolution. Two image sharpness sensors, the CMOS active pixel image sharpness

sensor (CAPIS) and the CMOS dynamic current mirror active pixel sensor, were

designed in the NMSU VLSI Laboratory. The CMOS dynamic current mirror active

pixel image sharpness sensor was designed as part of this project. The details of the

CMOS dynamic current mirror active pixel image sharpness sensor are discussed

in this report.

The unique contributions of this project are:

1

1. The pixel-to-pixel mismatch is very low through the use of dynamic current

mirrors in each pixel.

2. The sensor output is 10-bits for high resolution in the integration time.

An outline of the chapters in this report follows. In chapter 2, the concept

of adaptive optics is explained. Further, different performance metrics and their

VLSI implementation are discussed. The history of CMOS imaging technology is

summarized and a comparison of CCD and CMOS imagers is done. Photodiode

operation and CMOS photodiodes are explained. The 3-T pixel sensor operation

is explained in detail. The CAPIS sensor architecture and operation is explained

and finally the principle of dynamic current mirrors is reviewed.

In chapter 3, the architecture, design and simulations of the CMOS dynamic

current mirror active pixel image sharpness sensor are described. A 4 by 4 design

was simulated in order to have low simulation times.

In chapter 4, the electrical and optical testing of the CMOS dynamic current

mirror active pixel image sharpness (DCM-APIS) sensor is discussed. The electrical

testing involves the electrical testing of the test pixel, the counter and the clock

divider. The optical testing involves testing the array. This chapter also includes

optical testing of a test pixel and estimation of the charge injection present in the

test pixel. The Layout Versus Schematic (LVS) report of the GDS file and the

floor schematic is included. Figures of highlighted analog, digital and pad power

supply(VSS and VDD) connections in the GDS layout are included. Finally, the

simulation results of 40x40 pixel array with current comparator is included.

In chapter 5, conclusions are drawn from the obtained results. Applications

of the DCM-APIS sensor and future work to further improve the performance of

this sensor are discussed.

2

Chapter 2

FUNDAMENTALS OF ADAPTIVE OPTICS AND IMAGE SENSING

Laser communication (lasercom) is a widely used technology to communicate data

efficiently at high data rates and at reduced costs. Principle applications of lasercom

are ground-to-satellite optical communication, communication in remote locations,

and space systems. If we use lasercom for ground-to-satellite or ground based

communications over large distances, due to atmospheric disturbances, the laser

beam may wander, scintillate or spread in different directions. These distortions

become less significant by increasing the laser power but increased power may

increase system cost and pose a hazard for the human eye [1]. Adaptive optics

with wavefront control can be used to automatically rectify the adverse affects of

atmospheric turbulence [2].

Adaptive optics systems using model-free optimization are widely used to

correct temporally and spatially varying wavefront aberrations. Critical for imple-

menting adaptive optics is accurate and instantaneous measure of the wavefront

phase. A wavefront sensor that can operate at low illumination levels and fast

speeds in real time is ideal for wavefront correction.

The continuous growth in CMOS technologies encourages the development

of new image sensors that can operate at low illumination levels and fast speeds

and also offer advantages such as high resolution, high dynamic range, and high

spatial resolution. Another advantage of CMOS technologies is the possibility of

integrating other functions for image processing on a single chip. Although the

3

image sensors that are available commercially can be used for image processing,

they require a CPU / DSP core for off-chip digital processing. Such systems usually

have some limitations such as high power consumption, computational time, poor

scalability and complex inter chip interconnections [3].

In this chapter, the concept of adaptive optics is explained. Further, different

performance metrics and their VLSI implementations are discussed. The history of

CMOS imaging technology is summarized and a comparison of CCD and CMOS

imagers is done. Photodiode operation and CMOS photodiodes are explained. The

3-T pixel sensor operation is explained in detail. The CAPIS sensor architecture

and operation is explained and finally the principle of dynamic current mirrors is

explained.

2.1 Adaptive Optics Systems

Adaptive optics (AO) is a technique to measure the wavefront distortions and

compensate for them in real-time. The main applications of adaptive optics systems

is to improve the image quality in infrared and optical astronomical telescopes,

tracking and imaging of rapidly moving space objects, and compensating for laser

beam distortion through the atmosphere [4].

Figure 2.1 shows the diagram of an adaptive optics imaging system. The

basic components of an AO system are a wavefront sensor, a deformable mirror

which is a wavefront corrector, and a control system such as a very fast computer.

The wavefront sensor estimates the incoming wavefront phase aberrations.

Based on the wavefront sensor measurements, control circuitry quickly adjusts the

reflecting surface of the deformable mirror to compensate for atmospheric turbu-

lence. The purpose of the beam splitter is to deflect part of the light to a high-

resolution camera in order to observe the corrected wavefront [6].

4

Figure 2.1: Adaptive Optics Imaging System from [5].

2.2 Performance Metrics

The main purpose of performance metrics is to provide a measure of phase

distortion in an optical wavefront. The type of performance metric needed depends

on the adaptive optics system. One of the most widely used performance metrics

is image sharpness.

In 1974, Muller and Buffington [7] described image sharpness. Its value for

the true undistorted image is always greater than that of the aberrated image. They

defined several image sharpness metrics. Four of the metrics are discussed here.

5

The first image sharpness metric is

S1 =

∫I2(x, y)dxdy, (2.1)

where I(x,y) is the irradiance at a point (x,y) in the image plane. This equation was

justified using the Fresnel-Kircoff equation for irradiance calculation. This metric

is maximized for the true image, irrespective of the distribution of object-radiance.

The second image sharpness metric is

S2 =

∫M(x, y) · I(x, y)dxdy, (2.2)

where M(x,y) is the transmittance of a mask placed over the image. For S2 to be

a good sharpness definition, M should be an exact copy of the true undistorted

image. S2 reduces to S1 when the distortion is completely eliminated.

The third image sharpness metric is

S3 =

∫In(x, y)dxdy, n = 2, 4, 6...... (2.3)

This metric is also called a power law metric. In 2003, Fienup [8] explored

various power law metrics. According to him, higher-order power law metrics tend

to work better with scattered scenes, whereas lower-order power-law metrics tend

to work better with scatter free scenes.

The fourth image sharpness metric is

S4 = −∫I(x, y) ln[I(x, y)]dxdy, (2.4)

6

This metric reduces the randomness(entropy) in the image and is useful for images

that have large dynamic range.

2.2.1 Square-Law Image Sharpness Metric (SLISM)

To implement the image sharpness metric in VLSI, a new metric called the

square law image sharpness metric (SLISM) is defined. SLISM is the exact discrete

form of the image sharpness metric S1 and is given by

SLISM =N∑i

M∑j

I2i·j, (2.5)

where Ii,j is the intensity at the (i, j)th pixel of the received image and N, M are

the number of rows and columns. This metric increases with image quality and

achieves a maximum value for zero distortion [7].

A CMOS active pixel image sharpness (CAPIS) sensor was designed in the

NMSU VLSI Laboratory. This image sensor did not function under dark conditions

for clock frequencies in the range of 350kHz to 4MHz. In this frequency range

the reset signal doesn’t stay high. Hence, a new focal plane image sensor named

the dynamic current mirror active pixel image sharpness (DCM-APIS) sensor is

designed for better performance. The complete design of DCM-APIS sensor is

discussed in Chapter 3.

2.3 CMOS Image Sensing

In 1970, with the invention of Charge Coupled Devices (CCDs), digital imag-

ing began in a big way. Since then, for the past four decades, CCDs have dominated

the imaging industry. The continuous upgrade in CMOS technology has allowed

CMOS image sensors to compete with CCDs in performance. CMOS image sensors

are not as optically efficient as CCDs but they offer several advantages such as high

levels of integration, reduced power consumption and lower manufacturing costs.

7

The rapid evolution of CMOS technology has led to the their adoption in mass

production applications such as cell phones and automotive imaging systems. At

present, CMOS imaging dominates the imaging business and is likely to dominate

in the future.

2.3.1 Image Sensor Technology

In this section, the historical background of solid-state imaging is provided.

Further, a comparison between CCD and CMOS imagers is discussed.

2.3.1.1 Historical Background

Solid sate imaging history described by Fossum [9] can be summarized as

follows

1. In 1963, Morrison developed a computational sensor to find the position of a

light spot using the photoconductivity effect [10].

2. In 1964, IBM reported the scansistor, designed with an array of n-p-n junc-

tions which gives an output pulse proportional to the intensity of local incident

light [11].

3. In 1966, Westinghouse described a 50x50 element monolithic array of photo-

transistors [12].

4. In 1967, Weckler suggested the operation of a p-n junction in a photon flux

integration mode. All of the above sensors output a signal which is propor-

tional to the intensity of the local incident light and did not intentionally

integrate any optical signal. So, the sensitivity of these senors to light was

low. In integration mode the reverse biased p-n junction capacitance is dis-

charged at a rate determined by the photocurrent, which is proportional to

incident photon light [13]. In 1968, A 100x100 array of these photodiodes was

reported [14].

8

5. In 1968, Noble reported an active-pixel design with a MOS source follower for

readout buffering [15]. Fry, Nobel, and Roycroft explored fixed-pattern-noise

(FPN) in CMOS imagers.

6. In 1970, Boyle and Smith reported the Charge Coupled Device [16]. The low

FPN and simplicity in pixel structure in CCDs attracted an emerging solid

state imaging market.

7. In the 70’s and early 80’s, research mainly concentrated on CCD technology.

Research resulted in improvements in quantum efficiency, fill factor, dark

current, smear, lag, charge transfer efficiency, readout rate, readout noise, area

and power consumption in CCDs. On the other side, Hitachi and Matsushita

continued research on CMOS imagers for video applications [17], [18].

8. In 1985, Hitachi integrated a CCD image sensor with a CMOS readout scheme

[19] .

9. In 1987, Hitachi introduced on-chip techniques to vary exposure time and to

suppress flicker noise from indoor lighting [20].

10. In 1990, a passive pixel sensor (PPS) array was reported by VLSI Vision

Ltd. [21]. But the performance of PPS wasn’t comparable to CCDs even for

low-end vision applications [22].

11. Till the mid 1990’s, FPN was the major problem in CMOS imagers. Because

of FPN, the development of MOS image sensors did not progress forward.

12. In 1992, NASA’s Jet Propulsion Laboratory started research on active pixel

sensors (APS). They included an amplifier in each pixel to improve the sensor

speed and signal-to-noise ratio (SNR). However, the feature sizes of MOS

transistors were too large to make APSs market friendly.

9

13. In 1995, NASA’s JPL developed a CMOS APS for radiation hardness in

space. From then on, CMOS imaging technology rapidly developed. The first

commercial CMOS imagers were placed into toy cameras and in some low-end

vision applications where image quality wasn’t paramount.

Research has continued in CMOS image sensors (CISs) to improve the per-

formance. The advent of deep sub micron technologies, novel pixel designs and

micro lens technologies have improved the performance of CISs. Nowadays, CISs

dominate the imaging business [23]. In 2006, 60% of the estimated $7 billion image

sensors market was CISs. In 2007, CCD dominated the digital still camera market,

whereas CMOS dominated the lower resolution camcorder market. In 2008, the

market for CISs is expected to be higher.

Figure 2.2: History of solid state image sensors from [24].

10

2.3.1.2 CCD vs CMOS Image Sensors

An image sensor naturally includes an array of pixels. Each pixel contains

a photodiode, which transduces the incident photons into electrical charge. This

electrical charge is converted to voltage or current by readout circuits and is made

available at the output of the sensor [22].

The advantages and disadvantages of CCD and CMOS are detailed by

Litwiller [25] and El Gamal [22]. They are summarized as follows:

Responsivity : The amount of electrical charge produced by the sensor in re-

sponse to the incident optical power. In this regard, CMOS Image Sensors (CISs)

are better than Charge Coupled Devices (CCDs). In CISs, complementary transis-

tor structures allow low-power, high gain amplifiers, whereas in CCDs, amplification

requires a significant amount of power.

Dynamic Range : The ratio of the maximum amount of charge sampled to the

signal threshold. In this area, CCDs are better than CISs. In CCDs, the readout

technique is passive; hence, it doesn’t introduce any temporal noise and fixed-

pattern noise (FPN). In CISs, the readout path comprises active elements that

introduce temporal noise and FPN.

Uniformity: Consistency of different pixels response under uniform illumination

conditions. In normal illumination conditions CISs are comparable to CCDs. How-

ever, in dark or low light conditions CISs suffer from increased temporal noise and

FPN.

Shuttering: The capability of randomly starting and stopping exposure. This is

a standard feature in CCDs. In CISs, additional transistors are required to imple-

ment this feature in each pixel, thus reducing the fill factor.

Speed : Generally CISs are superior to CCDs in this regard. CISs are better be-

cause it is possible to integrate all camera functions onto a single chip. In CCDs,

11

the charge transfer is serial, which limits the speed of operation.

Windowing: To readout a small portion of pixel array. This is the unique ca-

pability in CISs. This allows higher speeds of operation when reading out smaller

regions of interest. This is important for high speed tracking.

Antiblooming: To drain the overexposure on individual pixels. In CISs, blooming

effects can be reduced by controlling the reset signal. In CCDs, implementing this

feature requires special engineering.

Power : Compared to CCDs, CISs consume less power. In CCDs, implement-

ing approximately ideal charge transfer requires multiple high-speed, high-voltage

clocks. No such high-voltage clocks are required in CISs.

Cost : Simple fabrication processes make the cost of CISs lower. And the integra-

tion of different functions onto a single chip makes further reduction in the cost of

CISs. To fabricate CCDs requires a special fabrication process.

Radiation hardness : The radiation tolerance of CISs is higher when compared

to CCDs. In space applications, CISs are the dominant image sensor.

2.3.2 Solid-State Phototransconduction

A material that has very small energy band gap between conduction band

and valence band is called a semiconductor. Band gap energy is the amount of

energy that is needed to move an electron from the valence band to the conduction

band. Two well known semiconductor materials are Silicon and Germanium. For

silicon, the energy band gap is 1.12eV and for germanium, the energy band gap is

0.66eV. At absolute zero temperature, no free charge carriers are available in the

semiconductor for conduction, so it acts as an insulator. Photons with energies

greater than the band gap energies of semiconductors can generate an electron-hole

pair. These free charge carriers are available for conduction. This is the basis

for photo detection using semiconductors. Three well known photo detectors are

12

the photogate, photodiode, and phototransistor. At present, the most widely used

photo detector is the photodiode.

2.3.2.1 Photodiode

A photodiode is a semiconductor device which converts the incident photons

into electrical charge. Various photodiodes are the p-n junction diode, p-i-n diode,

Schottky diode, or hetrojunction diode. Because of its simple and inexpensive

fabrication process, the p-n junction diode is the most widely used photo diode for

imaging applications.

2.3.2.2 Photodiode Operation

Assume the photodiode is a p-n junction photo diode. The p-type material

has holes and negatively charged impurity ions. The n-type material has electrons

and positively charged impurity ions. When these two materials are placed side

by side, holes from the p-region diffuse into the n-region and combine with free

electrons and electrons from the n-region diffuse into the p-region and combine

with free holes. This diffusion of charge carriers form one region to another region

is due to thermal energy and the difference in carrier concentrations. Because of

the diffusion of electrons and holes between the n and p regions across the junction,

a depletion region is formed. The depletion region has no free charge carriers; it has

only immobile ions. Because of the immobile acceptor and donor ions, an electric

field is formed between the immobile ions.

The electrical field formed at the junction rejects further crossing of charge

carriers across the junction. Figure 2.3 shows the formation of the depletion region.

When light is incident on the depletion region, photons are absorbed in

the depletion region and generate electron-hole pairs. The generated carriers drift

across the junction by the electric field. If a p-n junction is placed in a closed loop

13

Figure 2.3: Carrer drift and diffusionin a p-n+ junction photodiode [26].

circuit, an external current flows through the junction. The number of electron-hole

pairs generated is proportional to the number of incident photons [27].

Under dark conditions and when the photodiode is operating in the reverse

bias mode, there is no generation of new charge carriers. Only reverse current flows

through the photodiode, because of minority carriers. This current is also called

dark current. The dark current mainly depends on the temperature of the reverse

biased p-n junction, doping concentrations and energy band gap [28].

The responsivity of the photodiode is defined as the ratio of photocurrent

density generated to the incident optical power. The response of the silicon photo-

diode is mostly linear in the range from minimum detectable light power to several

milliWatts.

14

By increasing the reverse bias voltage, the width of the depletion region

increases and improves the responsivity and linearity of the photodiode [29].

2.3.2.3 Photo Diode Model

The photodiode equivalent model is shown in Figure 2.4. Iph is the pho-

tocurrent, which is proportional to the incident photon light. Cph is the junction

capacitance of the photodiode. One could also add a large shunt resistance in par-

allel with the current source and a series resistance due to contacts and undepleted

silicon. The shunt resistance is the slope of the current-voltage curve at the origin.

It is used to measure the noise current in the photodiode. Because the value of the

shunt resistance is so high and the value of the series resistance is small for CMOS

photodiodes, they can be neglected in this application. In simulations, real light

sources and photodiodes cannot be used, so the photodiode model shown in Figure

2.4 was used.

Figure 2.4: Photodiode model for simulations.

The CMOS photodiode used in this project is n+ diffusion in a p-type sub-

strate. The DC characteristics of the pn junction photodiode can be written as

[28]

ID = IS

(e

VdnUT − 1

), (2.6)

In the equation, ID is the diode current, IS is the saturation current, Vd is the

forward bias voltage applied across the photodiode, n is the emission coefficient

15

and UT is the thermal voltage, given as

UT ≡ kT/q, (2.7)

where k is Boltzmann’s constant, T is the temperature in degrees Kelvin, and q is

electron charge value.

The junction capacitance of the photodiode can be compiled as the sum of

bottom plate and sidewall capacitances.

Cph = CJ · A+ CJSW · P (2.8)

where Cph is the junction capacitance for the photodiode, CJ is the bottom plate

capacitance per unit area, A is the bottom plate area, CJSW is the sidewall capac-

itance per unit length and P is the sidewall perimeter.

2.3.3 Photodiode: Charge Integration Voltage Mode

The photodiode mainly operates in two modes. First the sense node capac-

itance is charged to a reset voltage by closing switch S1 as shown in Figure 2.5.

Then, by turning the switch off, the photodiode starts operating in the charge in-

tegration mode. The sense node capacitance is discharged for an integration time

of Tint at a rate of photo current which is proportional to the incident photon flux.

The final voltage at the sense node is sampled and the photodiode is reset again

and the process repeats.

For the case of a photodiode with area A = 10 µm2, Vr = 5V, NA = 1016

cm−3 and Iph = 1pA, the voltage across the photodiode Vd(t) is plotted and is

shown in Figure 2.6. From the plot, for small integration times, the voltage is

linearly varying with the photocurrent, making the output voltage proportional to

incident photon flux.

16

Figure 2.5: Photodiode in charge integration mode [30].

Figure 2.6: Photodiode in charge integration mode [30]

2.3.4 CMOS Photodiodes

Using the standard CMOS p- substrate process, three different photodiodes

can be implemented. The possible photodiodes are the p-substrate/n+ photodiode,

p+/n-well photodiode and p-substrate/n-well photodiode. The respective struc-

17

tures are shown in Figure 2.7. The first two photodiodes have shallow junctions

and the third photodiode has a deep junction. A comparison of these photodiodes

is given in [31] and is summarized below.

Figure 2.7: CMOS Photodiodes: (a) p-substrate/n+ photodiode, (b) p+/n-wellphotodiode, (c) p-substrate/n-well photodiode. [31]

2.3.4.1 The p-substrate/ n+ photodiode

This photodiode is the most widely used photodiode in the CMOS process.

The main advantage of this photodiode is its simple layout. Responsivity to light

is more than the p+/n-well photodiode. However, this photodiode is susceptible

to crosstalk and substrate noise. The response time is longer than the p+/n-well

photodiode because of the contribution of the carriers generated in the substrate.

At a wavelength of 620nm, it exhibits highest quantum efficiency. The dark current

in this photodiode is less compared to the other two photodiodes.

2.3.4.2 The p+/n-well photodiode

This photodiode has a very narrow p+/n-well junction, so its quantum effi-

ciency is low when compared to the other two photodiodes. In this photodiode, the

charge generated outside the well isn’t collected and hence it has lower crosstalk.

This has a faster response because it only collects the charge carriers which are

generated in the depletion region. The quantum efficiency is maximum at a wave-

18

length of 530nm. This photodiode has the highest dark current when compared

with the other two photodiodes.

2.3.4.3 The p-substrate/n- well photodiode

This photodiode has a wide and deep depletion region. So its quantum

efficiency is highest, when compared with the other photodiode structures. It is

able to collect charge carriers which are generated deep in the substrate region.

This photodiode has the lowest depletion capacitance, so this photodiode has high

bandwidth. Because of the diffusion of minority carriers from neighboring photodi-

odes, this photodiode is more sensitive to crosstalk and substrate noise. The dark

current is moderate in this photodiode when compared with the other photodiode

structures. The quantum efficiency is maximum at a wavelength of 620nm.

2.3.5 CMOS Image Sensors

An image sensor consists of an array of pixels. Each pixel has a photodiode

which converts the incident photon light into electrical charge. Readout circuits

in the sensor convert this electrical charge into voltage or current. Various types

of image sensors are: passive pixel sensor, 3-T active pixel sensor, 4-T active pixel

sensor, photogate active pixel sensor, global shutter or snapshot active pixel sensor,

logarithmic active pixel sensor, and digital pixel sensor. To understand the pixel

structure used in this project, knowledge of the 3-T active pixel sensor is necessary.

Operation of the 3-T active pixel sensor is described here.

2.3.5.1 3-T Active Pixel Sensor

This active pixel sensor (APS) uses a pixel structure which has 3 transistors.

The structure of the 3-T pixel is shown in the Figure 2.8. The 3-T pixel consists

of one reset transistor (M1), a source-follower transistor (M2) which is the active

element, and a row select transistor (M3). The photodiode is at the gate of M2.

19

Figure 2.8: 3-T Active pixel from [3].

The capacitance at the sense node comprises the parasitic photodiode ca-

pacitance (CSN), the parasitic source capacitance of the reset transistor and the

parasitic gate capacitance of the source follower. The photodiode area is chosen

such that the capacitance of the photodiode dominates the capacitance at the sense

node. The transistor M2 acts as a buffer amplifier which isolates the photodiode

node and the bias transistor (M4). The bias transistor is attached to each column,

rather than to each pixel, in order to get high fill-factor and reduce pixel-to-pixel

variation. The integration time is controlled by the reset transistor, M1. The reset

transistor is usually implemented with an NMOS, rather than a PMOS, transistor.

If the reset function were implemented with a PMOS transistor, each pixel would

need extra area because of the necessary n-well. However, using an NMOS tran-

sistor, the dynamic range of the pixel is reduced. A voltage of VDD at the gate

20

and drain of an NMOS transistor results in a maximum voltage of VDD-VTHN to

the source terminal, where VTHN is the threshold voltage of the NMOS transistor.

Another disadvantage of using an NMOS transistor is that its threshold voltage

varies from pixel to pixel. This leads to much non-uniformity in the output voltage

at the source of M2.

The pixel operation has two modes: one is reset mode and the other one is

charge integration mode.

Reset Mode: During reset mode, by making input RS high, transistor M1 is

turned on. The sense node capacitance (CSN) is reset to a voltage VR = VDD-

VTHN . By selecting the row select transistor, the reset voltage is sampled and held

on one of the sample and hold circuits for each column. The bias current through

M4, M3, and M2 is given using the square law equation.

IB = K(VGS2 − VTN2)2 = K(VS − VO − VTN2)

2, (2.9)

where VS is the voltage at the sense node, VO is the output voltage, VTN2 is the

threshold voltage of transistor M2, and K is given by

K =1

2µCOX

(W

L

). (2.10)

Rearranging 2.10 to solve for VO, we get

VO = VS −

(VTN2 +

√IBK

). (2.11)

In reset mode, VS is the reset voltage

VOR = VR −

(VTN2 +

√IBK

)= VDD −

(VTN1 + VTN2 +

√IBK

). (2.12)

21

Integration mode : During this mode, the reset transistor and the row select

transistor are off and Cphoto is discharged for an integration time (TINT ) at a rate of

photo current (Iphoto) which in turn is proportional to incident photon flux. Suppose

VPH is the voltage dropped due to the photon flux and is given by

VPH =

∫ TINT

0

Iphoto

Cphoto

(2.13)

The voltage at the sense node after integration TINT is

VSP = VDD − (VTN1 + VPH) . (2.14)

From equation 2.11, the output voltage after an integration period is given as,

VOP = VDD − VPH −

(VTN1 + VTN2 +

√IBK

). (2.15)

So, for bright pixels, the output signal voltage is low, and for dark pixels, the output

signal is high. The output voltage depends on the threshold voltages which is a

major source of fixed-pattern-noise (FPN). By using a double sampling technique,

the FPN can be removed from the output signal. Double sampling has four steps:

sampling the signal voltage, resetting the pixel, sampling the reset voltage, and then

subtracting the signal voltage from the reset voltage. The output from the double

sampling circuit is the difference between the reset voltage and signal voltage.

VO = VOR − VOP = VPH , (2.16)

From the above equation, the output is purely the photo voltage, which is propor-

tional to the incident photon flux and is free of FPN [3].

22

2.4 CMOS Active Pixel Image Sharpness Sensor

The CMOS active pixel image sharpness (CAPIS) sensor is designed as an

improvement over the Logarithmic Image Sharpness (LIS) sensor. In the LIS sensor,

the output is current which is the sum of the pixels’ output current. So, in order to

measure the sensor performance, the output current can be used. However, in real

time applications, variations in the light intensity are significant. As the intensity

of light increases, the photo current also increases and the voltage at the sense

node might end up at a low value. If the integration time is not varied, this could

lead to adverse effects. To overcome this problem a different readout scheme was

implemented. In the new readout scheme, the integration time (Tint) was used as

the sensor performance metric instead of the sum of the pixels’ output current. The

CAPIS sensor architecture is shown in Figure 2.9

The sensor includes a 40x40 pixel array. The output from the pixels is

an output current, which is proportional to the square of the voltage drop across

the sense node. The voltage drop is proportional to the photon flux incident on

the sense nodes of the pixels in the array. The current comparator compares the

array output current (Ioutarray) with a reference current(Iref ). The counter is used

to measure the integration time. The output register stores the integration time.

The frequency divider is used to divide the frequency of the counter under low light

illumination levels. The purpose of the control circuitry is to generate a reset signal

and clock for the output register under different light conditions.

A novel pixel structure was implemented for this sensor and is shown in

Figure 2.10. The pixel operates in two modes. One is reset mode and the other

is integration mode. The sensor operation starts by setting the global reset low.

This makes the pixels operate in reset mode and resets the counter to all 0’s. By

making the global reset signal high, the pixels start operating in charge integration

23

Figure 2.9: CAPIS sensor. [32]

mode. At the same time, a counter starts counting from all 0’s. While the pix-

els are operating in the charge integration mode, a current comparator compares

Ioutarraywith Iref . When Ioutarray exceeds Iref , the output (VC) of the current com-

parator changes its state from logic high to logic low. Control circuitry detects this

transition and triggers the output register to latch onto the count at that moment.

The count value stored in the register is the integration time. The variable integra-

tion time is the measure of performance for this sensor, which is called the CMOS

24

Figure 2.10: Pixel Circuit. [32]

active pixel image sharpness (CAPIS) sensor metric. Under low light illumination

levels, the current comparator may not ever change its output state. In this situa-

tion, decreasing the reference current or dividing the clock frequency to f2

or f4

or f8

using a clock divider circuit, increases the maximum integration time. The CAPIS

sensor metric decreases with increasing image sharpness.

This image sensor did not operate under dark conditions with a clock fre-

quency in the range of 350kHz to 4MHz. In this frequency range, the reset signal

doesn’t stay high. The reason couldn’t be found. So this necessitates the design of

25

a new sensor that can perform better than the CAPIS sensor and one of the main

motivations for this project.

2.4.1 Dynamic Current Mirrors

The main disadvantages of standard mirrors are mismatch between tran-

sistors and flicker noise, which is a dominant noise source at low frequencies. By

increasing the saturation voltage VDS,sat and gate area WL, mismatch and flicker

noise can be reduced. But this approach doesn’t generally reduce the current error

below 1%.

The basic principle involved in dynamic analog circuits is using the gate

capacitance to temporarily hold analog information [33]. One application of this

principle is dynamic current mirrors.

The basic diagram of a dynamic current mirror is shown in Figure 2.11.

The circuit contains a single transistor Tm and three switches Sx, Sy, and Sz. The

operation of the dynamic current mirror is divided in to two phases. In phase0, Tm

operates as an input device of a current mirror. Its drain and gate are connected

by turning switches Sx and Sy on. During this phase, the gate capacitance, C is

charged to a voltage V required to obtain a drain current of I0. In phase1, Tm

operates as an output device of a current mirror. Its drain is connected to the

output by turning the switch Sz on. Because of the stored gate voltage V, Tm

sinks a drain current of I1 which is equal to I0. In this method of copying currents,

using the same transistor as two devices makes mismatch disappear [34].

26

(a) Phase0. (b) phase1.

Figure 2.11: Dynamic Current Mirror Principle.

27

Chapter 3

IMAGE SHARPNESS SENSOR VLSI IMPLEMENTATIONS:

ARCHITECTURE, DESIGN AND SIMULATION

To correct the wavefront aberrations in real time applications such as astronomy

and laser communication, an adaptive optics system-using model free optimization

is a widely used technique. The essential thing for implementation of an adaptive

optics system is a wave front sensor, which provides the system performance metric.

One of the most widely used system performance metrics is image sharpness. In the

NMSU VLSI Laboratory, an image sharpness sensor named the CMOS active pixel

image sharpness (CAPIS) sensor was designed and tested. A new sensor called

the dynamic current mirror active pixel image sharpness (DCM-APIS) sensor has

been developed as part of this project. In this chapter the architecture, design

and simulations of the DCM-APIS sensor are included. This sensor provides an

accurate measure of the Square Law Image Sharpness Metric, which is essential for

the implementation of adaptive optics.

3.1 Dynamic Current Mirror Active Pixel Image Sharpness Sensor

The dynamic current mirror active pixel Image sharpness (DCM-APIS) sen-

sor architecture is shown in Figure 3.1. The sensor is designed in the AMI 0.5µm

process. The power supply used is 3V. The sensor has a 40x40 pixel array. Each

pixel gets its bias voltage from the biasing circuit. The output from each pixel is a

current that is proportional to the square of the voltage drop across the sense node.

This voltage drop is directly proportional to the intensity of light incident on the

28

sense node. The readout scheme implemented in this sensor uses integration time

as the performance metric.

Clock generator

40X40 Array

Bias circuit

Control Circuitry

OutputRegister

10-bit CounterFrequencyDivider

RSPhi 1

Phi 2

Iref

RS

Input clock clock

Comparator

VC

clock_r

B9 B0

IIN

Vb

LSB

MSB

Iarray

Global reset

Figure 3.1: DCM-APIS sensor.

The sensor operation starts by making the global reset low, driving the

pixels into reset mode and resetting the counter to all 1’s. Making the global

reset high causes pixels to start operating in the charge integration mode. When

the pixel changes its mode of operation, the counter also starts counting from

the minimum count. While pixels are operating in the charge integration mode,

a current comparator compares the pixel array output current, Iarray with the

reference current, Iref . When the array output current attains a value greater than

the reference current, the comparator switches its output state from logic high to

logic low. Control circuitry detects this transition and triggers the output register

to latch onto the counter output at the same instant. The count stored in the

output register is the sensor performance metric. After storing the integration

29

time, control circuitry makes the pixels to operate in reset mode and allows the

counter to continue counting. Once the counter reaches the maximum count, pixels

again start operating in charge integration mode.

However, in dark conditions the current comparator will not switch its out-

put state. This is because of the low photo current. In this type of situation, one

can divide the frequency of the counter using the frequency divider circuit into f2

or

f4

orf8

so that the pixel has more time to operate in integration mode. By changing

the select lines S0, S1 of a 4x1 multiplexer, one of the divided frequencies can be

selected. An alternative in such situations is to lower the reference current.

By using the charge integration time as the performance metric, as the light

intensity level grows, the integration time stored at B9 to B0 decreases. So the

metric is minimized as the image gets sharper. The architecture is explained in the

following subsections.

3.1.1 Pixel Design

A novel pixel is designed for this active pixel sensor. The structure of the

pixel is shown in Figure 3.2. In the pixel structure, transistor P1 acts as a common

source amplifier. P1 the active element, which justifies the sensor as an active pixel

sensor. The area of each pixel is 16.3x16.3 µm2. The pixel uses one n+/p-substrate

photodiode which forms a very fast, shallow p-n junction photodiode. The fill

factor, which is the percentage of photo diode area in the total pixel area is 14.9%.

The sense node SN capacitance includes the photodiode junction capacitance

CPH , gate-to-source capacitance CGS of transistor P1, gate-to-drain capacitance

CGD of transistor P1, gate-to-source capacitance CGS of transistor P2 and source-

to-bulk capacitance CSB of transistor P2. The pixel was laid out in such a way that

the capacitance of the photodiode dominates the capacitance at the sense node SN.

30

Figure 3.2: Pixel Circuit.

The capacitance CPH of the photodiode at the sense node is the sum of the

bottom plate and side wall capacitances. CPH is calculated using (2.8), as in

CPH = 40.995µm2 × 4125af

µm2+ 69.8µm× 344

af

µm= 40.74fF (3.1)

The gate-to-source capacitance CGS of transistor P1 is

CGS1 =2

3·W · L · C ′OX = 14.4fF (3.2)

The gate-to-drain capacitance CGD of transistor P1 is

CGD1 = CGDO ·W = 1fF (3.3)

31

The gate-to-source capacitance CGS of transistor P2 is

CGS2 =1

2·W · L · C ′OX = 2.76fF (3.4)

The sourc-to-bulk capacitance CSB of transistor P2 is

CSB2 = Cjs = 1.125fF (3.5)

The total capacitance CSN at the sense node is 60fF. Iout(i,j) is the output current

from the pixel(i, j) which is proportional to the photon flux incident on the sense

node. Transistors N0, N2, P1, P2 are switches with size 1.5µm/0.6µm. These

switches are controlled by two clock signals phi1 and phi2, which are generated

from the reset signal, RS. A separate bias circuit provides the bias voltage, Vb to

transistor N3. N3 is biased to sink 200nA of current. The pixel operates in two

modes: Reset mode and Charge Integration mode. The operation of these modes

is explained as follows:

Reset Mode: In this mode, phi1 is low and phi2 is high to turn the transistors N0

and P2 on and transistors N2 and P1 off, as shown in Figure 3.3. So the output

current from the pixel is ideally zero.

Iout(i,j) = 0. (3.6)

As P2 shorts the gate and drain of P0, and because the bias current is in moderate

inversion, the pixel sense node is reset to a voltage

VRESET = VDD − VTHP1. (3.7)

32

where VTHP1 is the threshold voltage of transistor P1. In simulations, given a

Figure 3.3: Pixel Circuit in reset mode.

power supply of 3V, a reset voltage of about 1.89V was found.

Charge Integration Mode: When phi1 is high and phi2 is low, the pixel starts

operating in charge integration mode. During this mode phi1 and phi2 turn tran-

sistor N3 and P3 on and transistors N2 and P2 off, as shown in Figure 3.4.

Figure 3.4: Pixel Circuit in charge integration mode.

The sense node capacitance CSN discharges for an integration time Tint at

a rate equal to the photo current IPH(i,j). IPH(i,j) is directly proportional to the

33

photon flux incident on the photo diode. VPH is the voltage drop due to the photon

flux at the sense node. Therefore, the voltage at the sense node after Tint is

VINT = VDD − VTHP1 − VPH (3.8)

which is also the gate voltage of P1. Tint was chosen in such a way that the voltage

drop across the photodiode node is high enough to make the transistor P1 operate

in strong inversion. By using the square law equation, the drain current of P1 is

given by

ID1 = K(VSG1 − VTHP1)2. (3.9)

Where K is given by

K =

(1

2

)µpCOX

(W

L

). (3.10)

The source terminal of P1 is connected to VDD and the gate voltage of P1 after Tint

is VINT . Therefore the current flowing in P1 is

ID1 = K(VDD−VINT−VTHP1)2 = K(VDD−VDD+VTHP1+VPH−VTHP1)

2 = K(VPH)2.

(3.11)

Iout(i,j) = ID1 − Ib. (3.12)

Just after reset, ID1 = Ib and Iout(i,j) ≈ 0. However, after integration, the drain

current ID1 is generally so high that the bias current Ib can be neglected. Therefore,

Iout(i,j) ≈ ID1 = K(VPH)2. (3.13)

34

Thus, Iout(i,j) is directly proportional to the square of the voltage drop across the

sense node, which in turn is proportional to the photon flux incident on the photo-

diode.

The response of a single pixel circuit for a photo current of 10nA is shown

in Figure 3.5. Figure 3.6 shows how the output current varies with increasing VPH

for the same photo current, 15 nA.Transient Response

0 2.5 5.0 7.5 10.0 12.5time (us)

3.5

1.5

−.5

V (

V)

V (

V)

3 .5

1.5

−.5

V (

V)

V (

V)

2 .0

1.5

1.0

.5

0

−.5

V (

V)

V (

V)

8 0

−10

I (u

A)

I (u

A)

/ph i1b

/ph i1

/net018

/R0/PLUS

voltage at sense nodevoltage at sense nodevoltage at sense nodevoltage at sense nodevoltage at sense node

Output currentOutput currentOutput currentOutput currentOutput current

time (us)

User: chinna Date: Nov 15, 2008 12:24:09 PM MST Thesis DA_PIXEL_TB schematic : Nov 15 12:23:26 2008 35

Figure 3.5: Pixel Circuit response for Iph = 15nA.

Figures 3.7 and 3.8 show the pixels response for a photocurrent of 10nA but

different integration times. The bias current is 200nA. Clearly, with more integra-

35

DC Response

/R0/PLUS

1.0 1.25 1.5 1.75 2.0 2.25 2.5dc (V)

4 0

3 5

3 0

2 5

2 0

1 5

1 0

5.0

0

−5.0

I (u

A)

dc (V)

User: chinna Date: Nov 15, 2008 12:38:56 PM MST Thesis DA_PIXEL_1_TB schematic : Nov 15 12:38:41 2008 51

Figure 3.6: Variation of output current with sense node voltage.

tion time the pixel voltage discharges more and the output current is increased.

3.1.2 Bias Voltage Circuit

The bias circuit provides the bias voltage Vb to all pixels in the array. It’s

a current mirror. The current ratio is 5:1. The circuit diagram is shown in Figure

3.9. The size of transistor N1 is 5· (WL

). The bias current Ib in each pixel is 200nA.

So the input current is 1µA.

3.1.3 Current Comparator

The current comparator compares the output current Iarray from the pixel

array with the reference current Iref . When Iarray crosses Iref , the output of the

current comparator Vc changes its state from logic high to low. The circuit diagram

36

Transient Response

0 1 2 3 4 5time (us)

3.5

1.5

−.5

V (

V)

V (

V)

3 .5

1.5

−.5

V (

V)

V (

V)

2 .5

2.0

1.5

1.0

.5

0

−.5

V (

V)

V (

V)

8 0

−10

I (u

A)

I (u

A)

/ph i1b

/ph i1

/net018

/R0/PLUS



time (us)


Figure 3.7: Pixel response for IPH = 10nA and integration time of 3.5µs

of the current comparator and also sizing of the transistors are shown in Figure 3.10.

The comparator was designed with the help of Dr. Ramirez-Angulo [35].

The transistor N2 is a diode-connected transistor so the time constant asso-

ciated with the input node is very small. This allows for a fast response. Transistors

N5 and P3 form a CMOS complementary amplifier. Transistor N4 acts as the neg-

ative feedback resistor of the CMOS complementary amplifier. Transistors N6 and

P4 and transistors N7 and P5 are the two pseudo-resistive-load amplifiers. The

purpose of two pseudo-resistive-load amplifiers is to increase the gain. The inverter

formed by N7 and P5 provide a rail-to-rail output swing. Initially Iref is greater

than Iout so that transistor P2 turns on and the node N is pulled high. As Iout

37

Transient Response

0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0time (us)

3.5

1.5

−.5

V (

V)

V (

V)

3 .5

1.5

−.5

V (

V)

V (

V)

2 .5

2.0

1.5

1.0

.5

0

−.5

V (

V)

V (

V)

8 0

−10

I (u

A)

I (u

A)

/ph i1b

/ph i1

/net018

/R0/PLUS



time (us)


Figure 3.8: Pixel response for IPH = 10nA and integration time of 13µs

Figure 3.9: Bias voltage circuit.

increases, the node N is pulled down to low because transistor N3 gradually turns

on more. The transistor N10 acts as a negative feedback resistor; it helps in fast

switching of node P.

38

Figure 3.10: Current Comparator Circuit.

Figure 3.11 shows the response of a current comparator for a refernce current,

Iref = 150µA and Ioutarray varies from 0 to 300µA. From the Figure 3.11 it shows

that as Iout exceeds Iref , the current comparator output VC switches its state from

logic high to logic low. However, for a lower reference current, the response of the

current comparator is delayed. The delay is due to charging or discharging of the

parasitic capacitances associated with the nodes N and P. The response time also

depends on the rate at which Iout is changing. The delay in the current comparator

responses is shown in Figure 3.12 for different rates of change of Iout. The slopes

of Iout1 is 1.51µA/µs, Iout2 is 0.75µA/µs, Iout3 is 0.50µA/µs. From Figure 3.12, for

Iout1 the delay is 1.51µs. For Iout2 the delay is 2.6µs. For Iout3 the delay is 3.8µs.

39

Transient Response

/ vou t /I2/PLUS /I1/PLUS

0 50.0 100 150 200 250 300time (us)

3.5

3.0

2.5

2.0

1.5

1.0

.5

0

−.5

V (

V)

3 50

300

250

200

150

100

50.0

0

−50.0

I (u

A)I ref = 150uAIref = 150uAIref = 150uAIref = 150uAIref = 150uA

IoutarrayIoutarrayIoutarrayIoutarrayIoutarrayComp_outComp_outComp_outComp_outComp_out

time (us)

User: chinna Date: Nov 15, 2008 10:08:57 AM MST Thesis currentcomp_tb_rough1 schematic : Nov 15 10:06:54 2008 57

Figure 3.11: Comparator response for Iref = 150µA as Ioutarray is varied.

So, it clearly shows that, for higher rates of change of Iout the delay in response is

less.

The comparator output is asynchronous. To use Vc further in digital circuitry

it is required to synchronize Vc with the clock used in the readout circuitry. Two

D-flip flops are used to synchronize the comparator output with the clock as shown

in Figure 3.13.

3.1.4 Counter

The purpose of this 10-bit positive edge triggered synchronous counter is

to count the integration time of the pixel array. The basic building block used to

design the counter is shown in Figure 3.14. The basic building block of the counter

40

Transient Response

a="200u";/vout a="350u";/vout a="500u";/vout

a="200u";/I2/PLUS a="350u";/I2/PLUS a="500u";/I2/PLUS

a="200u";/I1/PLUS a="350u";/I1/PLUS a="500u";/I1/PLUS

0 50.0 100 150 200 250 300time (us)

3.5

3.0

2.5

2.0

1.5

1.0

.5

0

−.5

Y0

(V)

1 75

150

125

100

75.0

50.0

25.0

0

−25.0

Y1

(u

A)

IrefIrefIrefIrefIref

Iout3Iout3Iout3Iout3Iout3



vc1vc1vc1vc1vc1

vc2vc2vc2vc2vc2

vc3vc3vc3vc3vc3

time (us)

User: chinna Date: Nov 15, 2008 1:05:02 PM MST Thesis currentcomp_tb_rough1 schematic : Nov 15 13:02:52 2008 55

Figure 3.12: Comparator response for Iref = 70µA as Ioutarray is varied

Figure 3.13: Circuit for synchronization of the comparator output with clock

41

consists of a D-type flip-flop with asynchronous set, an XOR gate and an AND

gate. The same circuit is used ten times for the implementation of a 10-bit ripple

counter.

Fi = Qi ⊕Xi−1. (3.14)

where

Xi−1 = Qi−1 ·Qi−2 ·Qi−3.........Q1 ·Q0 · Enable. (3.15)

When the Enable signal is high, the counter starts counting. For every rising

edge of the clock, the output of the D-flip flop changes. So one of the inputs of

the XOR and AND gates changes and thus the input signal to the next block Xi

changes. Therefore, the count gets incremented for every positive edge of the clock.

Figure 3.14: Single block of counter.

Simulation results for a clock frequency of 65 MHz are shown in Figures 3.15

and 3.16. Figures 3.17 and 3.18 show simulation results for 66 MHz. Clearly the

counter is not operational for 66 MHz.

42

Transient Response

0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0time (us)

3.5

1.5

−.5

V (

V)

V (

V)

3 .5

1.5

−.5

V (

V)

V (

V)

3 .5

1.5

−.5

V (

V)

V (

V)

3 .5

1.5

−.5

V (

V)

V (

V)

3 .5

1.5

−.5

V (

V)

V (

V)

/Q9

/Q8

/Q7

/Q6

/Q5

11111

00000

11111

00000

11111

00000

11111

00000

11111

00000

time (us)

User: chinna Date: Nov 14, 2008 10:33:28 PM MST Thesis counter_10bit_tb schematic : Nov 14 21:32:24 2008 27

Figure 3.15: Counter outputs Q9, Q8, Q7, Q6, Q5 at 65 MHz

3.1.4.1 D Flip-Flop

The transistor level circuit diagram for a synchronous D flip-flop with active

low asynchronous set is shown in Figure 3.19. The output changes with the rising

edge of the clock. The W/L of all NMOS transistors used is 1.5/0.6 and W/L of

all PMOS transistors used is 3.0/0.6.

3.1.4.2 XOR gate and AND gate

The transistor level schematics of the AND and XOR gates used in the design

are shown in Figure 3.20. The gates are implemented with transmission gate logic.

Transmission gate logic reduces the layout area and increases the speed. The W/L

of all PMOS transistors is 3.0/0.6 and W/L of NMOS transistors is 1.5/0.6.

43

Transient Response

0 .250 .500 .750 1.0time (us)

3.5

1.5

−.5

V (

V)

V (

V)

3 .5

1.5

−.5

V (

V)

V (

V)

3 .5

1.5

−.5

V (

V)

V (

V)

3 .5

1.5

−.5

V (

V)

V (

V)

3 .5

1.5

−.5

V (

V)

V (

V)

/Q4

/Q3

/Q2

/Q1

/Q0

11111

00000

11111

00000

11111

00000

11111

00000

11111

00000

time (us)



3.1.5 Output Register

The purpose of the output register is to store the integration time. It stores

the integration time as a binary count. The count stored in the register is a mea-

sure of the performance metric of the dynamic current mirror active pixel image

sharpness sensor. The register is designed with 10 D-flip-flops. The design of the

D-flip-flop is the same as the one explained in the previous section, except for one

small change. For the register, active-low asynchronous set is not needed, so NAND

gates are replaced with inverters. The clock of the register goes high on any one

of three occasions: when the current comparator changes its state from logic high

to logic low, when the global reset is low, or when the current comparator never

44

Transient Response

0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0time (us)

1.75

.75

−.25

V (

V)

V (

V)

3 .5

1.5

−.5

V (

V)

V (

V)

3 .5

1.5

−.5

V (

V)

V (

V)

3 .5

1.5

−.5

V (

V)

V (

V)

3 .5

1.5

−.5

V (

V)

V (

V)

/Q9

/Q8

/Q7

/Q6

/Q5

00000

00000

11111

00000

11111

00000

11111

00000

11111

time (us)


Figure 3.17: Counter outputs Q9, Q8, Q7, Q6, Q5 at 66 MHz.

changes its state and the counter reaches the maximum count. The last can occur

under extremely low illumination levels.

3.1.6 Control Circuitry

The functionality of the control circuitry is to generate the reset signal (RS)

for the pixel array, generate the clock for output register (clockr) and divide the

frequency of the counter under low light illumination conditions. The logic im-

plemented is based on the current comparator output, counter outputs and global

reset. The control circuitry is implemented with D flip-flops, NAND gates and

NOR gates. Circuit diagrams are included in Appendix A. The three functions of

the control circuitry are explained separately.

45

Transient Response

0 100 200 300 400 500 600 700time (ns)

3

2

1

0

V (

V)

V (

V)

3

2

1

0

V (

V)

V (

V)

3

2

1

0

V (

V)

V (

V)

3

2

1

0

V (

V)

V (

V)

3

2

1

0

V (

V)

V (

V)

/Q4

/Q3

/Q2

/Q1

/Q0

00000

11111

00000

11111

00000

11111

00000

11111

00000

11111

time (ns)



The control circuitry generates RCLK and RS signals on three occasions.

1. When the current comparator changes its output, VC state from logic high to

logic low.

2. When VC doesn’t change its state and the counter reaches the maximum

count.

3. When global reset is low.

In the first case, the comparator output changes its output state from logic

high to logic low. Control circuitry detects this transition and first generates clockr

so that the register latches onto the count at that moment. Then the control cir-

46

Figure 3.19: D flip-flop circuit diagram

(a) AND gate. (b) XOR gate.

Figure 3.20: AND gate and XOR gate

cuitry makes the reset signal, RS, go low. By making RS low, the pixels start

operating in reset mode. Otherwise the register doesn’t have the actual count.

The counter continues its counting after the RS signal goes low. After the counter

reaches the maximum count, the RS signal will be high and the pixels start operat-

47

ing in charge integration mode. In the second case, the comparator doesn’t change

its output state even when the counter reaches its maximum count. This could

happen under low light illumination conditions. In low light illumination condi-

tions, the voltage drop across the sense node of the photodiodes is not enough, so

Iarray never exceeds Iref . Therefore VC stays high only. In this type of situations,

one can decrease Iref or dividing the frequency of the counter to (f2) or (f

4) or (f

8)

with clock divider circuit (explained in the next section) so that pixels have enough

time to discharge. In the third case, by making the global reset low, the counter is

set to a maximum count. In both the 2nd and 3rd cases, the output register stores

the maximum count.

3.1.6.1 Frequency Divider

The basic diagram of the clock divider circuit is shown in Figure 3.21. It

is designed with a D flip-flop. The output of the D flip-flop changes on the rising

edge of the original clock. So, for one period of the divide-by-2 clock, it takes two

periods of the original clock. And, this divide by 2 clock is given as the clock for

the next D flip-flop with the same connections to get the divide-by-4 clock. The

same procedure continues for the generation of the divide-by-8 clock. The design

of the D-flip-flop is the same as the one explained in the previous sections. The

circuit response is shown in Figure 3.22. To select one of the divided frequencies, a

4x1 multiplexer is used.

3.1.6.2 Multiplexer 4x1

The transistor level circuit diagram of 4x1 multiplexer is shown in Figure

3.23. It is implemented with transmission gates. Two select lines S0, S1 pass one of

the inputs to the output. The W/L of all PMOS transistors used is 3.0µm/0.6µm

and for all NMOS transistors W/L is 1.5µm/0.6µm. The truth table of the 4x1

multiplexer is shown in Table 3.1.

48

Figure 3.21: Frequency divider circuit.Transient Response

0 .500 1.0 1.5 2.0time (us)

3.5

1.5

−.5

V (

V)

V (

V)

3 .5

1.5

−.5

V (

V)

V (

V)

3 .5

1.5

−.5

V (

V)

V (

V)

3 .5

1.5

−.5

V (

V)

V (

V)

/c lk

/d iv2

/d iv4

/d iv8

div2div2div2div2div2



Input ClockInput ClockInput ClockInput ClockInput Clock11111

00000

11111

00000

11111

00000

time (us)

User: chinna Date: Nov 14, 2008 9:12:22 PM MST Thesis freqdiv_tb schematic : Nov 14 21:08:30 2008 15

Figure 3.22: Frequency divider circuit response

3.1.7 Dynamic current mirror Active Pixel Image Sharpness Sensor

Metric

The measure of the performance metric of DCM-APIS sensor designed in

this project is integration time Tint, which is available at the output register as

a binary number. The integration time can be used to estimate the SLISM. The

mathematical relation between Tint and SLISM is shown below.

The output current (Iout(i,j)) of (i, j)th pixel is proportional to the square of

the voltage drop (VPH(i,j)) at the sense node which in turn is proportional to the

49

Figure 3.23: 4x1 multiplexer.

incident photon flux. So rewriting the eq.

Iout(i,j) = K(VPH(i,j))2 (3.16)

50

Table 3.1: 4x1 Multiplexer truth table.

S1 S0 Output0 0 Divide by 20 1 Divide by 41 0 Divide by 81 1 Input clock

The voltage drop VPH at the sense node due to the discharging of CSN at a

rate proportional to IPH for the integration time, Tint is given by

VPH =

(IPH

CSN

)Tint. (3.17)

The sum of all pixels output currents is

Ioutarray = K ·N∑

i=1

M∑j=1

(VPH(i,j))2. (3.18)

where N, M are the number of rows and columns, respectively, of the 40x40 pixel

array. Substituting VPH in 3.18

Ioutarray = K ·N∑

i=1

M∑j=1

(IPH(i,j)

CSN

· Tint

)2

. (3.19)

The integration time Tint is same for all pixels in the array and the charge

integration is stopped when Ioutarray equals to Iref . The capacitance, CSN at the

sense node is assumed the same for all pixels. Rewriting 3.13

Iref = K ·(TINT

CSN

)2 N∑i=1

M∑j=1

(IPH(i,j))2. (3.20)

51

From (2.5), SLISM is the sum of all pixels current. Rewriting 3.20

Iref = K ·(TINT

CSN

)2

· SLISM. (3.21)

From (3.21), charge integration time for the pixel array is

TINT =

(CSN ·

√Iref

K

)· 1√

SLISM. (3.22)

Since Iref , CSN , and K are constants, the integration time is inversely related

to SLISM. So, as the image gets sharper, the integration time reduces. Hence

Integration time can be used as a system performance metric and is given as

DCM − APISSM =C√

SLISM. (3.23)

where C is given by

C =

(CSN ·

√Iref

K

)(3.24)

So from above, the metric is minimized as the image gets sharper.

3.1.8 4x4 Array Simulation Responses

It is not possible to simulate the entire 40x40 pixel array with readout cir-

cuitry because of the large memory requirements and limitations with the simulator.

So, for checking the functionality of the sensor, a 4x4 array with readout circuitry

is simulated. The simulations for three different light conditions are shown below.

1. When the light is focused.

2. When the light is defocused.

3. In no light conditions.

52

The frequency for the counter is chosen to be 1 MHz for the three conditions.

Figure 3.24 shows the photo currents used in the 4x4 pixels for the defocused

beam. The total photo current is 20 nA. The total photo current is spread across

the array as shown in Figure 3.24. In the Figure 3.24, the middle pixels have

more photocurrent (2 nA) compared to the surrounding pixels (1 nA). The digital

output from the output register is shown in Figure 3.25. The maximum array

output current is 162µA. The binary number in the output register is

Output = (0000100010)2 = (34)10.

Hence the integration time for the defocused light is

TINTD =34

1× 106= 3.4µs (3.25)

Initially, the global reset is low, so all the bits in the register are logic 1’s.

When the VC signal goes low, after two clock delays, the count at that moment will

be stored in the output register. The two clock delays is due to the synchronization

of the current comparator output with the clock. In two clocks, the counter incre-

ments only two counts, creating an offset in the stored output value. In a closed

loop adaptive optics system, this offset will not effect the system performance.

Figure 3.26 shows the the photo currents used in each pixel for focused

light. For this case also the total photo current is 20 nA. The middle pixels have

more photocurrent (5 nA) compared to the surrounding pixels (1 pA). The digital

output from the sensor is shown in Figure 3.27. The maximum array output current

is 182µA. The binary number in the output register is

Output = (0000010101)2 = (21)10.

53

Hence the integration time for the focused light is

TINTD =21

1× 106= 2.1µs (3.26)

Clearly the integration time (2.1µs) for focused light is less than the integration

time (3.4µs) of the defocused light. Therefore as sharpness increases, integration

time is decreasing. This shows that DCM-APISSM is a valid metric that can be

used as a measure of image sharpness.

Figure 3.28 shows the the photocurrents used in the pixel array for no light

conditions. Every pixel has the same photocurrent under dark conditions. Under

no light conditions there is no measurable voltage drop across the sense node so

Iarray is always much less than Iref . Hence, the register always stores all 1’s. Figure

3.29 shows that all 1’s are stored in the output register.

1nA

1nA

1nA 1nA 1nA

2nA

1nA

1nA 1nA

2nA

2nA 1nA

2nA 1nA

1nA 1nA

Figure 3.24: Pixel photocurrents for defocused beam.

54

Figure 3.25: Output register data for defocused beam.

1pA

1pA

1pA 1pA 1pA

5nA

1pA

1pA 1pA

5nA

5nA 1pA

5nA 1pA

1pA 1pA

Figure 3.26: Pixel photocurrents for focused beam.

55

Figure 3.27: Output register data for focused beam.

1pA

1pA

1pA 1pA 1pA

1pA

1pA

1pA 1pA

1pA

1pA 1pA

1pA 1pA

1pA 1pA

Figure 3.28: Pixel photocurrents for no light conditions.

56

Figure 3.29: Output register data for no light conditions

57

Chapter 4

ELECTRICAL AND OPTICAL TESTING

Figure 4.1 shows the photomicrograph of dynamic current mirror active pixel im-

age sharpness (DCM-APIS) sensor. Electrical and optical testing of the DCM-APIS

sensor was done. The sensor is designed in the AMI 0.5µm CMOS process and fab-

ricated through MOSIS. Electrical testing involves measuring electrical character-

istics of important components in the sensor design. For electrical testing, a single

test pixel is laid out separately on the chip and, for other components, important

outputs are available as test pins. These components aren’t laid out separately, but

are part of the sensor array. Optical testing involves testing the whole sensor for

light sensitivity. Optical testing was done in static conditions.

4.1 Electrical Testing

The electrical test setup box is shown in Figure 4.2. The power source is

a 9V battery. The chip needs only 3V. By using an LM317T voltage regulator,

the required supply for the chip is generated. Further, two LMC6482s (CMOS I/O

rail-to-rail amplifiers) are used in the test setup for precise current and voltage

measurements.

Figure 4.3 shows the circuit for virtual ground generation. In Figure 4.3, the

op-amp is connected in a voltage follower configuration. Two 100kOhm resistors

are used to divide the voltage into half of the power supply. The output voltage is

1.5V, which is the virtual ground voltage. The capacitors are used to remove noise,

if any noise is present. Figure 4.4 shows the current generation and measurement

58

circuit for an on-chip NMOS device. In Figure 4.4, the op-amp is connected in a

voltage follower configuration. The current IIN is fixed using

IIN =3V − VOUT

R(4.1)

Figure 4.5 shows the current generation and measurement circuit for a

PMOS device. The current IIN is fixed using

IIN =VOUT

R(4.2)

4.1.1 Single Pixel Response

For testing the electrical properties of a pixel, a single pixel is laid out sep-

arately on the chip. The single pixel circuit, bias circuit and current measurement

circuit are shown in Figure 4.6. The photodiode node is available as a pin. The

bias voltage Vb = 600mV is applied using the bias circuit shown in Figure 4.6.

The bias voltage is measured with the DMM. The output current from the pixel

is measured using the current measurement circuit shown in Figure 4.6. In Figure

4.6, the positive terminal of the amplifier is connected to a virtual ground which is

1.5V. The virtual ground generation circuit is shown in the Figure 4.3. The current

from the pixel flows from the input to the output of the amplifier. If the positive

terminal is connected to ground, the output would go negative, which is outside

the power rails. The output voltage VOUT of the amplifier is measured using the

DMM. The current through the resistor is given as

IOUT =1.5V − VOUT

R(4.3)

Initially, by making signal RS low, the photodiode capacitance of the pixel

is reset to a voltage measured as 1.89V, 1.11V below power supply of 3V. The reset

59

Figure 4.1: Photomicrograph of CDAPIS sensor.

voltage was measured using the DMM. Then RS is connected to VDD. Using a

voltage source, a DC voltage is applied at the sense node in steps of 20mV starting

from the reset voltage (1.89V), down to 500mV. The output voltage VOUT of the

amplifier is measured using the DMM for each step. Using (4.1) the current is

calculated for each step. A plot of Iout versus VSG is shown in Figure 4.7.

60

Figure 4.2: Electrical Test setup for CDAPIS sensor

Figure 4.3: Circuit for virtual ground generation

61

Figure 4.4: Current generation and measurement circuit for NMOS device

From Figure 4.7 it can be observed that the current is approximately pro-

portional to the square of (VSG - VTHP ) of transistor P1 in the pixel circuit. This

is an extremely desirable characteristic for the image sharpness sensor.

4.1.2 Clock Divider

The clock divider circuit is not laid out as a separate block. Instead, the

required inputs and outputs that are used in the sensor design are available as test

pins. The clock divider circuit divides the clock frequency under low light conditions

to give more time for the pixel to operate in the charge integration mode. An input

clock with frequency f is given from a function generator. The outputs (f/2, f/4,

f/8) of the clock divider circuit are passed to the 4x1 multiplexer. By using the

select lines S0 and S1 of the multiplexer, one of the divided frequencies f/2, f/4,

62

Figure 4.5: Current generation and measurement circuit for PMOS device

f/8 or the original frequency f can be selected. The output of the multiplexer is

observed using the oscilloscope. The input clock frequency is 1MHz. Figure 4.8

shows the original clock from the function generator and the clock of frequency(f)

after the multiplexer. The multiplexer select lines S0S1 are 11, to select a clock of

frequency(f).

In Figure 4.9, the multiplexer select lines S0S1 are 10, to select a clock of

frequency f/2. In Figure 4.10, the multiplexer select lines S0S1 are 01, to select a

clock of frequency f/4. In Figure 4.11, the multiplexer select lines S0S1 are 00, to

select a clock of frequency f/8.

63

Figure 4.6: Electrical Test setup for CDAPIS sensor pixel

4.1.3 Counter

The counter is another block that is not laid out separately on the chip.

Instead important inputs and outputs that are used in the sensor design are avail-

able as pins for testing the counter circuit. The clock for the counter comes from

the 4x1 multiplexer. For measurments, the input clock frequency was chosen to be

64

1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 20

2

4

6

8

10

12

14

16

18

20

Vsg(V)

Iout

(uA

)

Figure 4.7: CDAPIS pixel circuit test response

1MHz. The select lines S0S1 are set to 11 so that counter gets 1MHz frequency.

Only the LSB and MSB bits of the counter are available as test pins. The LSB and

MSB bits are observed using the oscilloscope. For 1MHz frequency, 3VPP signal,

the expected LSB is 500kHz, 3VPP signal and MSB is 976.6Hz, 3VPP signal. Figure

4.12 shows the LSB bit, measured f = 499.4kHz and Figure 4.13 shows the MSB

bit, measured f = 977.5Hz for input signal of frequency 1 MHz and 3VPP .

4.2 Optical Testing

Array testing is done in static light conditions. Figure 4.14 shows the test

setup for static conditions. A laser beam passes through an attenuator, which

reduces the intensity of the laser beam. The low intensity beam passes through

a microscope objective lens to focus it. A pinhole is placed after the microscope

65

Figure 4.8: Clock divider circuit response for 1MHz Clock, for Input frequency f

Figure 4.9: Clock divider circuit response for 1MHz Clock, for frequency f/2

66


objective lens to get a clean circular beam. After the focal point of the microscope

objective lens, the rays diverge. A collimating lens makes the diverging rays into

collimated rays. An iris with diameter d is used to get the required laser beam spot

size. After the iris, a converging lens focuses the beam onto the sensor. The focal

length f of the converging lens is 50 cm. The diameter D of the spot size at the

focal point is calculated by

D =1.14× λ× f

d(4.4)

For a He-Ne laser, λ = 663nm.

For array testing, the reference current Iref = 140µm is set using the circuit

in Figure 4.5. The resistance value used to generate Iref is 1.28kOhms. VOUT is

measured using the DMM. The equation to calculate the current is given by

67


IIN = VOUT/R. (4.5)

To measure a copy of pixel array output current, the circuit shown in Figure

4.4 is used. The resistance value used is 10kOhms. VOUT is measured using the

DMM. The input current can be calculated using

IIN = (3.0− VOUT )/R (4.6)

Figure 4.15 shows the reset signal (RS) and current comparator output (VC).

In Figure 4.15, the signal VC is immediately going down after the RS signal goes

68

Figure 4.12: Counter circuit response, LSB bit. Measured f = 499.4kHz

high. For all light intensity levels, the VC signal stays the same as that shown in

the Figure 4.15. Even for no light conditions it stays the same. But for no light

conditions VC should stay high all the time. For measuring a copy of the pixel array

output current, the circuit shown in Figure 4.4 used. The output voltage (VOUT ) is

plotted instead of current. Figure 4.16 shows the reset signal (RS) and VOUT . The

voltage VOUT does not vary with light intensity. So the sensor is not light sensitive

at all. To know the reason for the malfunctioning of the sensor, different tests were

done. The tests are discussed in the next section.

4.3 Diagnostic Tests

The different tests performed were:

1. Exploring the light sensitivity of the test pixel

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Figure 4.13: Counter circuit response, MSB bit. Measured f = 977.5Hz

Figure 3: Test Bench for Static illumination conditions

Figure 4.14: Optical test setup for static illumination conditions

70

Figure 4.15: DCM-APS sensor test response, RS (top) and VC (bottom) signals

Figure 4.16: DCM-APS sensor test response, RS (top) and VIoutc (bottom) signals

71

2. Measuring the charge injection present in the test pixel due to the clocks

3. Performing Layout Versus Schematic (LVS) of the GDS file, that is, the file

that is sent for fabrication.

4. Verifying the bulk VSS and VDD connections in the GDS file.

5. Simulations of the entire 40x40 pixel array with the current comparator.

4.3.1 Light Sensitivity of Test Pixel

The array is insensitive to light. This test is to find whether the test pixel

is light sensitive or not. The frequency of the reset signal applied is 10Hz. A 10Hz

signal is used due to the large output capacitance of 2 pF attached to the sense

node. A flash light is focused on the chip. Depending on the light intensity, the

pixel output current and the drop in the voltage at the sense node varies. Figures

4.17 and 4.18 shows the voltage at the sense node and the output voltage when the

flash light is focused on the chip from a distance of 8 cm. Figures 4.19 and 4.20

shows the voltage at the sense node and the output voltage when the flash light

is focused on the chip from a distance of 4 cm. For high intensity light (Figures

4.19, 4.20) the sense node is discharged more and the output current is high when

compared to low intensity light (Figures 4.17, 4.18). So it is very clear that the test

pixel is light sensitive.

4.3.2 Charge injection in a single pixel

Charge injection is the injection of charge from a MOSFET channel when

it is turned off. The malfunctioning of the sensor may be due to charge injection

of the clocks onto the sense nodes in the pixels. So we tried to estimate how much

charge injection is present in the test pixel, that is, whether charge injection is

really affecting the output current. In the test pixel, the sense node is available as

a pin. In the array, the sense nodes are not available as pins. To make the test

72

Figure 4.17: DCM-APIS sensor test pixel response, RS (top) and sense node voltage(bottom). The distance of flash light is 8cm.

Figure 4.18: DCM-APIS sensor test pixel response, RS (top) and output voltage(bottom). The distance of flash light is 8cm.

pixel sense node available as a pin, it was connected to a bonding pad. Because

of the bonding pad, 2pF of extra capacitance is added to the sense node. In the

pixel array, the sense nodes are not connected to bonding pads. Charge injection

73

Figure 4.19: DCM-APIS sensor test pixel response, RS (top) and sense node voltage(bottom). The distance of flashlight is 4cm.

Figure 4.20: DCM-APIS sensor test pixel response, RS (top) and output voltage(bottom). The distance of flash light is 4cm.

increases the discharge rate of the sense node capacitance. Charge injection can

be reduced by increasing the sense node capacitance or reducing the size of the

MOSFET switch.

74

A metal2 wire is used to connect the photodiode sense node to the bonding

pad, as shown in Figure 4.21. We tried to break the metal2 on the chip using a

microscope, probe, monitor and vacuum pump. The microscope was used to zoom

in on the chip. A monitor is connected to the microscope to observe the chip. The

probe was used to scratch the metal on the chip. A vacuum pump was used to

stabilize the chip on the platform. The setup figure is included in Appendix A. By

looking in the monitor, we moved the probe over the metal2 wire so that probe

attempts to scratch through the overglass to break the metal2 wire. But it wasn’t

possible to break this metal2 wire. So the charge injection present in the test pixel

could not be measured.

Figure 4.21: Metal-2 connected between sense node and bonding pad

75

4.3.3 LVS of the GDS file and the chip schematic

To know whether any metal or contact or component or layer might be

missing in the GDS file, LVS of the GDS file and original schematic was done. The

netlists are perfectly matched. So no metal layer or contact is missing in the layout.

The LVS report is included in Appendx A.

4.3.4 Verification of bulk VSS and VDD connections by flattening

The netlist is perfectly matched so no layer is missing in the layout. But two

different VSS connections could be shorted through the substrate or two different

VDD rails could be shorted through an n-well. If this happens, high substrate

currents flow through high resistance paths in the chip and this may cause the chip

to malfunction. Cadence doesn’t show any error in the LVS for this type of layout

error.

VDD and VSS connections can be checked by flattening the layout. The steps

in the flattening are:

Figure 4.22: The layout of GDS file

1. Copy the GDS file into a new layout file, as shown in Figure 4.22.

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Figure 4.23: The extracted layout of GDS file after flattening

Figure 4.24: The extracted layout of GDS file after flattening, highlighting arrayVSS

2. Flatten the new layout file, which gets rid of all hierarchy.

3. Select M1, M2, M3, via and via1 as shown in the Figure 4.23.

77

Figure 4.25: The extracted layout of GDS file after flattening, highlighting digitalVSS

Figure 4.26: The layout of GDS file after flattening, highlighting pads VSS

4. Copy metals to a new layout. Delete top pins at the top layer. Extract the

remaining layout.

78

Figure 4.27: The extracted layout of GDS file after flattening, highlighting testpixel VSS

5. In the extracted file, highlight one connection of VSS and check whether the

remaining VSS connections are shorted through metal layers. This is done

and is shown in Figures 4.24, 4.25, 4.26 and 4.27.

6. In the extracted file, highlight one connection of VDD and check whether the

remaining VDD connections are shorted through metal layers. This is done

and is shown in Figures 4.28, 4.29, 4.30, and 4.31.

It was found that no VSS and VDD connections are shorted through the

substrate or n-well, respectively.

4.3.5 Simulation of 40x40 pixel array with current comparator

This is another test that was done to know the reason for the malfunctioning

of the sensor. We simulated the 40x40 pixel array with the current comparator.

The digital counter and output register are not included in simulations because

of the enormous simulation time. Figure 4.32 shows the simulation results of the

79

Figure 4.28: The extracted layout of GDS file after flattening, highlighting arrayVDD

Figure 4.29: The extracted layout of GDS file after flattening, highlighting digitalVDD

40x40 pixel array with the current comparator. The simulations are done at 1MHz.

For one row of pixels, the photocurrent used is 2nA and for the remaining rows

the photocurrent is 100pA. In Figure 4.26, FC is the reset signal. When FC is low,

80

Figure 4.30: The extracted layout of GDS file after flattening, highlighting testpixel VDD

the pixel array is operating in the reset mode. When FC is high, the pixel array is

operating in the charge integration mode. The reference current Iref in simulations

is 140µA. In reset mode the output current Iout is not zero but actually it should be

zero. The current comparator output is high in reset mode. The abrupt increase

in the output current is due to charge injection. In charge integration mode, Iout is

increasing linearly instead of as square law. The current comparator output became

low when Iout crossed Iref . In optical testing, Iout shoots up immediately when the

pixels changes its mode of operation from reset mode to charge integration mode

for all light intensity levels. May be this is the problem for malfunctiong of the

sensor. This needs to be investigated further.

Even after the above tests, the reason for the malfunctioning of the sensor

could not be found.

81

Figure 4.31: The extracted layout of GDS file after flattening, highlighting padsVDD

Transient Response

5.0 5.25 5.5 5.75 6.0 6.25time (us)

3.53.02.52.01.51.0.5

V (

V)

V (

V)

1 55

150

145

140

135

130

125

I (u

A)

I (u

A)

3 00250200150100

50.00

−50.0

I (u

A)

I (u

A)

3 .5

1.5

−.5

V (

V)

V (

V)

/FC

/I13/PLUS

/ I19/ I10/N0/D

/Cout

IrefIrefIrefIrefIref

IoutIoutIoutIoutIout

Comparator outputComparator outputComparator outputComparator outputComparator output

time (us)

User: chinna Date: Dec 2, 2008 6:04:01 PM MST Graph Window 4

Figure 4.32: The response of 40x40 pixel array with current comparator at 1MHz

82

Chapter 5

CONCLUSIONS, APPLICATIONS AND RECOMMENDATIONS

5.1 Conclusions

The main goal of this project is to design an image sharpness sensor to

operate at low illumination conditions, with a high bandwidth and with repeatable

outputs. This sensor is designed and fabricated in the AMI 0.5µm technology.

Dynamic current mirrors are used in the pixel design to remove mismatch between

transistors. The main features of this sensor are the ability to operate at low light

illumination conditions and its fast response because of the active pixel technology.

The sensor output is a 10-bit digital output which makes off-chip digital processing

and control very fast.

For some reason the sensor is not sensitive to light. To find the reason for

malfunctioning of the sensor, several tests were done. But the core reason could

not be found.

5.2 Applications

Image sharpness sensors find application in adaptive optics systems that

are required in laser communication applications. The principle applications of

laser com are ground-satellite optical communication, communication in remote

locations, and space systems. Without laser communication, space systems would

be susceptible to RF interference.

83

The active pixel technology used in the sensor design helps the sensor to

operate at extremely low illumination levels, which makes this sharpness sensor

also useful in astronomy applications.

This sensor could be useful in autofocusing camera systems. The sensor

output can be used to change the position of the lens in the camera so that the

image plane would be at the focal point [36].

5.3 Recommendations and Future Work

1. The reason for the light insensitiveness of the CDAPIS sensor needs to be

found.

2. The design of the current comparator can be improved to reduce the delay in

switching of output levels even for low current values.

3. Include the current comparator input as a pin so that the current comparator

can be tested.

4. Include pixel array output, RS (phi1) and RSB (phi2) as pins so that sensor

is more testable.

5. Include test circuits for measuring charge injection at the sense nodes at one

or two pixels in the array.

6. Revisit figure 4.32. Iout is not going to zero in reset mode. Actually it

should be zero in reset mode. And also Iout is increasing linearly in charge

integration mode but it should follow the square law. There is also lot of

charge integration. This needs to be investigated further.

7. Make the sensor resolution programmable - 10bits, 8bits, 6 bits, or perhaps

even 4-bits, depending on the application. Lower resolution means the sensor

can run at a slower clock rate.

84

APPENDIX A

@(#)$CDS: LVS.exe version 5.1.0 06/20/2007 02:10 (cicln03) $

Command line: /opt/cadence/ic5141/tools.lnx86/dfII/bin/32bit/LVS.exe -dir /home/graduate/chinna/cadence/LVS -l -s -t /home/graduate/chinna/cadence/LVS/layout /home/graduate/chinna/cadence/LVS/schematicLike matching is enabled.Net swapping is enabled.Using terminal names as correspondence points.Compiling Diva LVS rules...

Net-list summary for /home/graduate/chinna/cadence/LVS/layout/netlist count

8089 nets33 terminals13183 pmos13202 nmos

Net-list summary for /home/graduate/chinna/cadence/LVS/schematic/netlist count

8089 nets33 terminals2573 cap8144 pmos10656 nmos

Devices in the rules but not in the netlist: nfet pfet nmos4 pmos4

The net-lists match.

layout schematic instances

un-matched 0 0rewired 0 0size errors 0 0pruned 0 0active 21373 21373total 21373 21373

netsun-matched 0 0merged 0 0pruned 0 0active 8089 8089total 8089 8089

terminalsun-matched 0 0matched butdifferent type 0 0total 33 33

Figure 1: LVS report of GDS file and Schematic

85

Probe files from /home/graduate/chinna/cadence/LVS/schematic

devbad.out:

netbad.out:

mergenet.out:

termbad.out:

prunenet.out:

prunedev.out:

audit.out:

Probe files from /home/graduate/chinna/cadence/LVS/layout

devbad.out:

netbad.out:

mergenet.out:

termbad.out:

prunenet.out:

prunedev.out:

audit.out:

Figure 2: LVS report of GDS file and Schematic continuation

86

Figure 3: Control circuitry and counter-register schematic

87

Figure 4: Clock divider circuit and Multiplexer 4x1

88

Figure 5: Reset Signal(RS) generation circuit

89

Figure 6: Counter and Register

90

Figure 7: Register clock generation schematic

91

Figure 8: Register clock generation schematic

92

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