dynamic reduction of voltage margins by leveraging on-chip ecc in itanium ii processors
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Dynamic Reduction of Voltage Margins by Leveraging On-chip ECC in Itanium II Processors. Presented By : SOMESH PAL (13IS23F) - PowerPoint PPT PresentationTRANSCRIPT
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Presented By : SOMESH PAL (13IS23F)VISHAL BABU (13IS25F) MTECH CSE-IS NITK SURATHKAL Dynamic Reduction of Voltage Margins by Leveraging On-chip ECC in Itanium II Processors
Anys BachaComputer Science and EngineeringThe Ohio State [email protected] TeodorescuComputer Science and EngineeringThe Ohio State [email protected] Guidance Of :Dr. Basvaraj TalawarAssistant professor,Dept. of CSE, NITKCONTENTS:IntroductionMotivationECC-Based voltage speculationPrototype ImplementationEvaluation MethodologyEvaluationRelated WorkConclusion and Future Work
Introduction :Dynamically reducing voltage margins & lowering vdd while chip operating frequency constant.
Firmware-based technique for voltage speculation.
On-chip correctable error report to identify lowest, safe operating voltage.
Evaluates a prototype implementation of the voltage speculation system on an HP server using Intel's Itanium 9560 processors.
MotivationSupply voltage depends on:
Design process such as speed, power consumption etc.
Run time environment it includes temperature variation, circuit aging etc.
MotivationExperiments on Intel Itanium II 9560 8-core processors:
Chip frequency was set at their nominal values according to the product specications. The Vdd was gradually lowered for each core while running a stress test workload until system crashes or data corruption occur. The lowest safe voltage at which each core runs reliably is recorded. Voltages that are signicantly lower than nominal values 12% lower on average.
Motivation
MotivationResults of experiments :
Record correctable error report agged by the hardware. They are single-bit errors that occur in ECC-protected functional units. The ECC hardware corrects these errors and logs them for debugging purposes.
When the Vdd of the core is lowered below 0.96V, the system no longer operates reliably.
Motivation
ECC-Based voltage speculation:Our solution has two main components:
Error monitoring system : for identifying and logging correctable errors Dynamic voltage speculation governor : for dynamically controlling Vdd.
This paper present a new voltage speculation system that dynamically lowers Vdd and uses correctable error reports to ensure cores do not reach unsafe operating levels.
In general correctable error handling, as implemented in current processors is invisible to the Operating System (OS) and the applications running on the system.
Our system taps into correctable error logs by conguring the hardware to report correctable errors to a rmware layer that implements our monitoring functions.
Margin Voltage Discovery:
Aggressive vs. Conservative Cores:
Dynamic Voltage Speculation:A rmware-based Voltage Speculation Governor .
The governor receives input from the error monitoring system and reacts to information about error rates according to predened algorithms.
The governor is also responsible for coordinating the margin voltage discovery phase.
Aggressive and conservative cores are handled dierently by the voltage speculation algorithms.
So this Dynamic Voltage Speculation work in two parts 1. Conservative Speculation 2. Aggressive Speculation
Conservative Speculation :
Conservative Speculation :Conservative cores are more vulnerable to low-voltage operation.
To ensure correct execution, we add a small safety padding
when computing their margin voltage. Conservative cores are never allowed to run below the margin voltage
if correctable errors occur the governor raises its Vdd in increments of 10 mV per correctable error
If no error is observed for a while, the governor attempts to lower the Vdd again in 5 mV decrements after every minute
Decrementing the voltage continues until the margin voltage is reached again.Aggressive Speculation:
Aggressive Speculation:Aggressive cores can, in many cases, operate below the margin voltage.
The Voltage Speculation Governor gradually lowers Vdd below the margin as long as the error rate remains below the Max error threshold.
In our implementation, that threshold is 1 error per minute
Once that threshold is reached, the governor will maintain a constant Vdd and continue to monitor the error rate
Aggressive speculation ends if any of the following events occur:Correctable error rate exceeds the Max error thresh- old indicating approaching timing margins.Correctable error rate is below the Min error threshold.
A context switch is signaled by the OS indicating the need to reevaluate suitability for aggressive speculation
Aggressive Speculation: aggressive core running the stress test workload
Prototype Implementation:
Prototype ImplementationThe proposed voltage speculation system was prototyped on an HP Integrity Server that uses Intels Itanium 9560 processorsThere are two layers
Processor Abstraction Layer (PAL) : it is interface between SAL(System Abstraction Layer) and hardware power management, error record extraction. it provides hooks for communicating with the rest of System Firmware via architected entry- points. Our solution mainly uses PAL calls for extracting and clearing error information generated by the processor hardware.
System Abstraction Layer (SAL): main layerThere are two module in SALError Monitor for Margin DetectionVoltage Speculation Governor
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