8/10/2019 EC303 CHAPTER_4

1/48

EC303- COMPUTER ARCHITECTURE AND

ORGANIZATION

CHAPTER 4

ARITHMETIC LOGIC UNIT (ALU)

8/10/2019 EC303 CHAPTER_4

2/48

INTRODUCTION

The ALU is the part of the computer that actuallyperforms arithmetic and logical operations ondata. All of the other elements of the computersystem-control unit, registers, memory, I/O are

there mainly to bring data into the ALU for it toprocess and then to take the results back out.

An ALU and, indeed, all electronic components inthe computer are based on the use of simpledigital logic devices that can store binary digitsand perform simple Boolean logic operations.

8/10/2019 EC303 CHAPTER_4

3/48

4.1.1 Integer Representation

Only have 0 & 1 to represent everything

8 bits word could be used to represent the non-negative numbers from 0to 255.

Positive numbers stored in binary

e.g. 41=00101001

No minus sign and No period (radix point) for computer storage andprocessing

General - n-bit sequence: an-1 an-2 ..a1a0 is interpreted as unsigned integerA, then

n-1

A = 2i ai i=0

Representation of negative integers - Sign-Magnitude, ones complement,Twos complement, Biased

8/10/2019 EC303 CHAPTER_4

4/48

Left most bit is sign bit 0 means positive 1 means negative +24 = 00011000

-24 = 10011000 n-2 A = 2i ai , if an-1=0 i=0 General case A = n-2

A = - 2i

ai , if an-1 = 1 i=0

The rule for forming the negation of an integer is invertthe sign bit.

8/10/2019 EC303 CHAPTER_4

5/48

Conversion Between different bit

lengths

For taking n-bit integer and store in m bits,

m>n

For sign- magnitude, move the sign bit to the

new left-most position and fill in with zeros.

+18 = 0001 0010 (sign magnitude,8bits)

+18=0000 0000 0001 0010 (16 bits) -18= 1001 0010 (8 bits)

-18=1000 0000 0001 0010 (16 bits)

8/10/2019 EC303 CHAPTER_4

6/48

4.12 Design Binary Half Adder and Full Adder Using Boolean

Algebra

8/10/2019 EC303 CHAPTER_4

7/48

8/10/2019 EC303 CHAPTER_4

8/48

8/10/2019 EC303 CHAPTER_4

9/48

8/10/2019 EC303 CHAPTER_4

10/48

8/10/2019 EC303 CHAPTER_4

11/48

HAX

Y

S

C

HAX

Y

S

C

x

y

c

c

s

8/10/2019 EC303 CHAPTER_4

12/48

4.13 Manipulate Full Adder Gate Level To Create a

Parallel Binary Adder

8/10/2019 EC303 CHAPTER_4

13/48

8/10/2019 EC303 CHAPTER_4

14/48

8/10/2019 EC303 CHAPTER_4

15/48

Adding bigger binary numbers

A half adder has 4 logic gates

A full adder has two half adders plus a OR gate

Total of 9 logic gates

To add nbit binary numbers, you need 1 HA and n-1 FAs

To add 32 bit binary numbers, you need 1 HA and 31 FAs

Total of 4+9*31 = 283 logic gates

To add 64 bit binary numbers, you need 1 HA and 63 FAs

Total of 4+9*63 = 571 logic gates

15

8/10/2019 EC303 CHAPTER_4

16/48

4.14 Modify the Parallel Binary Adder to do Addition and

Subtration in a parallel Arithmetic Element

8/10/2019 EC303 CHAPTER_4

17/48

8/10/2019 EC303 CHAPTER_4

18/48

4.15 Operation of a Binary Coded Decimal Adder Using Full

Binary Adder and Half Binary Adder Block

8/10/2019 EC303 CHAPTER_4

19/48

8/10/2019 EC303 CHAPTER_4

20/48

8/10/2019 EC303 CHAPTER_4

21/48

8/10/2019 EC303 CHAPTER_4

22/48

8/10/2019 EC303 CHAPTER_4

23/48

8/10/2019 EC303 CHAPTER_4

24/48

8/10/2019 EC303 CHAPTER_4

25/48

4.2 Shift Register in ALU

IntroductionShift registers are a type of sequential logic circuit,

mainly for storage of digital data. They are a groupof flip-flops connected in a chain so that the

output from one flip-flop becomes the input ofthe next flip-flop.

Most of the registers possess no characteristicinternal sequence of states. All flip-flop is driven

by a common clock, and all are set or resetsimultaneously.

8/10/2019 EC303 CHAPTER_4

26/48

Shift Register Operation Shift registers, like counters, are a form of sequential logic. Sequential logic, unlike

combinational logic is not only affected by the present inputs, but also, by the prior history.

In other words, sequential logic remembers past events. Shift registers produce a discrete delay of a digital signal or waveform. A waveform

synchronized to a clock, a repeating square wave, is delayed by "n"discrete clock times,where "n"is the number of shift register stages. Thus, a four stage shift register delays"data in" by four clocks to "data out". The stages in a shift register are delay stages,typically type "D"Flip-Flops or type "JK"Flip-flops.

Serial data transmission, over a distance of meters to kilometers, uses shift registers toconvert parallel data to serial form. Serial data communications replaces many slow

parallel data wires with a single serial high speed circuit. Serial data over shorter distances of tens of centimeters, uses shift registers to get data

into and out of microprocessors. Numerous peripherals, including analog to digitalconverters, digital to analog converters, display drivers, and memory, use shift registers toreduce the amount of wiring in circuit boards.

Some specialized counter circuits actually use shift registers to generate repeatingwaveforms. Longer shift registers, with the help of feedback generate patterns so long thatthey look like random noise,pseudo-noise.

Basic shift registers are classified by structure according to the following types: Serial-in/serial-out

Parallel-in/serial-out

Serial-in/parallel-out

Universal parallel-in/parallel-out

Ring counter

8/10/2019 EC303 CHAPTER_4

27/48

Serial in/serial out shift registerSerial-in, serial-out shift registers delay

data by one clock time for each stage.

They will store a bit of data for each

register. A serial-in, serial-out shift register

may be one to 64 bits in length, longer if

registers or packages are cascaded.

Serial in/serial Out shift register using type D flip-

flop

8/10/2019 EC303 CHAPTER_4

28/48

Serial in/parallel out shift register

A serial-in/parallel-out shift register is

similar to the serial-in/ serial-out shift

register in that it shifts data into internalstorage elements and shifts data out at the

serial-out, data-out, pin. It is different in that

it makes all the internal stages available as

outputs. Therefore, a serial-in/parallel-out

shift register converts data from serial

format to parallel format. If four data bits

are shifted in by four clock pulses via a

single wire at data-in, below, the data

becomes available simultaneously on thefour Outputs QAto QDafter the fourth clock

pulse.

8/10/2019 EC303 CHAPTER_4

29/48

Parallel in/parallel out shift register

The purpose of the parallel-in/ parallel-out

shift register is to take in parallel data, shift it,

then output it as shown below. A universal

shift register is a do-everything device in

addition to the parallel-in/ parallel-out

function.

8/10/2019 EC303 CHAPTER_4

30/48

4-bit Parallel-Access Shift Register

(74HC195)

The 74HC195 can be used for parallel in/parallel out

operation, serial in/serial out and serial in/parallel

out operations. Q3 is the output when it is used for

parallel in/serial out operation.

8/10/2019 EC303 CHAPTER_4

31/48

4.2.1 Draw the shift register

(SN74195) gate level and Operation

Timing Diagram

8/10/2019 EC303 CHAPTER_4

32/48

4.2.2 Explain the shift Register Operation

FUNCTIONAL DESCRIPTION

The Logic Diagram and Truth Table indicate the functional characteristicsof the LS195A 4-Bit Shift Register. The device is useful in a wide variety of

shifting, counting and storage applications. It performs serial, parallel,

serial to parallel, or parallel to serial data transfers at very high speeds.

The LS195A has two primary modes of operation, shift right (Q0 " Q1) and

parallel load which are controlled by the state of the Parallel Enable (PE)

input. When the PE input is HIGH, serial data enters the first flip-flop Q0

via the J and K inputs and is shifted one bit in the direction Q0 " Q1 " Q2

"Q3 following each LOW to HIGH clock transition. The JK inputs provide

the flexibility of the JK type input for special applications, and the simple Dtype input for general applications by tying the two pins together.

8/10/2019 EC303 CHAPTER_4

33/48

When the PE input is LOW, the LS195A appears

as four common clocked D flip-flops. The data on the parallel

inputs P0, P1, P2, P3 is transferred to the respective Q0, Q1,Q2, Q3 outputs following the LOW to HIGH clock transition.

Shift left operations (Q3 "Q2) can be achieved by tying the Qn

Outputs to the Pn1 inputs and holding the PE input LOW.

All serial and parallel data transfers are synchronous,

occurring after each LOW to HIGH clock transition. Since theLS195A utilizes edge-triggering, there is no restriction on the

activity of the J, K, Pn and PE inputs for logic operation

except for the set-up and release time requirements.

A LOW on the asynchronous Master Reset (MR) input sets

all Q outputs LOW, independent of any other input condition.

8/10/2019 EC303 CHAPTER_4

34/48

8/10/2019 EC303 CHAPTER_4

35/48

4.3 Logical Operations in Arithmetic Logic Unit (ALU)

8/10/2019 EC303 CHAPTER_4

36/48

8/10/2019 EC303 CHAPTER_4

37/48

8/10/2019 EC303 CHAPTER_4

38/48

four possible

8/10/2019 EC303 CHAPTER_4

39/48

four possible

operations:

8/10/2019 EC303 CHAPTER_4

40/48

4bit arithmetic logic unit

8/10/2019 EC303 CHAPTER_4

41/48

4.4 Multiplexers in Arithmetic Logic Unit

Multiplexer(Mux)

A combinational circuit that receives binary information from one of 2n

input data lines and directs it to a single output line

A 2n-to 1 multiplexer has 2ninput data linesand

n input selection lines

8-input Digital Multiplexer - ability to select one bit of data from up to eight

sources.

Attaching the 8 source pins to digital sources / streams of information allowsthe designer to very easily select which source to enable, by use of three

selecting pins, the result will appear on the chip's output.

8/10/2019 EC303 CHAPTER_4

42/48

The ability to select one bit of data from up to eight sources.

Multiplexer(Mux)

A combinational circuit that

receives binary information from

one of 2ninput data lines and

directs it to a single output line

A 2n-to 1 multiplexer has 2ninputdata linesand n input selection

lines

4.4 Multiplexers in Arithmetic Logic Unit

8/10/2019 EC303 CHAPTER_4

43/48

4.4.2 Design Eight Input Multiplexers Gate Level

8/10/2019 EC303 CHAPTER_4

44/48

8/10/2019 EC303 CHAPTER_4

45/48

4.4.3 Design Two Multiplexers in a Single IC (SN54153)

l l l

8/10/2019 EC303 CHAPTER_4

46/48

Two multiplexers in single IC

(SN541543)

8/10/2019 EC303 CHAPTER_4

47/48

Two multiplexers in single IC at gate level

4 4 4 Sketch the Connection Between Four Flip-flop

8/10/2019 EC303 CHAPTER_4

48/48

4.4.4 Sketch the Connection Between Four Flip-flop

Register and Multiplexer Blocks