ece 260b – cse 241a testing 1 ece260b – cse241a winter 2005 testing website:

ECE 260B – CSE 241A Testing 1 http://vlsicad.ucsd.edu

ECE260B – CSE241A

Winter 2005

Testing

Website: http://vlsicad.ucsd.edu/courses/ece260b-w05


Outline

Defects and Faults

ATPG for Combinational Circuits

ATPG for Sequential Circuits


Fault models

Fault types: Functional.Timing.

Abstraction level: Transistor. (layout)Gate. (netlist)Macro ( functional blocks ).

Source Drain

Gate

D S

G

Open Shortgm

C

R

Vt

Delay

Parameter

11/2 2

Doping

l

w


Fault Models

0

1

sa0

sa1

(output)

(input)

Most Popular - “Stuck - at” model

x1

x2x3

Z

: x1 sa1

: x1 sa0 or

x2 sa0

Covers many otheroccurring faults, such asopens and shorts.


Fault Models

To detect an and-bridging

Detect a s-a-0 and b = 0

Detect b s-a-0 and a = 0

To detect a transition fault

Pattern 1: c = 1

Pattern 2: detect c s-a-1

c

a

b

good

bad

and

1


Problem with stuck-at model: CMOS open fault

x1 x2

x1

x2

Z

Sequential effectNeeds two vectors to ensure detection!

Other options: use stuck-open or stuck-short modelsThis requires fault-simulation and analysis at the switch ortransistor level - Very expensive!


Problem with stuck-at model: CMOS short fault

‘0’

‘0’

‘0’

‘1’

C

A B

D

A

B

C

D

Causes short circuit betweenVdd and GND for A=C=0, B=1

Possible approach:Supply Current Measurement (IDDQ)but: not applicable for gigascale integration


Exhaustive Algorithm

For n-input circuit, generate all 2n input patterns

Infeasible, unless circuit is partitioned into cones of logic, with < 15 inputs

Perform exhaustive ATPG for each cone Misses faults that require specific activation patterns for

multiple cones to be tested

M state regs

N inputs K outputs

K outputsN inputs

Combinational

Logic

Module

Combinational

Logic

Module

(a) Combinational function (b) Sequential engine

2N patterns 2N+M patterns


Flow chart for method

Use to get tests for 60-80% of faults, then switch to D-algorithm or other ATPG for rest

Random Pattern Generation


Fault simulation

Fault coverage found by fault simulations

Test patterns

Single faultsimulation model

Referenceresponse

Goodsimulation model

Compareresponse

Repeat for all possible stuck at zero/one faults

Requires long simulation times !.

Toggle test ( counts how many times each node has changed) can be used to get a first impression of fault coverage.


g = G (X1, X2, …, Xn) for the fault site

fj = Fj (g, X1, X2, …, Xn)

1 j m

Xi = 0 or 1 for 1 i n

Boolean Difference Symbolic Method (Sellers et al.)


Shannon’s Expansion Theorem:

F (X1, X2, …, Xn) = X2 F (X1, 1, …, Xn) + X2 F (X1, 0, …, Xn)

Boolean Difference (partial derivative):

Fj

g

Fault Detection Requirements (for g s-a-0):

G (X1, X2, …, Xn) = 1

Fj

g

= Fj (1, X1, X2, …, Xn) Fj (0, X1, …, Xn)

= Fj (1, X1, X2, …, Xn) Fj (0, X1, …, Xn) = 1

Boolean Difference (Sellers, Hsiao, Bearnson)


Basic Terms, Path Sensitization

Out

Techniques Used: D-algorithm, Podem

Goals: Determine input pattern that makes a faultcontrollable (triggers the fault, and makes its impactvisible at the output nodes)

sa011

0

11

10

1

Fault propagation

Fault enabling

Controllability: the ease of controlling the state of a node in the circuit

Observability: the ease of observing the state of a node in the circuit


5-Value Logic

0 – binary 0 in both good and fault circuit

1- binary 1 in both good and fault circuit

X – don’t care

D – binary 1 in good circuit, 0 in bad circuit

D – binary 0 in good circuit, 1 in bad circuit


Primitive D-Cube of Failure

Models circuit faults: Stuck-at-0 Stuck-at-1 Bridging fault (short circuit) Arbitrary change in logic function

AND Output sa0: “1 1 D”

AND Output sa1: “0 X D ”

“X 0 D ”

Wire sa0: “D”

Propagation D-cube – models conditions under which fault effect propagates through gate


Forward Implication

Results in logic gate inputs that are significantly labeled so that output is uniquely determined

AND gate forward implication table:


Backward Implication

Unique determination of all gate inputs when the gate output and some of the inputs are given


1 Fault Sensitization

2 Fault Propagation

3 Line Justification

Path Sensitization Method Circuit Example


Try path f – h – k – L blocked at j, since there is no way to justify the 1 on i

10

D

D1

1

1DD

D



Try simultaneous paths f – h – k – L and

g – i – j – k – L blocked at k because D-frontier (chain

of D or D) disappears

1

DD D

DD

1

1

1



Final try: path g – i – j – k – L – test found!

0

D D D

1 DD

1

0

1



D-Algorithm – Top Level

1. Number all circuit lines in increasing level order from PIs to POs;

2. Select a primitive D-cube of the fault to be the test cube;

3. D-drive ();

4. Consistency ();

5. return ();


D-Algorithm – Propagation

D-frontier: all gates whose output is X, at least one input is D or D

J-frontier: all gates whose output is defined, but is not implied by the input values


Step 1 – D-Drive – Set A = 1

D1 D

Example 7.2: Fault A sa0


D1

0

D

Step 2 – D-Drive – Set f = 0

D

Step 2 -- Example 7.2


D1

0

D

Step 3 – D-Drive – Set k = 1

D

1

D



D1

0

D

Step 4 – Consistency – Set g = 1

D

1

D

1



D1

0

D

Step 5 – Consistency – f = 0 Already set

D

1

D

1



D1

0

D

Step 6 – Consistency – Set c = 0, Set e = 0

D

1

D

1

0

0



D1

0

X

D

Step 7 – Consistency – Set B = 0

D-Chain dies

D

1

D

1

0

0

0

Test cube: A, B, C, D, e, f, g, h, k, L

D-Chain Dies -- Example 7.2


Example 7.3 – Fault s sa1

Primitive D-cube of Failure

1

Dsa1


Example 7.3 – Step 2 s sa1

Propagation D-cube for v

1

D

0

sa1 D1D



Forward & Backward Implications

1

Dsa1

0D

D

1 1

0

11



Propagation D-cube for Z – test found!

1

Dsa1

0D

D

1 1

0

11

1

D


PODEM High-Level Flow

1. Assign binary value to unassigned PI

2. Determine implications of all PIs

3. Test Generated? If so, done.

4. Test possible with more assigned PIs? If maybe, go to Step 1

5. Is there untried combination of values on assigned PIs? If not, exit: untestable fault

6. Set untried combination of values on assigned PIs using objectives and backtrace. Then, go to Step 2


Select path s – Y for fault propagation

sa1

Example 7.3 -- Step 1 s sa1


Initial objective: Set r to 1 to sensitize fault

1

sa1




Backtrace from r

1

sa1



Set A = 0 in implication stack

1

0

sa1



Forward implications: d = 0, X = 1

1

sa1

00

1



Initial objective: set r to 1

1

sa1

00

1



Backtrace from r again

1

sa1

00

1



Set B to 1. Implications in stack: A = 0, B = 1

1

sa1

00

1

1


D

Example 7.3 -- Step 9 s sa1 Forward implications: k = 1, m = 0, r = 1, q = 1, Y = 1, s

= D, u = D, v = D, Z = 1

1

sa1

1

0

1

1

DD

1

0

1

0

1


Backtrack -- Step 10 s sa1

X-PATH-CHECK shows paths s – Y and s – u – v – Z blocked (D-frontier disappeared)

1

sa1

00

1


Step 11 -- s sa1

Set B = 0 (alternate assignment)

1

sa1

0

0


Backtrack -- s sa1

1sa1

00

1

0 1

0

1

01

01

Forward implications: d = 0, X = 1, m = 1, r = 0,

s = 1, q = 0, Y = 1, v = 0, Z = 1. Fault not sensitized


Step 13 -- s sa1

Set A = 1 (alternate assignment)

1

sa1

1


Step 14 -- s sa1

Backtrace from r again

1

sa1

1


Step 15 -- s sa1

Set B = 0. Implications in stack: A = 1, B = 0

1

sa1

1

0


Backtrack -- s sa1

Forward implications: d = 0, X = 1, m = 1, r = 0. Conflict: fault not sensitized. Backtrack

sa1

1

0

0

0

1

1

1

1

10

01


Step 17 -- s sa1

Set B = 1 (alternate assignment)

1

sa1

1

1


Fault Tested -- Step 18 s sa1

Forward implications: d = 1, m = 1, r = 1, q = 0, s = D, v = D, X = 0, Y = D

1

sa1

1

1

11

0

D

0

D

D

X

D


Comparison

Path sensitization: multiply SAT problems

D-algorithm: decisions are made at the J-frontier

PODEM: decisions are made at the PIs

FAN: Multiply paths are traced back simultaneously A decision can be made at a headline


Algorithm

D-ALGPODEMFANTOPSSOCRATESWaicukauski et al.ESTTRANRecursive learningTafertshofer et al.

Est. speedup over D-ALG(normalized to D-ALG time)17232921574 2189 8765 3005 48525057

Year

1966198119831987198819901991199319951997

History of Algorithm Speedups


Sequential Circuits: State! Combinational circuit testing is relatively easy

Sequential circuit testing needs to drive sequential elements to specific state to test a fault

M state regs

N inputs K outputs

K outputsN inputs

Combinational

Logic

Module

Combinational

Logic

Module

(a) Combinational function (b) Sequential engine

2N patterns 2N+M patterns


Sequential Circuit Controllability and Observability

CONTROLABILITY: The ease of controlling the state of a node in the circuit.

OBSERVABILITY: The ease of observing the state of a node in the circuit

Example: 4 bit counter with clear

clr

q3q2q1q0

Control of q3:

Set low: perform clear = 1 vector

Set high : perform clear + count to 1000B = 9 vectors

Testing a node in a circuitA: Apply sequence of test vectors to circuit which sets node to demanded

state.B: Apply sequence of test vectors to circuit which enables state of node to

be observed.C: The observing test vector sequence must not change state of node.


Ad-hoc Test

Inserting multiplexer improves testability

I/O bus

Memory

Processor

data

addr

ess

I/O bus

Memory

Processor

data

addr

ess

selecttest


Scan-based Test

Logic

Combinational

Logic

Combinational

Reg

iste

r

Reg

iste

r

OutIn

ScanOutScanIn

A B


Scan-based Test —Operation

TestScanIn

Test

Latch

In0

Out0

Test Test

Latch

In1

Out1

Test Test

Latch

In2

Out2

Test Test

Latch

In3

Out3

ScanOut

Test

1

2

N cycles 1 cycleevaluationscan-in

N cyclesscan-out


Scan-Path Testing

Partial-Scan can be more effective for pipelined datapaths

REG[5]

REG[4]

REG[3]REG[2]

REG[0]REG[1]

+

COMP

OUT

SCANIN

COMPIN

SCANOUT

A B


Boundary Scan (JTAG)

Printed-circuit board

Logic

scan path

normal interconnect

Packaged IC

Bonding Pad

Scan-in

Scan-out

si so

Board testing becomes as problematic as chip testing


Self-test

(Sub)-Circuit

Under

Test

Stimulus Generator Response Analyzer

Test Controller

Rapidly becoming more important with increasingchip-complexity and larger modules


Design verification testing

Specification(text)

Behavioural model(Verilog, Spice, etc.)

Design:Full custom,Standard cell,Gate array

Produced chip

Application

Does model complywith specification ?

Does design have samebehaviour as model ?

Does design work ?Does chip workas specified ?( 50 % )

Does chip work in application ?(50 % * 50 % = 25 %)

Does specification complywith application ? (50 %)

How do we find outwhat’s wrong ?

Sufficient margins forproduction variations ?

Low quantity

Reliability ?

Is it testable in production ?

(10- 50% of total development costs)

Imperfect designs are often accepted in HEP if ways around bugs can be found.

(Can be improved by System - IC behavioural modelling)


Production testing

Packaged

Wafer

Bare dieBurn-in ?

Functional test:fault coverage, stuck at 0/1

Internal speed test:clocking speed

External speed test:setup time, hold time,

I/O level test:output levels, input thresholds

Analog parameters:gain, noise, time constants,precision, etc.

Margins ? (noise, measurement accuracy, etc.)Temperature ?.Supply voltage ?External loads ?

MCM

delay

(Production test pattern development 5 - 25 % of development costs)(Production test 20 - 50% of final chip cost)

Monitoring of radiation resistance (destructive test)


Cost of finding failing chip

LEVEL FAILURE MECHANISM PRICE

Wafer Yield, speed, noise, gain 1$

Chip Cutting, bonding 10$

ModuleSoldering, ESD 100$ 100 $

SystemCables, connectors 1000$ 100 $

At customerReliability of components,vibrations, corrosion, 10.000$ GOLDradiation, high voltage

(MCM)

(Sub)

Design

PrototypeVerification,Qualification,Production margins

SpecificationFunctionality, PerformanceTestability, reliabilityInteroperability

1$

1000$ 100 $

100.000$ GOLD

Designverificationtesting

Productiontesting

( price per design)

(price per chip)

100K$ - ? $(if not sufficient design verificationperformed)


Thanks

ece 260b – cse 241a testing 1 ece260b – cse241a winter 2005 testing website:

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