Project Report

On

4 bit synchronous ALU (Arithmetic Logic Unit) using 250 nm SOI technology

Team:

1. Bhavana Byreddy (UIN-657869795)2. Lakshmi Yasaswi Kamireddy3. Sai Chinmayananda Korlimarla 4. Shashikala Kodandaraman

Problem Description:

To Design (Both Schematic & Layout) a 4 bit synchronous ALU (Arithmetic Logic Unit) using 250 nm SOI technology that will be able to perform the following functions based on provided operation codes (op. codes). The function is selected through control lines s2, s1, s0, the input is evaluated using the respective function. The output is stored in a 4-bit output register which is implemented using a D -flip-flop design.

The functions and their op-codes are mentioned below.

4 bit Addition (op. code 000) 2's Complement of A (op. code 001) 4 bit Add-traction (op. code 010) 4 input NAND operation using a NAND gate (op. code 011) 4 input NOR operation using a NOR gate (op. code 100) 1's Complement of B (op. code 101)

ALU

An arithmetic logic unit (ALU) is a digital electronic circuit that performs arithmetic and bitwise logical operations on integer binary numbers. In this project, a 4-bit ALU is designed, implemented and simulated using Cadence.

The ALU supports 4 bit addition, 2’s complement, 1’s complement, add-traction, NAND and NOR operations.

The operations are selected using the select lines S0, S1, S2 as follows

S0 S1 S2 OPERATION0 0 0 Addition0 0 1 2’s compliment0 1 0 Add-traction0 1 1 NAND1 0 0 NOR1 0 1 1’s compliment

ALU DESIGN

SCHEMATIC:

SYMBOL:

LAYOUT:

The placement of the components in the layout is as follows

Layout :

DRC check for layout:

DRC is performed for layout and ensured that there are no errors. Layout is designed in such a way that area is minimized.

Extracted view:

LVS Check:

SIMULATIONS:

Addition:

When the select lines S0 S1 S2 were set at 000, the operation selected was addition, the transient analysis of the ALU was as follows

2’s comp

When the select lines S0 S1 S2 were set at 001, the operation selected is 2’s compliment, the transient analysis of the ALU was as follows

Addtraction

When the select lines S0 S1 S2 were set at 010, the operation selected was addtraction, the transient analysis of the ALU was as follows

NAND:

When the select lines S0 S1 S2 were set at 011, the operation selected was NAND, the transient analysis of the ALU was as follows

NOR:

When the select lines S0 S1 S2 were set at 100, the operation selected was NOR, the transient analysis of the ALU was as follow

1’s Complement

When the select lines S0 S1 S2 were set at 101, the operation selected was 1’s compliment, the transient analysis of the ALU was as follows

All the schematic and layout designs and simulation of the functional units that were used in ALU are shown below

2’s Compliment

Schematic:

Layout :

LVS Check:

1. FULL ADDER:

Schematic:

Layout:

LVS Check:

2. NAND:

Schematic

Layout:

LVS Check:

3. NOR:

Schematic

Layout:

LVS Check:

4. ADDTRACTION:

Schematic

DRC Check:

LVS Check:

5. 1’s Compliment:

Schematic

Layout:

LVS Check:

6. 8*1 MUX:

Schematic:

Layout:

LVS Check:

7. 4 – Bit Register

Schematic:

Layout:

LVS Check:

Without Parasitics Final ALU simulations:

NOR:Net 63 to 69 ---A0 to A3Net 71 to 77 ---B0 to B3Net 79 -clkNet 81 to 85 ---S0 to S2Net 106 to 103 ---OPs

2’s compliment:

With Parasitics:

Conclusion:

Thus, schematic and layout of 4 bit synchronous ALU (Arithmetic Logic Unit) using 250 nm SOI technology are generated and simulations are performed by obtaining transient analysis.