ece 550d fundamentals of computer systems and engineering fall...

ECE 550DFundamentals of Computer Systems and Engineering

Fall 2017

Finite State Machines

Prof. John Board

Duke University

Slides are derived from work byProfs. Tyler Bletsch and Andrew Hilton (Duke)

2

Last time…

• Who can remind us what we did last time?

• Storage and Clocking

• Latches

• Flip-flops

• Level vs Edge triggered

3

Finite Storage = Finite States

• Computers have finite storage (inside processor):

• Design in fixed number of DFFs

• Result: finite number of states (N bits => 2N states)

• Useful to talk about finite state machines

• Ubiquitous in processor design

• Basically how the processor works out many multi-step processes

• We will see a couple of very simple finite-state machines designed manually, but then you will rely on Quartus to handle most of the details for you

4

4

General structure

Combinational

Logic

Flip

Flops

Combinational

Logic

Primary

Inputs WPrimary

Outputs Z

Clock

Tip: if you go further into digital design

in ECE559, understanding this dashed line

and the difference between Mealy and Moore

machines will be critical! But we gloss over it in

550.

• A finite state machine has primary inputs, primary outputs, and

a present “state” encoded as a value on flip flops

• A FSM is defined by two functions: the next state function,

which tells us the next state given the present state and the

present inputs

• And the output function, defined by the present state and

(possibly) the present inputs

5

Electronic lock (sequence recognizer)

• want a circuit with 3 buttons that recognizes pattern 3-2-1 –activates solenoid to unlock door when received.

5

initial

1,2,-/-3/-

first_ok

1/-

second_ok2/-

2,3/-

1/Solenoid_on

“State Diagram” for

a Mealy-type Finite

State Machine

“dash” – means “no

button pushed this clock

cycle”

call the states I,F,S

For now, can’t push

more than one

button at a time! (one-hot

inputs, or no inputs)

3,-/-

-/-

We should see an arrow from every state for every possible input (which here includes

“no input”!)

6

Electronic lock (sequence recognizer)

• want a circuit with 3 buttons that recognizes pattern 3-2-1 –activates solenoid to unlock door when received.

6

initial

1,2,-/-3/-

first_ok

1/-

second_ok2/-

2,3/-

1/Solenoid_on

“State Diagram” for

a Mealy-type Finite

State Machine

“dash” – means “no

button pushed this clock

cycle”

call the states I,F,S

For now, can’t push

more than one

button at a time!

3,-/-

-/-

Technical detail: probably want to recognize

button being released – why?

or else have button push generate a pulse

7

State transition table7

Next State

Present input 321

Present output Solenoid_on

Present input 321

Present

state

000 001 010 100 000 001 010 100

I I I I F 0 0 0 0

F F I S F 0 0 0 0

S S I I I 0 1 0 0

3 states needs 2 flip flops to encode. (Arbitrary) State assignment with flip-flops F1,F0

F1 F0

I 0 0

F 0 1

S 1 0

assumes 0 or 1 button pushed at a time – 1-hot and 000 are legal

8

8

Implementation

Next State

Present input 321

Present output

Solenoid_on

Present input 321

Present state

Q1Q0

000 001 010 100 000 001 010 100

00 00 00 00 01 0 0 0 0

01 01 00 10 01 0 0 0 0

10 10 00 00 00 0 1 0 0

Pick D flip-flops with inputs

D1, D0 and outputs Q1,Q0

9

9

Implementation

Output is in Mealy form, depending on both state and present inputs

123

12123

,123123123

123123

01

01010

0101010

01011

QQtSolenoidOu

QQQQD

orQQQQQQD

QQQQD

Next State

Present input 321

Present output

Solenoid_on

Present input 321

Present state

Q1Q0

000 001 010 100 000 001 010 100

00 00 00 00 01 0 0 0 0

01 01 00 10 01 0 0 0 0

10 10 00 00 00 0 1 0 0

10

10

Implementation

Old School Design

11

Transition function

• State diagrams describes transition function pictorially

• next_state = f (inputs, current_state)

• Easy to translate into (approximate) VHDL (when we let it do state management for us)

state_d <= F when state_q = I and THREE and !TWO and !ONE else

F when state_q = F and !TWO and !ONE else

S when state_q = F and !THREE and TWO and !ONE else

S when state_q = S and !THREE and !TWO and !ONE else

I ;

…

Why state_d and state_q?

Will latch state in DFFs from

one cycle to next.

state_d = next one

state_q = current one

12

Output function

• Also need an output function:

• Easy here

Solenoid <= 1 when state_q = S and !THREE and !TWO and ONE else

0 ;

13

Large number of similar states

• Sometimes have large # of similar states

• E.g., instead of I, F, S, may have 0 to 200

• Example: VGA controller….

• Painful:

• Actually have NSg0, …NSg200 states

• Easier

• NSg state, and a counter.

• Transition to next state on counter_q = 200

14

Second quick example – vending machine

• Items cost 15 cents, the machine takes nickles (5 cents) and dimes (10 cents)

14

S0

S1 S2

S3

S7

[Open]

S4

[Open]

S5

[Open]

S6

[Open]

S8

[Open]

N D

N D

N D

N D

0¢

Reset Reset

5¢

10¢

15+¢

[Open]

N

N

N,D

D

D

Observe:

S3==S2

S4==S5==S6==S7==S8

15

15

State Transition Table

Present Inputs Next Output(s)

State D N State Open

0¢ 0 0 0¢ 0

0 1 5¢ 0

1 0 10¢ 0

1 1 d d

5¢ 0 0 5¢ 0

0 1 10¢ 0

1 0 15+¢ 0

1 1 d d

10¢ 0 0 10¢ 0

0 1 15+¢ 0

1 0 15+¢ 0

1 1 D D

15+¢ X X 15+¢ 1

16

16

Encoded State Transition Table

Present State Inputs Next State Output(s)

Q1 Q0 D N D1 D0 Open

0 0 0 0 0 0 0

0 1 0 1 0

1 0 1 0 0

1 1 d d d

0 1 0 0 0 1 0

0 1 1 0 0

1 0 1 1 0

1 1 d d d

1 0 0 0 1 0 0

0 1 1 1 0

1 0 1 1 0

1 1 d d d

1 1 0 0 1 1 1

0 1 1 1 1

1 0 1 1 1

1 1 d d d

4 states

require

2 flip-flops

to implement.

Arbitrarily

choose

D flip-flops.

Choose

arbitrary

encoding:

Q1Q0

0 0 0¢

0 1 5¢

1 0 10¢

1 1 15+¢

17

17

Design

• Using D flip flops, again very simple logic for D1, D0, Open (exploiting don’t cares)

• D1=Q1 + D + Q0N

• D0=Q0N’ + Q0’N + Q1N + Q1D

• Open = Q1Q0 (Moore machine)

• This is an AWFUL vending machine!• No reset logic! Eats money! Doesn’t make change!

• Rather user-unfriendly design!

• Improvements: change, multiple items, multiple price items, item out indicators, coin return button….

18

Take a moment to draw an FSM…

• Take a minute to draw an FSM for a more elaborate combination lock

• Combination: 12345

“So the combination is... one, two, three, four, five? That's the stupidest combination I've ever heard in my life! That's the kind of thing an idiot would have on his luggage!”—Dark Helmet (Spaceballs, the movie)

• Inputs:• One hot is_0, is_1, is_2, …

• Outputs:• Unlock

• Draw transitions as state diagram, note which states have unlock on.

• Feel free to abbreviate “all other cases” by leaving arrow label blank

https://www.youtube.com/watch?v=a6iW-8xPw3k

19

Combination Lock

• is_1 always takes us to S1

• Correct input moves us “right”

• Other: back to start

• S5 unlocks

Start S1is

_1

is_1

S2

is_

2

S3

is_3

S4

is_4

S5

is_

5

(others)

20

VGA controller: FSM

• Hwk2 will have FSM to implement in VHDL

• VGA controller

• Scan row from left to right, sending out data pixel by pixel

• One pixel per cycle

21

VGA controller: FSM


• VGA controller



• Then period of black (all 0 pixel) with some control signals

• “Past” the right edge

• Actually three different states here.

22

VGA controller: FSM


• VGA controller



• Then period of black (all 0 pixel) with some control signals

• “Past” the right edge

• Then restart on next row

23

VGA controller: FSM

• VGA controller

• After last row, similar behavior to horizontal

24

VGA controller: FSM

• VGA controller


• Trace blank rows

• All black, goes through same horizontal states as real rows

• Also three different states.

25

VGA controller: FSM

• VGA controller


• Trace blank rows

• All black, goes through same horizontal states as real rows

• Also three different states.

• Then reset to top left corner

26

VGA on hwk2

• More details in hwk2 assignment

• Can think of as one big state machine

• Or two working together (one horizontal, one vertical)

27

Division: math with an FSM

• We have talked about add, sub

• Pretty easy math to implement in hardware

• What about divide?

• Much more complicated

• Multi-step process

• Well suited to FSM

45673

3

15

15

06

6

07

6

13

12

1

3

15224 R 1

28

Division: Binary

• Binary long division similar to decimal

• But a little simpler, because it goes in 1 or 0 times

10110111

29

Division: Binary



10110111

11 > 1

0

1

30

Division: Binary



10110111

11 > 10

00

10

31

Division: Binary



10110111

11 <= 101

001

101

32

Division: Binary



10110111

101 – 11 = 10

001

10

33

Division: Binary



10110111

11 <= 101

0011

101

34

Division: Binary



10110111

101 – 11 = 10

0011

10

35

Division: Binary



10110111

11 <= 100

00111

100

36

Division: Binary



10110111

100 – 11 = 1

00111

1

37

Division: Binary



10110111

11 <= 11

001111

11

38

Division: Binary



10110111

11– 11 = 0

001111

0

39

Division: Binary



• 45 / 3 = 15 remainder 0

10110111001111 = Answer

Remainder =0 Done

40

Division FSM/Circuit

• 32 bit division: 32 states (5 bits)

• Decrement state # each cycle (count down which bit)

Remainder

(Register)<<1

q Answer

(Register)<<1

q

Dividend

(Register)

Divisor

(Register)

State

(Register)

-1

q

Mux

32

d

31

32

d31

<?

d

32sub

Mux

5

41


• Use State # to pick out which bit of Dividend

Remainder

(Register)<<1

q Answer

(Register)<<1

q

Dividend

(Register)

Divisor

(Register)

State

(Register)

-1

q

Mux

32

d

31

32

d31

<?

d

32sub

Mux

5

42


• Shift remainder left 1, concatenate dividend bit at right

Remainder

(Register)<<1

q Answer

(Register)<<1

q

Dividend

(Register)

Divisor

(Register)

State

(Register)

-1

q

Mux

32

d

31

32

d31

<?

d

32sub

Mux

5

43


• Check if divisor is < result… used for two things

• Mux selector on remainder_d

• Lowest bit of answer_d

Remainder

(Register)<<1

q Answer

(Register)<<1

q

Dividend

(Register)

Divisor

(Register)

State

(Register)

-1

q

Mux

32

d

31

32

d31

<?

d

32sub

Mux

5

44


• For answer, shift old answer <<1, concatenate in < result

Remainder

(Register)<<1

q Answer

(Register)<<1

q

Dividend

(Register)

Divisor

(Register)

State

(Register)

-1

q

Mux

32

d

31

32

d31

<?

d

32sub

Mux

5

45


• For remainder, pick from two things (based on < result)

• Result of shifting old remainder and concatenating dividend bit

• That minus the divisor

Remainder

(Register)<<1

q Answer

(Register)<<1

q

Dividend

(Register)

Divisor

(Register)

State

(Register)

-1

q

Mux

32

d

31

32

d31

<?

d

32sub

Mux

5

46

Summary

• Finite State Machine

• Finite states (encoded in some way: binary nums, one-hot…)

• Transition function: (state * inputs) -> state

• Helpful to draw as diagram

• Output function: (state * inputs) -> outputs

• Examples:

• Traffic Light

• VGA controller (hwk2)

• Division

• Plus learned division algorithm

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