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ECE PhD Qualifying Exams

Presentation Schedule

Fall 2020

ECE QE Presentation Schedule Fall 2020Slide Number Last Name First Name Date Time Venue Title PhD Advisor

4 Balagopal Gokul 10/30/2020 3:00 PM Webex Virtual Meeting Calibration of Airborne Particulate Sensors using Machine Learning Lary David5 Brigner Wesley Hayden 11/09/2020 12:45 PM Webex Virtual Meeting Biomimetic Devices for a Purely Spintronic Neuromorphic Architecture Joseph S. Friedman6 Chitale Akshay A 11/05/2020 1:30 PM Webex Virtual Meeting Hardware Acceleration for Analog Circuit Analysis Yun Chiu7 Chowdhury Prattay 10/16/2020 1:00 PM Webex Virtual Meeting Approximation of Behavioral Heterogeneous SoCs Benjamin Carrion Schaefer

8 Daniar Ahmad 10/19/2020 2:00-3:00PM Webex Virtual Meeting Design and modeling of the planar matrix transformer for LLC resonant converter Bilal Akin

9 Dutta Satwik 11/05/2020 10:00-11:00AM Webex Virtual Meeting Advancing speech activity detection for automatic speech assessment of pre-school children prompted speech John H.L. Hansen

10 Edwards Alexander James 10/21/2020 1:00 PM Webex Virtual Meeting Reservoir Computing with Frustrated Nanomagnets Joseph S. Friedman11 Farhadi Masoud 10/19/2020 2:00-3:00PM Webex Virtual Meeting Reliability And Condition Monitoring Of SiC Power MOSFETs Bilal Akin

12 Farooq Muhammad Musab 11/09/2020 1:00 PM Webex Virtual Meeting Design and demonstration of antenna-coupled Schottky diodes in a

foundry complementary metal-oxide semiconductor (CMOS) technology for electronic detection of far-infrared radiation

Kenneth O

13 Guo Haidong 11/11/2020 9:00-10:00AM Webex Virtual Meeting Digitally Modulated CMOS Polar Transmitters for Highly-Efficient mm-Wave Wireless Communication Kenneth O

14 Kapoor Pinky 10/29/2020 10:30 AM Webex Virtual Meeting Direction of arrival estimation with co-prime array Aria Nosratinia

15 Kovalyov Anton 11/02/2020 2:00 PM Webex Virtual Meeting Arbitrary Microphone Array Optimization Method Based on TDOA for Specific Localization Scenarios Issa Panahi

16 Kumar Hiranya Garbha 11/4/2020 11:00 AM Webex Virtual Meeting A survey on hand gesture recognition for Mixed reality applications B. Prabhakaran17 Kundu Shamik 10/15/2020 9:00-10:00AM Webex Virtual Meeting Towards Functional Safety of Deep Learning Hardware Accelerators Kanad Basu

18 Kuruvila Abraham Peedikayil 10/15/2020 8:00-9:00 AM Webex Virtual Meeting Defending Hardware-based Malware Detectors against Adversarial Attacks Kanad Basu

19 Lin Dayang 11/09/2020 10:00 AM Webex Virtual Meeting High Response Speed of Imprinted Organometal Halide Perovskite Photodetectors Qing Gu

20 Mahmoodi Nasrabadi Hazhir 11/02/2020 10:00 AM Webex Virtual Meeting Simulation, Fabrication, and Characterization of AFM cantilevers S. O. Reza Moheimani21 Meng Xingyu 10/15/2020 10:00-11:00AM Webex Virtual Meeting Concolic Testing on RTL for Detecting Security Vulnerabilities Kanad Basu

22 Mishra Richa 11/11/2020 10:00 AM Webex Virtual Meeting Observer based estimation of disturbances in topographic imaging by STM S. O. Reza Moheimani

ECE QE Presentation Schedule Fall 2020Slide Number Last Name First Name Date Time Venue Title PhD Advisor

23 Moore Francois 10/12/2020 3:30 PM Webex Virtual Meeting Gaussian noise model for estimation of non linear effects in a fiber

based network: Applications and Limitations in a multi vendor agnostic Open Line System

Andrea Fumagalli

24 Murillo Borjas Bayron Lennin 10/14/2020 10:30 am Webex Virtual Meeting Towards High Speed and Small Footprint Nano-LEDs Qing Gu

25 Murugesan Goutham Kumarasamy 11/10/2020 2:00-3:00PM Webex Virtual Meeting A Fully Integrated Transformer-Coupled Power Detector With 5 GHz RF PA for WLAN 802.11ac in 40 nm CMOS Kenneth O

26 Ni Aoxin 11/17/2020 10:00-11:00AM Webex Virtual Meeting Literature Survey of Contact and Noncontact Signal/Image Processing Approaches for Physiological Measurements Nasser Kehtarnavaz

27 Nikfarjam Hamed 11/17/2020 11:00 AM Webex Virtual Meeting Comparative Study of Electrical Biosensing Technologies Siavash Pourkamali

28 Ramanathan Shunmugapriya 11/02/2020 11:00 AM Webex Virtual Meeting Low-latency and high-throughput software turbo decoders on multi-core architectures Andrea Fumagalli

29 Safaoui Sleiman 10/30/2020 3:30 PM Webex Virtual Meeting Temporal Logics in Robotics and Control Tyler Summers30 Shariff Sarfraz Habibullah 11/10/2020 3:00-4:00 PM Webex Virtual Meeting CMOS On-chip Phase-Noise Measurement Techniques Kenneth O

31 Tang Yijie 11/16/2020 3:00 PM Webex Virtual Meeting Self-Powered Analog/RF Hardware Trojan in a Standards Compliant Wireless Network Yiorgos Makris

32 Wang Zhenyu 11/05/2020 11:30-12:45PM Webex Virtual Meeting Cross-domain Adaptation with Discrepancy Minimization for Text-independent Forensic Speaker Verification John H.L. Hansen

33 Weng Sean Bang Li 11/12/2020 3:00 PM Webex Virtual Meeting Transistor-level Programmable Fabric using the GF 12nm process Carl Sechen

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Calibration of Airborne Particulate Sensors using Machine Learning

Gokul BalagopalOctober 30, 2020 3:00 PM

Abstract:

PhD Advisor: Dr. Lary David

Airborne particulates (aerosols) are criterion pollutants that have a wide variety of human health impacts as well as playing key roles in bothatmospheric radiative transfer and atmospheric chemistry. The usual instruments that environment agencies (such as the US EPA) use to measureairborne particulates are expensive, ranging from $100k to $1m. Extensive street level surveys carried out by UT Dallas with a spatial resolution of about1 m have shown that to adequately characterize the spatial variability of the abundance of airborne particulates ata neighborhood scale we need to make measurements with a spatial resolution of 0.5 km. For this to be economically feasible we need to useeconomically priced sensors. The purpose of this study is to show that we can build low cost sensors and then use machine learning to accuratelycalibrate them against primary reference sensors. For accurate calibration of the aerosol sensors it is critical that measurements of the atmosphericpressure, humidity and temperature are also made. Over the next year we hope to deploy over 100 sensors across theDFW area. A live map displaying the data from the sensors as they are deployed is available at https://www.sharedairdfw.com/. The low cost (tertiary)sensors that are described in this thesis are solar powered and communicate with a central gateway using a LoRa network. Each gateway has a wirednetwork connection or cellular modem and includes a secondary aerosol sensor and a suite of other environmental sensors measuring a variety ofgasses, light levels, lightning and ionizing radiation. These sensors are being deployed across DFW with the support of a broad consortium of includingthe DOD, EPA, the City of Plano, Dallas County Community College District, Paul Quinn University, Plano ISD, Richardson ISD and the community groupDown-winders at Risk.

Webex Meeting Number: 133 606 1406Webex Meeting Password: nPTqSWxv593

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Biomimetic Devices for a Purely Spintronic Neuromorphic Architecture

Wesley Hayden BrignerNovember 09, 2020 12:45 PM

Abstract:

PhD Advisor: Dr. Joseph S. Friedman

Even though standard complementary metal oxide semiconductor (CMOS) based von Neumann architectures are highly adept at processing structured data, their binary and non-volatile nature significantly decreases their efficiency when processing real-world, unstructured information. For instance, in 2016, an advanced artificial intelligence named AlphaGo was pitted against world-renowned professional Go player Lee Sedol. Although AlphaGo won 4 out of the 5 total games played, it consumed more than 500 times as much power and more than 1000 times the space of a human brain. In order to resolve the issue of the massive size and power consumption of neuromorphic computing, researchers investigated the use of a branch of beyond-CMOS computing known as spintronics. A number of spintronic devices have already been proposed to this end, but they require a considerable amount ofCMOS circuitry to operate, which results in a considerably higher power consumption, area overhead, and fabrication complexity. The research presented here aims to develop a purely spintronic neuromorphic system, thereby eliminating the need for this external circuitry.

Webex Meeting Number: 145 099 0083Webex Meeting Password: NPeFDjm3d35

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Hardware Acceleration for Analog Circuit Analysis

Akshay A. ChitaleNovember 5, 2020 1:30 PM

Abstract:

PhD Advisor: Dr. Yun Chiu

Circuit simulation is a necessary step to verify functionality when designing analog circuits. However, executing a simulation on a single processor may not be sufficiently fast, especially if many simulations need to be performed or if the circuit has a long settling time. Additional hardware such as GPUs and FPGAs, respectively, can greatly accelerate those simulations. For parallelizable tasks such as Monte Carlo simulations, simply adding more processor cores can also result in a significant speedup.

Webex Meeting Number: 133 916 6473Webex Meeting Password: 7AQdJxMMi77

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Approximation of Behavioral Heterogeneous SoCs

Prattay ChowdhuryOctober 16, 2020 1:00 PM

Abstract:

PhD Advisor: Dr. Benjamin Carrion Schaefer

Approximation computing has shown to be an effective approach to generate smaller and more power efficient circuits bytrading off the accuracy of the circuit vs. area/power. So far, most work on approximate computing has focused on specificcomponents within a system. This severely limits the approximation potential as most Integrated Circuits (ICs) are nowcomplex heterogenous systems. This presentation addresses the question of how to approximate multiple componentswithin a larger heterogenous System-on-Chip (SoC) such that the overall system is optimized while meeting a givenmaximum error threshold. The salient idea is to find the best mixes of approximation across all the components in thesystem such that the target metric (area or energy) is minimized within the target maximum error. This presentationconsiders the Analog-to-Digital Converter (ADC), CPU, hardware accelerators and interconnect between all thesecomponents. Moreover, to quickly measure the effect of different approximation mixes, a framework has been developedthat allows to generate complete SoCs at the behavioral level through a bus generator and a library of synthesizable businterfaces. This enables to use fast simulation models (transaction and cycle-accurate) to accurately measure the error atthe system's output while measuring the benefit in terms of area or energy reduction of different mixes of approximations.

Webex Meeting Number: 133 046 5316Webex Meeting Password: AmaYNnPH563

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Design and modeling of the planar matrix transformer for LLC resonant converter

Ahmad DaniarOctober 19, 2020 2:00 PM - 3:00 PM

Abstract:

PhD Advisor: Dr. Bilal Akin

In this presentation, at first, a new structure for a 3×1 matrix transformer is developed. The structure is based on three transformer elements that are integrated into a single component. Utilizing "flux cancellation" concept the structure is then improved in terms of flux density distribution, core loss, core size and even copper loss. As previously mentioned, an integrated design includes two inductors which need to be tuned in such a way that resonate tank operates at the desired frequency. Hence, designing a transformer with tuned parameters is an iterative process that requires an accurate and fast tool. Typically Finite Element Analysis (FEA) is the most accurate and generally accepted method for electromagnetic performance prediction of a transformer. However due to the particular structure of some transformer cores and also the high sensitivity of the magnetic parameters, 2-D FEA analysis cannot be employed because of the significant inaccuracy. 2-D FEA simulation only considers a cross section of the core and assigns a constant value as the core depth. But as previously mentioned, some core parts have different depth so 2-D simulation would be ineffective. In some cases there is more than 30% error for 2-D simulations. As a result, 3-D FEA which is very time consuming should be utilized. As a result, in the next step, a model based on Magnetic Equivalent Circuit (MEC) for tuning the inductances of the resonance tank is proposed. Multiple winding arrangements based on level of interleaving are then investigated to see the changing rate of leakage inductance. The model is fast enough that can be used as a design tool for magnetic parameters tuning of the transformer. Finally, validation and error analysis of the proposed model is investigated using 3-D FEA.

Webex Meeting Number: 133 080 1509Webex Meeting Password: u3KrpZGDW73

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Advancing speech activity detection for automatic speech assessment of pre-school children prompted speech

Satwik DuttaNovember 5, 2020 10:00 AM – 11:00 AM

Abstract:

PhD Advisor: Dr. John H.L. Hansen

Speech sound disorder (SSD), a developmental disorder which affects children’s ability to produce the sounds (and words) within their native language, has a prevalence rate of 3-16% among children in USA. Screening for SSDs generally requires recording, evaluation, and decision-making by a certified speech-language pathologist (SLP). Automating part or all of this process could significantly reduce the amount of time and effort in the screening process. However, in order for this process and especially the final ‘pass’/‘fail’ screening decision to be automated, children’s speech content must be extracted from within a collected audio sample and therefore requires speech/silence activity detection. For this study, an iOS application for field use was developed to collect speech word productions from children, with algorithmic processing of all participants assigned a Percentage of Consonants Correct-Revised (PCC-R) score by a certified SLP. An unsupervised speech-activity-detection (SAD) algorithm is explored. COMBO-SAD, originally developed during the DARPA-RATS program, was modified to for use on child speech. Model evaluation was performed on a diverse collected child corpus based on their PCC-R score. Finally, a duration “shoulder” extension of SAD boundary labels was also analyzed to benchmark potential system impact on model performance.

Webex Meeting Number: 145 409 3767Webex Meeting Password: 9pnRpMSJg33

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Reservoir Computing with Frustrated NanomagnetsAlexander James Edwards

October 21, 2020 1:00 PM

Abstract:

PhD Advisor: Dr. Joseph S. Friedman

Reservoir computing is an emerging methodology for neuromorphic computing that is especially well-suited for hardware implementations in size, weight, and power (SWaP) constrained environments. We have proposed a novel implementation for the reservoir layer comprising a planar arrangement of frustrated nanomagnets. We simulated our nanomagnet reservoir computer (NMRC) design on benchmark tasks, demonstrating NMRC’s high memory content and expressibility. In support of the feasibility of this method, a frustrated nanomagnet reservoir layer was fabricated, the first step in realizing a full (NMRC) system. Using this structure, we describe a low-power, low-area system with an area-energy-delay product ten orders of magnitude lower than classical RC systems, that is therefore promising for SWaP-constrained applications.

Webex Meeting Number: 145 112 4384 Webex Meeting Password: V7RvuYEyx69

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Reliability And Condition Monitoring Of SiC Power MOSFETs

Masoud FarhadiOctober 19, 2020 2:00 PM – 3:00 PM

Abstract:

PhD Advisor: Dr. Bilal Akin

SiC MOSFETs is the key technology for modern power electronics converters with higher voltage ratings, higher maximum operating temperatures, and higher thermal conductivity. Although SiC devices provide a solution to overcome the physical limitations of Si, their market adoption remains limited. Reliability of SiCdevices is one of the main barriers preventing their high penetration into the market.Therefore, it is essential to investigate progressive degradation and parameter shifts in SiC devices to develop condition monitoring tools which can recognize failure precursors at the earliest stage and increase the system reliability. This presentation is discussing new methods for gate oxide degradation. Also, a comprehensive reliability analysis test setup for aging power modules will be fabricated. Therefore, more realistic results will be revealed based on AC power cycling test.

Webex Meeting Number: 133 471 6660 Webex Meeting Password: s93USCjh3hY

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Design and demonstration of antenna-coupled Schottky diodes in a foundry complementary metal-oxide semiconductor (CMOS) technology for electronic detection of far-infrared radiation

Muhammad Musab FarooqNovember 09, 2020 1:00 PM

Abstract:

PhD Advisor: Dr. Kenneth O

For the first time, Electronic detection of far-Infrared (FIR) radiation is reported at frequencies of 4.92 THz and 9.74 THz respectively, using Schottky-barrier diodes (SBDs) fabricated in 130-nm metal-oxide-semiconductor (CMOS) technology without any process modification. A significant improvement in measured peak responsivity (Rv) of detectors (383 and 25 V/W at 4.92 and 9.74 THz, respectively) compared to existing MOSFET and SBD detectors is observed. This improvement in Rv will ensure a negligible impact on the system noise-equivalent power (NEP) due to the input-referred noise of the amplifier following the detector. A good agreement between the simulation and measurement results is achieved by incorporating the effects of plasma resonance, transit time, and FIR absorption behavior of SiO2 in the device model in addition to performing the 3D electromagnetic simulations. The detector designed for a 10 THz operation achieves an optical Noise Equivalent Power (NEP) of 1.1 nW/√Hz at 9.74 THz in the shot-noise limit, which is comparable to that of commercially available Pyrodetectors that are 50 000× larger. Using a SBD fabricated in CMOS will lead to low-cost millimeter wave and sub-millimeter wave imagers.

Webex Meeting Number: 133 606 2903 Webex Meeting Password: QJidivpk922

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Digitally Modulated CMOS Polar Transmitters for Highly-Efficient mm-Wave Wireless Communication

Haidong GuoNovember 11, 2020 9:00AM - 10:00AM

Abstract:

PhD Advisor: Dr. Kenneth O

A polar transmitter (TX) is implemented at 60 GHz, enabling a power amplifier (PA) to operate in saturation where efficiency is highest, even when handling higher order modulations such as QPSK and 16-QAM. The phase path is upconverted by I-Q mixers, while the amplitude path modulates an RF-DAC. Aimed at 802.11ad applications, the 10 GS/s (i.e., 6x-oversampled) polar TX realizes more than 30 dB alias attenuation, and the input bandwidth exceeds 3.1 GHz. The PA saturated output power is 10.8 dBm with 29.8% drain efficiency at the maximum RF-DAC code. Average output power is 8.1 dBm with 22.3% drain efficiency at −20.7 dB EVM for QPSK modulation without RF-DAC predistortion. The corresponding 16-QAM values are: 7.2 dBm average output power with 19.8% efficiency at −16.5 dB EVM.With predistortion, a QPSK modulated output achieves 5.3 dBm average power with 15.3% efficiency at −23.6 dB EVM, while 3.6 dBm average power with 11.6% efficiency at −18.1 dB EVM is realized for 16-QAM. For a sampling rate of 10 GS/s, the TX data rates are 3.33 Gb/and 6.67 Gb/s for QPSK and 16-QAM, respectively. Implemented in 40 nm bulk-CMOS, the core circuit occupies 0.18 mm2 core of the 2.38 mm2 total die area, and consumes 40.2mW from a 0.9 V supply.

Webex Meeting Number: 145 888 8831 Webex Meeting Password: 12345

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Direction of arrival estimation with co-prime array Pinky Kapoor

October 29, 2020 10:30 AM

Abstract:

PhD Advisor: Dr. Aria Nosratinia

Coprime arrays enjoy increased degrees of freedom (the number of directions of arrival that can be resolved) given the number of array elements. To overcome the grid mismatch problem of traditional sparse recovery techniques in the context of co-prime arrays, a recovery algorithm based on super-resolution is discussed in this presentation. Super-resolution considers a continuous range of possible sources, thus mitigating the off-grid effects in traditional sparse recovery. Comparisons with MUSIC with spatial smoothing and discrete sparse recovery will be presented. The second half of this talk addresses calibration issues in co-prime arrays. A virtual array interpolation algorithm using maximum correntropy criterion (MCC) is discussed. In this approach, the interpolated virtual array covariance matrix is reconstructed via nuclear norm minimization (NNM).

Webex Meeting Number: 133 859 3776Webex Meeting Password: Am3krbEmM69

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Arbitrary Microphone Array Optimization Method Based on TDOA for Specific Localization Scenarios

Anton KovalyovNovember 02, 2020 2:00 PM

Abstract:

PhD Advisor: Dr. Issa Panahi

Various microphone array geometries (e.g., linear, circular, square, cubic, spherical, etc.) have been used to improve the positioning accuracy of sound source localization. However, whether these array structures are optimal for various specific localization scenarios is still a subject of debate. This presentation addresses a microphone array optimization method for sound source localization based on TDOA (time difference of arrival). The geometric structure of the microphone array is established in parametric form. A triangulation method with TDOA is used to build the spatial sound source location model, which consists of a group of nonlinear multivariate equations. Through reasonable transformation, the nonlinear multivariate equations can be converted to a group of linear equations that can be approximately solved by the weighted least square method. Then, an optimization model based on particle swarm optimization (PSO) algorithm is constructed to optimize the geometric parameters of the microphone array under different localization scenarios combined with the spatial sound source localization model. In the optimization model, a reasonable fitness evaluation function is established which can comprehensively consider the positioning accuracy and robustness of the microphone array. In order to verify the array optimization method, two specific localization scenarios and two array optimization strategies for each localization scenario are constructed. The optimal array structure parameters are obtained through numerical iteration simulation. The localization performance of the optimal array structures obtained by the method described in this presentation is compared with the optimal structures proposed in the literature as well as with random array structures. The simulation results show that the optimized array structure gives better positioning accuracy and robustness under both specific localization scenarios. The proposed optimization model could solve the problem of array geometric structure design based on TDOA and could achieve the customization of microphone array structures under different specific localization scenarios.

Webex Meeting Number: 133 973 1220Webex Meeting Password: PpATrk3dP45

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A survey on hand gesture recognition for Mixed reality applicationsHiranya Garbha Kumar

November 04, 2020 11:00 AM

Abstract:

PhD Advisor: Dr. B. Prabhakaran

Hand gestures are one of the primary modes of interface between a user and a mixed reality system. As such, accurate and robust hand gesture recognition systems are essential and have a wide range of real-world applications. With 3D hand pose estimation algorithms becoming extremely accurate and robust, there is now a lot more focus on solving the challenge of hand gestures estimation. In this presentation, we go through the recent advances made in the field of hand gesture recognition, my previous work related to hand pose estimation, and the need for (and lack of) research on feet pose estimation in the context of Virtual/Augumented/Mixed reality systems.

Webex Meeting Number: 133 676 2777 Webex Meeting Password: Apd57MmR7Br

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Towards Functional Safety of Deep Learning Hardware AcceleratorsShamik Kundu

October 15, 2020 9:00 AM – 10:00 AM

Abstract:

PhD Advisor: Dr.

High accuracy and ever increasing computing power have made Deep Neural Networks (DNNs) the algorithm of choice for various machine learning, computer vision and image processing applications across the computing spectrum. To this end, Google developed Tensor Processing Unit (TPU) to accelerate the computationally intensive matrix multiplication operation of a DNN on its systolic array architecture. Faults manifested in the datapath of such a systolic array due to latent manufacturing defects or single event effects may lead to Functional Safety (FuSa) violation. Although DNNs are known to resist minor perturbations with their inherent fault tolerant characteristics, we show that the classification accuracy of the model plummets from 97.4% to 7.75% with a minimal fault rate of 0.0003% in the accelerator, implying catastrophic circumstances when deployed across mission-critical systems. Hence, to ensure FuSa of such accelerators, this paper provides an extensive FuSa assessment of the accelerator exposed to faults in the datapath, by varying the network parameters, position and characteristics of the induced error across multiple exhaustive datasets. Furthermore, we propose two novel strategies to obtain a diminutive set of functional test patterns to detect FuSa violation in a DNN accelerator. Our experimental results demonstrate that the obtained test sets can achieve up to 100% fault coverage with cardinality as low as 0.1% of the entire test dataset.

Kanad Basu

Webex Meeting Number: 145 075 9653Webex Meeting Password: P53Jbfpycc8

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Defending Hardware-based Malware Detectors against Adversarial Attacks

Abraham Peedikayil KuruvilaOctober 15, 2020 8:00 AM – 9:00 AM

Abstract:

PhD Advisor: Dr. Kanad Basu

In the era of Internet of Things (IoT), Malware has been proliferating exponentially over the past decade. Traditional anti-virus software are ineffective against modern complex Malware. In order to address this challenge, researchers have proposed Hardware-assisted Malware Detection (HMD) using Hardware Performance Counters (HPCs). The HPCs are used to train a set of Machine learning (ML) classifiers, which in turn, are used to distinguish benign programs from Malware. Recently, adversarial attacks have been designed by introducing perturbations in the HPC traces using an adversarial sample predictor to misclassify a program forspecific HPCs. These attacks are designed with the basic assumption that the attacker is aware of the HPCs being used to detectMalware. Since modern processors consist of hundreds of HPCs, restricting to only a few of them for Malware detection aids the attacker. In this paper, we propose a Moving target defense (MTD) for this adversarial attack by designing multiple ML classifiers trained on different sets of HPCs. The MTD randomly selects a classifier; thus, confusing the attacker about the HPCs or the number of classifiers applied. We have developed an analytical model which proves that the probability of an attacker to guess the perfect HPC-classifier combination for MTD is extremely low (in the range of 10^−1864 for a system with 20 HPCs). Our experimental results prove that the proposed defense is able to improve the classification accuracy of HPC traces that have been modified through anadversarial sample generator by up to 31.5%, for a near perfect (99.4%) restoration of the original accuracy.

Webex Meeting Number: 145 237 8506Webex Meeting Password: VhkMHjBh682

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High Response Speed of Imprinted Organometal Halide Perovskite Photodetectors

Dayang LinNovember 09, 2020 10:00 AM

Abstract:

PhD Advisor: Dr.

Solution-processed organic-inorganic metal halide perovskites have attracted tremendous attention in thephotodetector (PD) community in recent years due to their excellent optoelectronic properties and facile fabrication.Meanwhile, the metal-semiconductor-metal (MSM) structure is widely used in PD designs due to their fabricationsimplicity, low dark current, and compatibility with the field-effect transistor technology. Currently, the mainchallenge in MSM perovskite PDs is to simultaneously achieve high responsivity and fast speed. In this work, weovercome this challenge by employing nanoimprint lithography (NIL) on MSM perovskite PDs. As NIL not onlydirectly patterns the perovskite thin film, but also improves perovskite morphology and crystallinity, enhanced PDperformance can be expected. Furthermore, interdigitated ITO electrodes are applied to increase the photocurrentand on/off ratio, as well as to decrease carrier transient time without deteriorating perovskite. It is expected that thecombined strategies of NIL and interdigitated ITO electrodes will increase the responsivity and reduce the responsetime of perovskite PDs at the same time.

Qing Gu

Webex Meeting Number: 133 886 8355Webex Meeting Password: yF5m5FKWfB5

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Simulation, Fabrication, and Characterization of AFM cantileversHazhir Mahmoodi Nasrabadi

November 02, 2020 10:00 AM

Abstract:

PhD Advisor: Dr. S. O. Reza Moheimani

The atomic force microscope (AFM) is a mechanical microscope capable of producing three-dimensional images of a wide variety of sample surfaces with nanometer precision in air, vacuum, or liquid environments. The main concept in AFM is to use the force between the atoms of the tip of a Microcantilever and the atoms of sample surface for interpreting the surface profile of the sample. there are three major modes of AFM: Contact mode, Non-contact mode, tapping mode. In our research, we have designed and fabricated some different geometries of Microcantilevers with different resonance frequencies. Also we have designed readout circuits to decrease feedthrough effect and increase SNR in the output signal. This presentation will include the fabrication process, the techniques of on chip feedthrough cancellation, differential sensing, modal sensing and actuating, Q control, and designing Microcantilevers for Non-contact AFM, techniques to increase the SNR of the output signal of the readout circuits.

Webex Meeting Number: 133 009 5148Webex Meeting Password: JJqnDYmR832

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Concolic Testing on RTL for Detecting Security VulnerabilitiesXingyu Meng

October 15, 2020 10:00 AM – 11:00 AM

Abstract:

PhD Advisor: Dr. Kanad Basu

We presents RTL-ConTest, a Register Transfer Level (RTL)-level security vulnerability detection algorithm, that extracts critical process flows from a RTL design and executes RTL-level concolic testing to generate security test cases for identifying critical exploits manifested in a System-on-Chip (SoC). The efficiency of the proposed approach is evaluated on open source RISC-V-based SoCs. Our technique is successful in detecting the security vulnerabilities manifested in the processor core as well as in the rest of the SoC, e.g., debug modules, peripherals, etc., thereby providing a comprehensive vulnerability check on the entire hardware design. Since RTLConTest is implemented directly on the RTL of a SoC, it incurs substantially reduced latency and is more robust compared to existing techniques which translate the RTL to a high-level software representation. As demonstrated by our experimental results, in circumstances where conventional security verification tools are limited, RTL-ConTest furnishes significantly improved efficiency in detecting SoC security vulnerabilities.

Webex Meeting Number: 145 045 4175 Webex Meeting Password: BfA8XRCPJ37

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Observer based estimation of disturbances in topographic imaging by STM

Richa Mishra November 11, 2020 10:00 AM

Abstract:

PhD Advisor: Dr. S. O. Reza Moheimani

Scanning Tunneling Microscopy (STM) has potentially enabled and proven to be a powerful and unique tool for the determination of the structural and electronic properties of surfaces. Significant R&D over the years has enabled the commercialization of STM as a topographic imaging device and many related techniques have grown out of it such as Spectroscopy. The ability of resolving every single atom on solid surfaces is the most significant achievement of STM. STM has made it technically possible for scientists to probe directly the electronic structures of various materials at an atomicscale (z = 0.2 nm). Performance and preciseness of working of STM on atomic scale depends on the performance of its feedback control. While maintaining the tunneling current constant, the feedback control command maps the topography of the surface. However, this topography may not be accurate owing to the presence of disturbances in the form of slow surface variations and local density of states. The emphasis of this presentation will be on the literature survey in the context of conventional techniques of estimating these disturbances, and on the possibility of applying modern control techniques in modelling and estimating the disturbances. Finally, possible extensions or improvements to the existing technique of feedback control will also be discussed.

Webex Meeting Number: 133 024 6120Webex Meeting Password: bgScC9nmC28

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Gaussian noise model for estimation of non linear effects in a fiber based network: Applications and Limitations in a multi vendor agnostic Open Line System

Francois MooreOctober 12, 2020 3:30 PM

Abstract:

PhD Advisor: Dr. Andrea Fumagalli

The last few years have seen an increase in initiatives to open network infrastructure in order to remove the network's dependency on a single vendor. This is commonly referred to as removing "vendor lock-in". Several parallel initiatives, such as TIP and Open ROADM, are being implemented and commercialized with this goal in mind. In order to be successful, these initiatives much provide a vendor agnostic predictive model to estimate the optical reach of any DWDM wavelength. This presentation describes the use of a universal Gaussian Noise Model to estimate the fiber's non linear effects on the DWDM signal. It discusses its advantages and shortcomings, compares these calculated noise values against measured results and assesses the applicability of various computational simplifications against actual deployment scenarios.

Webex Meeting Number: 133 668 7574Webex Meeting Password: Gaussian

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Towards High Speed and Small Footprint Nano-LEDsBayron Lennin Murillo Borjas

October 14, 2020 10:30 AM

Abstract:

PhD Advisor: Dr. Qing Gu

Light emitting devices are featured in households, cars, traffic lights, cell phones, and many scientific laboratories. As the case of electronic devices such a transistor, there has been great effort in the miniaturization of light emitting devices to improved power consumption and modulation speed. Miniaturization of light emitting devices is key to replace or work in conjunction with current electronics. Since the challenge is to stay competitive with current transistor technology, light emitting devices need to reach nanometer size scale and high integration density. To this end, metal nano-cavities provide a path into below diffraction limited devices.

Webex Meeting Number: 133 907 0898Webex Meeting Password: SbGwmUwU755

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A Fully Integrated Transformer-Coupled Power Detector With 5 GHz RF PA for WLAN 802.11ac in 40 nm CMOS

Goutham Kumarasamy MurugesanNovember 10, 2020 2:00 PM-3:00 PM

Webex Meeting Number: 133 966 7442 Webex Meeting Password: 7XRkJ3TxNY9

PhD Advisor: Dr. Kenneth O

This presentation talks about a fully integrated power detector that continually monitors RF voltage and RF current to detect the RF output power of a 5GHz on-chip power amplifier in 40nm CMOS technology. The RF current is detected by a sense winding in the output transformer, and the RF voltage through capacitive division of the RF output voltage. With this information, the power detector accurately and continuously determines the real output power of the RF PA with low inaccuracy of ±0.5dB over 32.5dB dynamic range. The power detector performs RF output power measurement even for an antenna impedance mismatch up to voltage standing wave ratio of 2.8:1 with an accuracy of ±1dB. Also, the power detector is incorporated inside the RF PA output transformer resulting in zero area overhead.

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Literature Survey of Contact and Noncontact Signal/Image Processing Approaches for Physiological Measurements

Aoxin NiNovember 17, 2020 10:00 AM - 11:00 AM

PhD Advisor: Dr. Nasser Kehtarnavaz

The interest in self physiological measurements in general and in non-contact or remote physiological measurements in particular has been steadily growing in healthcare and sports applications. This presentation covers a literature review of contact methods as well as non-contact or remote methods for physiological measurements. Contact methods primarily utilize a light source and a photodetector and involve signal processing operations and non-contact methods primarily utilize a video camera and involve image processing operations. The emphasis in this presentation will be placed on deep learning approaches as well as on the fusion of different sensing modalities for physiological measurements. A comparison of representative methods in terms of their approaches, pros, and cons will be provided.

Webex Meeting Number: 145 286 1245 Webex Meeting Password: BEwkGKKh233

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Comparative Study of Electrical Biosensing Technologies

Hamed NikfarjamNovember 17, 2020 11:00 AM

PhD Advisor: Dr. Siavash Pourkamali

The use of biosensors for medical technologies has increased exponentially. Biosensors can detect specific biological analytes and monitor their functions. Despite the tremendous improvements in biosensor technologies, there remain challenges to overcome as medical goals entails non-invasive, small-sized, portable, and cost-effective sensors. Many researchers worldwide are working to devise improved, highly sensitive, and rapid-response biosensors for medical applications. Biosensing can play a role through multiple aspects including bio-manufacturing product release criteria, organ-on-a-chip technologies, and indicators of therapeutic efficacy. Noninvasive, cost-effective, high-resolution, and portable biosensors may be utilized for in monitoring of organ functionality in high-risk patients. Therefore, we review the concept of biosensing as well as biosensor mechanisms and characteristics. The applications of biosensors in various fields such as cancer diagnosis, cardiovascular disease, and wound healing are discussed. Furthermore, we review the important role of biosensors and their applications in manufacturing. We, also, compare these different techniques of biosensing and review their pros and cons.

Webex Meeting Number: 133 676 0757Webex Meeting Password: n2pM9wdJef5

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Low-latency and high-throughput software turbo decoders on multi-core architectures

Shunmugapriya RamanathanNovember 02, 2020 11:00 AM

PhD Advisor: Dr. Andrea Fumagalli

In the last few years, with the advent of a software-defined radio (SDR), the processor cores were stated to be an efficient solution to execute the physical layer components. Indeed, multi-core architectures provide both high-processing performance and flexibility, such that they are used in current base station systems instead of dedicated FPGA or ASIC devices. Currently, an extension of the SDR concept is running. Indeed, cloud platforms become attractive for the virtualization of radio access network functions. Actually, they improve the efficiency of the computational resource usage,and thus the global power efficiency. However, the implementation of a physical layer on a Cloud-RAN platform as discussed by Wubben and Paul (2016); Checko et al. (JAMA 17(1):405–426, 2015); Inc (2015); and Wubben et al. (JAMA 31(6):35–44, 2014) or FlexRAN platform as discussed by Wilson (2018); Foukas et al. (2017); Corp. (2017); Foukas et al. (2016) is a challenging task according to the drastic latency and throughput constraints as discussed by Yu et al. (2017) and Parvez (2018). Processing latencies from 10 μs up to hundred of μs are required for future digital communication systems. In this context, most of works about software implementations of ECC applications is based on massive frame parallelism to reach high throughput. Nonetheless, they produce unacceptable decoding latencies. In this paper, a new turbo decoder parallelization approach is proposed for x86 multi-core processors. It provides both: high-throughput and low-latency performances. In comparison with all CPU- and GPU-related works, the following results are observed: shorter processing latency, higher throughput, and lower energy consumption. Regarding to the best state-of-the-art x86 software implementations, 1.5× to 2×throughput improvements are reached, whereas a latency reduction of 50× and an energy reduction of 2× are observed.

Webex Meeting Number: 133 357 7706Webex Meeting Password: W3mJMb7sRe2

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Temporal Logics in Robotics and ControlSleiman Safaoui

October 30, 2020 3:30 PM

PhD Advisor: Dr. Tyler Summers

Spatial and temporal objectives are ubiquitous in our daily lives. From the moment we open our eyes, our brain is making spatio-temporal decisions: moving without bumping into things, adding coffee into the cup before drinking from that cup, driving safely to work by a specific time, ... etc. Our brain does an excellent job of planning and controlling our bodies to accomplish our daily tasks. For robots, this is a lot more complicated. As we continue to depend on and interact with robots and automated systems, the need forrobots with spatial and temporal planning and control capabilities becomes more prevalent. In this presentation, we discuss three main topics. We first present some of the basic temporal logics that serve as formal systems to represent and reason about propositions over time. In particular, we introduce linear, metric interval, and signal temporal logics (LTL, MITL, and STL respectively). Next, we outline three problem formulations encountered when using temporal logics for planning and control for robotic and autonomous systems: model checking and verification, monitoring, and synthesis. Then, we present solution methodologies and tools for these problems using automata, sampling approaches, and optimization tools. We wrap up the presentation with a brief exampleof how uncertainty could affect the planning and control problem, demonstrating the need for systematic risk-based solutions.

Webex Meeting Number: 126 674 4589Webex Meeting Password: 2aNPYPmPj47

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CMOS On-chip Phase-Noise Measurement Techniques

Sarfraz Habibullah Shariff November 10, 2020 3:00 PM - 4:00 PM

PhD Advisor: Dr. Kenneth O

Webex Meeting Number: 133 698 1000 Webex Meeting Password: huPqf7zVJ43

The push for higher data bandwidth has necessitated the need for high frequency communication systems. Since the carrier frequency is in the order of 10-100 GHz , Phase Noise of the system becomes a critical metric in the overall system performance. Conventional phase noise detection techniques implemented in spectrum analyzers make use of a spectrally clean reference clock signals and external calibration. However, these methods are not conducive to modern scaled CMOS processes. This presentation explores the methods used to implement on-chip Phase Detectors in modern CMOS process. Typical implementations include Delay Line Method , Vernier oscillator method, Correlation method.

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Self-Powered Analog/RF Hardware Trojan in a Standards Compliant Wireless NetworkYijie Tang

November 16, 2020 3:00 PM

PhD Advisor: Dr. Yiorgos Makris

My research work focuses on developing a self-powered hardware Trojan circuit that electromagnetically couples power from the inductor of a PA and rectifies it to produce a constant DC supply voltage for covert channel attacks. Hardware Trojans are stealthy circuits that are added into a targeted device by an adversary to perform some malicious activity, of which data exfiltration is one. Among the various research activities in literature, a self-powered hardware Trojan circuit hasn’t been investigated before and therefore the outcome of my research will serve as the cornerstone for several future works in this area. The intended work will be demonstrated in the analog/RF domain, specifically using the power amplifier of a 2.4GHz Wi-Fi network, and thereby the DC voltage produced by the Trojan circuit will be used by a covert channel to exfiltrate secretive information, while remaining stealthy and evading detection from existing defense solutions. The proposed work will be theoretically modeled in HFSS, post-layout simulated in cadence and fabricated using UMC65N technology. Thereby, we intend to evaluate the solution when it is integrated in an experimental setup consisting of a practical IEEE802.11a/g/n device and thereby demonstrate the effectiveness and inconspicuousness of the Trojan circuit.

Webex Meeting Number: 145 629 8522 Webex Meeting Password: 3MFfwPwpB45

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Cross-domain Adaptation with Discrepancy Minimization for Text-independent Forensic Speaker Verification

Zhenyu WangNovember 05, 2020 11:30 AM - 12:45 PM

PhD Advisor: Dr. John H.L. Hansen

Webex Meeting Number: 145 682 1825 Webex Meeting Password: tHFg3tvYJ39

Forensic audio analysis for speaker verification offers unique challenges due to location/scenario uncertainty and diversity mismatch between reference and naturalistic field recordings. The lack of real naturalistic forensic audio corpora with ground-truth speaker identity represents a major challenge in this field. It is also difficult to directly employ small-scale domain-specific data to train complex neural network architectures due to domain mismatch and loss in performance. Alternatively, cross- domain speaker verification for multiple acoustic environments is a challenging task which could advance research in audio forensics. In this study, we introduce a CRSS-Forensics audio dataset collected in multiple acoustic environments. We pre-train a CNN-based network using the VoxCeleb data, followed by an approach which fine-tunes part of the high-level network layers with clean speech from CRSS-Forensics. Based on this fine-tuned model, we align domain-specific distributions in the embedding space with the discrepancy loss and maxi- mum mean discrepancy (MMD). This maintains effective performance on the clean set, while simultaneously generalizes the model to other acoustic domains. From the results, we demonstrate that diverse acoustic environments affect the speaker verification performance, and that our proposed approach of cross-domain adaptation can significantly improve the results in this scenario.

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Transistor-level Programmable Fabric using the GF 12nm process

Sean Bang Li WengNovember 12, 2020 3: PM

PhD Advisor: Dr. Carl Sechen

Webex Meeting Number: 133 924 1850Webex Meeting Password: vPgjkr7Kx23

Hardware obfuscation is a critical technique for the security of IC designs. A field programmable gate array (FPGA) is one of the options for implementing obfuscation. However, the area overhead of an FPGA is far greater than an ASIC design for the same functionality. Therefore, we pursued TRAP (Transistor-level Programming) which has orders of magnitude less area overhead compared to an FPGA and is therefore highly suitable for hardware obfuscation. The architecture of a TRAP unit consists of three parts: memory cells for storing programming bits, programmable interconnect for directing input and output signals, and a transistor array for logic gate implementation. Programming bits are generated by design specification from the user. The programming bits stored in memory cells decide the switching of transistors in TRAP. Part of the programming bits are used for the programmable interconnect which will determine the connection between gates and I/Os. The programmable interconnect for one unit, which consists of four columns of transistors in the transistor array, has 264 programming bits. The transistor array allows the configuration of standard height cells which are similar to standard cells an ASIC design. The column is the fundamental unit of the transistor array and there are 6 transistors in each column used to construct logic gates, e.g. NAND2. There are 4 columns in one unit. For one unit, 82 programming bits are used to generate logic functions using the transistor array. A design with 234 TRAP units was implemented using the Global Foundries 12nm process. The achievement of the design can accommodate a circuit with up to 468 logic gates in an area of 87070.46 µm².