ece260b w05 placement

ECE260B CSE241A Placement.1 http:/ /vlsicad.ucsd.edu

ECE260B CSE241A ECE260B CSE241A Winter 2005Winter 2005

PlacementPlacement

Website: http:/ /vlsicad.ucsd.edu/courses/ece260b-Website: http:/ /vlsicad.ucsd.edu/courses/ece260b-w05w05

Slides courtesy of Prof. Andrew B. Slides courtesy of Prof. Andrew B. KahngKahng


VLSI Design Flow and Physical Design VLSI Design Flow and Physical Design StageStage

Definitions:Cell: a circuit component to be placed on the chip area. In placement, the functionality of the component is ignored.Net: specifying a subset of terminals, to connect several cells.Netlist: a set of nets which contains the connectivity information of the circuit.Global

Placement

Detail Placement

Clock Tree Synthesisand Routing

Global Routing

Detail Routing

Power/Ground Stripes, Rings Routing

Extraction and Delay Calc.

Timing Verification

IO Pad Placement


Placement ProblemPlacement Problem

Input:A set of cells and their complete information (a cell library).Connectivity information between cells (netlist information).

Output: A set of locations on the chip: one location for each cell.

Goal:The cells are placed to produce a routable chip that meets timing and other constraints (e.g., low-power, noise, etc.)

Challenge:The number of cells in a design is very large (> 1 million).The timing constraints are very tight.


A B C

Optimal Relative Order:Optimal Relative Order:


A B C

To spread ...To spread ...


A B C

.. or not to spread.. or not to spread


A B C

Place to the leftPlace to the left


A B C

or to the rightor to the right


A B C

Optimal Relative Order:Optimal Relative Order:

Without free space, the placement problem is dominated by Without free space, the placement problem is dominated by orderorder


Placement ProblemPlacement Problem

A bad placement A good placement


Global and Detailed PlacementGlobal and Detailed Placement

Global Placement

Detailed Placement

In global placement, we decide the approximate locations for cells by placing cells in global bins.

In detailed placement, we make some local adjustment to obtain the final non-overlapping placement.


Placement Footprints:

Standard Cell:

Data Path:

IP - Floorplanning


Core

ControlIO

Reserved areas

Mixed Data Path & sea of gates:



Perimeter IO

Area IO



Placement objectives are subject to user constraints / Placement objectives are subject to user constraints / design style:design style:

Hierarchical Design Constraints pin location power rail reserved layers

Flat Design with Floorplan Constraints Fixed Circuits I/O Connections


Standard CellsStandard Cells


Standard CellsStandard Cells

Power connected by abutment, placed in sea-of-rows Rarely rotated DRC clean in any combination Circuit clean (I.e. no naked T-gates, no huge input

capacitances) 8,9,10+ tracks in height Metal 1 only used (hopefully) Multi-height stdcells possible Buffers: sizes, intrinsic delay steps, optimal repeater selection Special clock buffers + gates (balanced P:N) Special metastability hardened flops Cap cells (metal1 used?) Gap fillers (metal1 used?) Tie-high, tie-low


UnconstrainedPlacement


Floor plannedPlacement


Placement Cube Placement Cube (4D)(4D)

Cost Function(s) to be used Cut, wirelength, congestion, crossing, ...

Algorithm(s) to be used FM, Quadratic, annealing, .

Granularity of the netlist Coarseness of the layout domain

2x2, 4x4, .

An effective methodology picks the right mix from the above and knows when to switch from one to next.

Most methods today are ad-hoc

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Advantages of HierarchyAdvantages of Hierarchy Design is carved into smaller pieces that can be worked on in parallel

(improved throughput) A known floor plan provides the logic design team with a large degree of

placement control. A known floor plan provided early knowledge of long wires Timing closure problems can be addressed by tools, logic design, and

hierarchy manipulation Late design changes can be done with minimal turmoil to the entire design


Disadvantages of HierarchyDisadvantages of Hierarchy

Results depend on the quality of the hierarchy. The logic hierarchy must be designed with Physical Design taken into account.

Additional methodology requirements must be met to enable hierarchy. Ex. Pin assignment, Macro abstract management, area budgeting, floor planning, timing budgets, etc

Late design changes may affect multiple components. Hierarchy allows divergent methodologies Hierarchy hinders Design Automation algorithms. They can no longer

perform global optimizations.


Traditional Placement AlgorithmsTraditional Placement Algorithms

Quadratic Placement Simulated Annealing Bi-Partitioning / Quadrisection Force Directed Placement Hybrid

Algo

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Cost Function

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Quadratic PlacementQuadratic Placement

Analytical Technique

x4x4

x3x3x1x1

x2x2

Min Min [(x1-x3)[(x1-x3)22 + (x1-x2) + (x1-x2)2 2 + (x2-x4)+ (x2-x4)22] : ] : FF

F/F/ x1 = 0; x1 = 0;

F/F/ x2 = 0;x2 = 0;Ax = BAx = B

2 -12 -1-1 2-1 2 x = x =

x1x1x2x2A = A = B = B =

x3x3x4x4


Analytical PlacementAnalytical Placement

Get a solution with lots of overlap What do we do with the overlap?


Pros and Cons of QPPros and Cons of QP

Pros:Very Fast Analytical SolutionCan Handle Large Design SizesCan be Used as an Initial Seed Placement Engine

Cons:Can Generate Overlapped Solutions: Postprocessing NeededNot Suitable for Timing Driven PlacementNot Suitable for Simultaneous Optimization of Other Aspects of Physical Design (clocks, crosstalk)Gives Trivial Solutions without Pads (and close to trivial with pads)


Simulated Annealing PlacementSimulated Annealing Placement

Initial Placement Improved throughInitial Placement Improved through

Swaps and MovesSwaps and Moves

Accept a Swap/ Move if it improves costAccept a Swap/ Move if it improves cost

Accept a Swap/ Move that degrades costAccept a Swap/ Move that degrades costunder some probability conditionsunder some probability conditions

TimeTime

CostCost


Pros and Cons of SA Pros and Cons of SA

Pros:Can Reach Globally Optimal Solution (given enough time)Open Cost Function.Can Optimize Simultaneously all Aspects of Physical DesignCan be Used for End Case Placement

Cons:Extremely Slow Process of Reaching a Good Solution


Bi-Partitioning/QuadrisectionBi-Partitioning/Quadrisection


Pros and Cons of Partitioning Based Pros and Cons of Partitioning Based PlacementPlacement

Pros:More Suitable to Timing Driven Placement since it is Move BasedNew Innovation (hMetis) in Partitioning Algorithms have made this Extremely FastOpen Cost FunctionMove Based means Simultaneous Optimization of all Design Aspects Possible

Cons:Not Well UnderstoodLots of indifferent movesMay not work well with some cost functions.


Hypergraphs in VLSI CADHypergraphs in VLSI CAD

Circuit netlist represented by hypergraph


Hypergraph Partitioning in VLSIHypergraph Partitioning in VLSI

Variants directed/undirected hypergraphs weighted/unweighted vertices, edges constraints, objectives,

Human-designed instances Benchmarks

up to 4,000,000 vertices

sparse (vertex degree 4, hyperedge size 4) small number of very large hyperedges

Efficiency, flexibility: KL-FM style preferred


Context: Top-Down VLSI PlacementContext: Top-Down VLSI Placement

etc


Context: Top-Down PlacementContext: Top-Down Placement

Speed 6,000 cells/minute to final detailed placement partitioning used only in top-down global placement implied partitioning runtime: 1 second for 25,000 cells, < 30

seconds for 750,000 cells Structure

tight balance constraint on total cell areas in partitions widely varying cell areas fixed terminals (pads, terminal propagation, etc.)


Fiduccia-Mattheyses (FM) ApproachFiduccia-Mattheyses (FM) Approach

Pass: start with all vertices free to move (unlocked) label each possible move with immediate change in cost that it causes

(gain) iteratively select and execute a move with highest gain, lock the moving

vertex (i.e., cannot move again during the pass), and update affected gains best solution seen during the pass is adopted as starting solution for next

pass FM:

start with some initial solution perform passes until a pass fails to improve solution quality


Cut During One Pass (Bipartitioning)Cut During One Pass (Bipartitioning)

Moves

Cut


Multilevel PartitioningMultilevel Partitioning

RefinementClustering


Force Directed PlacementForce Directed Placement

Cells are dragged by forces.Cells are dragged by forces.

Forces are generated by nets connecting Forces are generated by nets connecting cells. Longer nets generate bigger forces.cells. Longer nets generate bigger forces.

Placement is obtained by either a Placement is obtained by either a constructive or an iterative method.constructive or an iterative method.

i

jFij

i


Pros and Cons of Force Directed Pros and Cons of Force Directed PlacementPlacement

Pros:Very Fast Analytical SolutionCan Handle Large Design SizesCan be Used as an Initial Seed Placement EngineThe Force

Cons:Not sensitive to the non-overlapping constraintsGives Trivial Solutions without PadsNot Suitable for Timing Driven Placement


Hybrid PlacementHybrid Placement

Mix-matching different placement algorithmsEffective algorithms are always hybrid


GORDIAN (quadratic + partitioning)GORDIAN (quadratic + partitioning)

Partitionand Replace

InitialPlacement

min { x ix j 2}min { y i y j 2}


Congestion MinimizationCongestion Minimization

Traditional placement problem is to minimize interconnection length (wirelength)

A valid placement has to be routable Congestion is important because it represents

routability (lower congestion implies better routability)

There is not yet enough research work on the congestion minimization problem


Definition of CongestionDefinition of Congestion

Routing demand = 3Assume routing supply is 1,overflow = 3 - 1 = 2 on this edge.

Overflow = overflowall edges

Overflow on each edge = Routing Demand - Routing Supply (if Routing Demand > Routing Supply)0 (otherwise)


Correlation between Wirelength and Correlation between Wirelength and CongestionCongestion

Total Wirelength = Total Routing Demand


Wirelength Wirelength Congestion Congestion

A congestion minimized placement A wirelength minimized placement


Congestion Map of a Wirelength Minimized Congestion Map of a Wirelength Minimized PlacementPlacement

Congested Spots


CongestionMAP


Congestion Reduction Postprocessing Congestion Reduction Postprocessing

Reduce congestion globally by minimizing the traditional wirelength

Post process the wirelength optimized placement using the congestion objective


Among a variety of cost functions and methods for congestion minimization, wirelength alone followed by a post processing congestion minimization works the best and is one of the fastest.

Cost functions such as a hybrid length plus congestion do not work very well.

Congestion Reduction Postprocessing Congestion Reduction Postprocessing


Cost Functions for PlacementCost Functions for Placement

The final goal of placement is to achieve routability and meet timing constraints

Constraints are very hard to use in optimization, thus we use cost functions (e.g., Wirelength) to predict our goals.

We will show what happens when you try constraints directlyThe main challenge is a technical understanding of various cost functions and their interaction.


Prediction What is prediction ?

every system has some critical cost functions: Area, wirelength, congestion, timing etc.

Prediction aims at estimating values of these cost functions without having to go through the time-consuming process of full construction.

Allows quick space exploration, localizes the search For example:

statistical wire-load models Wirelength in placement


Paradigms of Prediction Two fundamental paradigms

statistical prediction #of two-terminal nets in all designs #of two-terminal nets with length greater than 10 in all designs

constructive prediction #of two-terminal nets with length greater than 10 in this design

and everything in between, e.g.,

#of critical two-terminal nets in a design based on statistical data and a quick inspection of the design in hand.

Absolute truth or I need it to make progress SLIP (System Level Interconnect Prediction)

community.



Net-cutLinear wirelengthQuadratic wirelengthCongestionTimingCouplingOther performance related

cost functionsUndiscovered: crossing

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Net-cut Cost for Global PlacementNet-cut Cost for Global Placement

The net-cut cost is defined as the The net-cut cost is defined as the number of external nets between different number of external nets between different global binsglobal bins

Minimizing net-cut in global placement Minimizing net-cut in global placement tends to put highly connected cells close tends to put highly connected cells close to each other.to each other.


Linear Wirelength Cost Linear Wirelength Cost

The linear length of a net between cell 1 and The linear length of a net between cell 1 and cell 2 iscell 2 is

ll1212 = = |x1-x2| + |y1-y2||x1-x2| + |y1-y2|

The linear wirelength cost is the summation of The linear wirelength cost is the summation of the linear length of all nets. the linear length of all nets.

(x1,y1)(x1,y1)

(x2,y2)(x2,y2)

11

22


Quadratic Wirelength Cost Quadratic Wirelength Cost

The quadratic length of a net between cell 1 The quadratic length of a net between cell 1 and cell 2 isand cell 2 is

ll1212 = = (x1-x2)(x1-x2)22 + (y1-y2) + (y1-y2)22

The quadratic wirelength cost is the The quadratic wirelength cost is the summation of the quadratic length of all nets. summation of the quadratic length of all nets.

(x1,y1)(x1,y1)

(x2,y2)(x2,y2)

11

22


Congestion Cost Congestion Cost

Routing demand = 3Assume routing supply is 1,overflow = 3 - 1 = 2 on this edge.

Congestion Overflow = overflowall edges

Overflow on each edge =

Routing Demand - Routing Supply (if Routing Demand > Routing Supply)0 (otherwise)



Various cost functions (and a mix of them) have been used in practice to model/estimate routability and timing

We have a good feel for what each cost function is capable of doing

We need to understand the interaction among cost functions


Congestion Minimization Congestion Minimization and Congestion vs and Congestion vs WirelengthWirelength

Congestion is important because it closely represents routability (especially at lower-levels of granularity) Congestion is not well understoodAd-hoc techniques have been kind-of working since congestion has never been severeIt has been observed that length minimization tends to reduce congestion.Goal: Reduce congestion in placement (willing to sacrifice wirelength a little bit).


Correlation between Wirelength and Correlation between Wirelength and CongestionCongestion

Total Wirelength = Total Routing Demand


WirelengthWirelength

Congestion Congestion

A congestion minimized placement

A wirelength minimized placement


Congestion Map of a Wirelength Minimized Congestion Map of a Wirelength Minimized PlacementPlacement

Congested Spots


Different Routing Models for modeling Different Routing Models for modeling congestioncongestion Bounding box router: fast but inaccurate. Real router: accurate but slow. A bounding box router can be used in placement

if it produces correlated routing results with the real router.

Note: For different cost functions, answer might be different (e.g., for coupling, only a detailed router can answer).


Different Routing ModelsDifferent Routing Models

A bounding box routing model A MST+shortest_path routing model


Objective Functions Used in Congestion Objective Functions Used in Congestion MinimizationMinimization

WL: Standard total wirelength objective. Ovrflw: Total overflow in a placement (a direct

congestion cost). Hybrid: (1- )WL + Ovrflw QL: A quadratic plus linear objective. LQ: A linear plus quadratic objective. LkAhd: A modified overflow cost. (1- T)WL + T Ovrflw: A time changing hybrid objective

which let the cost function gradually change from wirelength to overflow as optimization proceeds.


Post Processing to Reduce CongestionPost Processing to Reduce Congestion

Reduce congestion globally by minimizing the traditional wirelength

Post process the wirelength optimized placement using the congestion objective


Post Processing HeuristicsPost Processing Heuristics

Greedy cell-centric algorithm: Greedily move cells around and greedily accept moves.

Flow-based cell-centric algorithm: Use a flow-based approach to move cells.

Net-centric algorithm: Move nets with bigger contributions to the congestion first.


Greedy Cell-centric HeuristicGreedy Cell-centric Heuristic


Flow-based Cell-centric HeuristicFlow-based Cell-centric Heuristic

Cell NodesBin Nodes


Net-centric HeuristicNet-centric Heuristic

2 1

2

2 2

1

1


From Global Placement to Detailed From Global Placement to Detailed PlacementPlacement

Global Placement: Assuming all the cells are placed at the centers of global bins.

Detailed Placement: Cells are placed without overlapping.


Correlation Between Global and Detailed Correlation Between Global and Detailed PlacementPlacement

WLg: Wirelength optimized global placement.

CONg: Wirelength optimized detailed placement.

WLd: Congestion optimized global placement.

CONd: Congestion optimized detailed placement.

Conclusion: Congestion at detailed placement level is correlated with congestion at global placement level. Thus reducing congestion in global placement helps reduce congestion in final detailed placement.


CongestionCongestion

Wirelength minimization can minimize congestion globally. A post processing congestion minimization following wirelength minimization works the best to reduce congestion in placement.

A number of congestion-related cost functions were tested, including a hybrid length plus congestion (commonly believed to be very effective). Experiments prove that they do not work very well.

Net-centric post processing techniques are very effective to minimize congestion.

Congestion at the global placement level, correlates well with congestion of detailed placement.


Shapes of Cost FunctionsShapes of Cost Functions

Solution Space

net-cut cost

wirelength

congestion


Relationships Between the Three Cost Functions:Relationships Between the Three Cost Functions:

The net-cut objective function is more smooth than the wirelength objective functionThe wirelength objective function is more smooth than the congestion objective functionLocal minimas of these three objectives are in the same neighborhood.


Crossing: A routability estimator?Crossing: A routability estimator?

Replace each crossing with a gate A planar netlist Easy to place


Timing CostTiming CostDelay of the circuit is defined as the longest delay among all possible paths from primary inputs to primary outputs.Interconnection delay becomes more and more important in deep sub-micron regime.

Critical Path


Timing Analysis Timing Analysis

5 5 5

4 4 4

2

LATCH

LATCH

3 2 1 1

2 1 3 2

1

2222

1919

How do we get the delay numbers on the gate/ interconnect?How do we get the delay numbers on the gate/ interconnect?


ApproachesApproaches

Budgeting In accurate information Fast

Path Analysis Most accurate information Very slow

Path analysis with infrequent path substitution Somewhere in between


Timing MetricsTiming Metrics

How do we assess the change in a delay due to a potential move during physical design?Whether it is channel routing or area routing, the problem is the same

translate geometrical change into delay change


Others costs: Coupling CostOthers costs: Coupling CostHard to model during placementCan run a global router in the middle of placementEven at the global routing level it is hard to model it

Avoid it


Spacing

Extra space

Segregation

Noisy region

Quiet regionShielding

Grounded Shields

Coupling SolutionsCoupling Solutions

Once we have some metrics for coupling, we can calculate sensitivities, and optimize the physical design...


Other Performance CostsOther Performance Costs

Power usage of the chip.Weighted netsDual voltages (severe constraint on placement)

Very little known about these cost functions and their interaction with other cost functions

Fundamental research is needed to shed some light on the structure of them


Netlist Granularity: Netlist Granularity: Problem Size and Solution Space SizeProblem Size and Solution Space Size

The most challenging part of the placement problem is to solve a huge system within given amount of timeWe need to effectively reduce the size of the solution space and/or reduce the problem size

Netlist clustering: Edge extraction in the netlist

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Layout CoarseningLayout Coarsening

Reduce Solution Space Edge extraction in the solution space Only simple things have been tried

GP, DP (Twolf) 2x1, 2x2, .

Coarsen only easy parts

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Incremental PlacementIncremental Placement

Given an optimal placement for a given netlist, how to construct optimal placements for netlists modified from the given netlist.Very little research in this area.

Different type of incremental changes (in one region, or all over)Methods to useHow global should the method be

An extremely important problem.


A placement move changes the interconnect capacitance and resistance of the associated netA net topology approximation is required to estimate these changes

Incremental PlacementIncremental Placement


Placynthesis Algorithms Placynthesis Algorithms

resizing buffering

cloningrestructuring


Many other Design Metrics:Many other Design Metrics:Power Supply and Total PowerPower Supply and Total Power

0

0.5

1

1.5

2

2.5

1997 1999 2002 2005 2008 2011

VddVt

Source: The Incredible Shrinking Transistor, Yuan Taur, T. J. Watson Research Center, IBM, IEEE Spectrum, July 1999

0

1

2

3

4

5

6

7

1997 1999 2002 2005 2011

power


HL

H L

feedthrough VHVL GND

H -- High Voltage Block L -- Low Voltage Block

Layout Structure

VH

VL

Cell Library withDual Power Rails

GND

IN OUT

Dual Voltages: A harder problemDual Voltages: A harder problem

Layout synthesis with dual voltages: major geometric constraints


Placement ReferencesPlacement References C. J. Alpert, T. Chan, D. J.-H. Huang, I. Markov, and K. Yan, Quadratic Placement

Revisited,Proc. 34th IEEE/ACM Design Automation Conference, 1997, pp. 752-757 C. J. Alpert, J.-H Huang, and A. B. Kahng, Multilevel Circuit Partitioning, Proc. 34th

IEEE/ACM Design Automation Conference, 1997, pp. 530-533 U. Brenner, and A. Rohe, An Effective Congestion Driven Placement Framework,

International Symposium on Physical Design 2002, pp. 6-11 A. E. Caldwell, A. B. Kahng, and I.L. Markov, Can Recursive Bisection Alone Produce

Routable Placements,Proc. 37th IEEE/ACM Design Automation Conference, 2000, pp 477-482

M.A. Breuer, Min-Cut Placement, J. Design Automation and Fault Tolerant Computing, I(4), 1997, pp 343-362

J. Vygen, Algorithms for Large-Scale Flat Placement, Proc. 34th IEEE/ACM Design Automation Conference, 1988,pp 746-751

H. Eisenmann and F. M. Johannes, Generic Global Placement and Floorplanning, Proc. 35th IEEE/ACM Design Automation Conference, 1998, pp. 269-274

S.-L. Ou and M. Pedram, Timing Driven Placement Based on Partitioning with Dynamic Cut-Net Control, Proc. 37th IEEE/ACM Design Automation Conference, 2000, pp. 472-476

C.M. Fiduccia and R.M. Mattheyses, A linear time heuristic for improving network partitions, Proc. ACM/IEEE Design Automation Conference. (1982) pp. 175 - 181.

ece260b w05 placement

Documents

leftece260b cse241a

rightece260b cse241a

set of cells

user constraints design

timing constraints

edua b coptimal relative

edua b cplace

edua b cto