ECEN 4633/5633 ECEN 4633/5633 Hybrid Embedded SystemsHybrid Embedded Systems

Fall 2010 SemesterFall 2010 SemesterDr. David WardDr. David WardDr. David WardDr. David Ward

Today’s AgendaToday’s AgendaToday s AgendaToday s Agenda

Background/ExperienceBackground/ExperienceCourse InformationCourse InformationAl DE2 B d O iAl DE2 B d O iAltera DE2 Board OverviewAltera DE2 Board OverviewIntroduction to Embedded SystemsIntroduction to Embedded SystemsDesign AbstractionDesign AbstractionDesign AbstractionDesign AbstractionMicroprocessors in Embedded SystemsMicroprocessors in Embedded SystemsAvalon Switch FabricAvalon Switch Fabrica o S tc ab ca o S tc ab cAssignmentsAssignmentsQuestionsQuestions

Course InfoCourse InfoCourse InfoCourse InfoTime:Time: Tuesday 5:30 p.m. Tuesday 5:30 p.m. –– 9:10 p.m. including lab time9:10 p.m. including lab timey py p p gp gLocation:Location: ECEE ECEE 1B28 1B28 (lectures), Lab room 287 (lab)(lectures), Lab room 287 (lab)Prerequisites:Prerequisites: ECEN 3100 (Digital Logic) and highECEN 3100 (Digital Logic) and high--level level Programming (C/C++)Programming (C/C++)Programming (C/C++)Programming (C/C++)Instructor:Instructor: David Ward, Office Hours: Tuesday 4:30David Ward, Office Hours: Tuesday 4:30--5:30 5:30 & 9:10& 9:10--10:10 PM, ECEE 12010:10 PM, ECEE 120Text:Text: ZainalabedinZainalabedin NavabiNavabi: ": " Embedded Core Design Embedded Core Design with FPGAswith FPGAs" McGraw" McGraw--Hill Electronic Engineering, 2007.Hill Electronic Engineering, 2007.Course web page:Course web page: http://ecee.colorado.edu/~ecen5633/http://ecee.colorado.edu/~ecen5633/Course web page:Course web page: http://ecee.colorado.edu/ ecen5633/http://ecee.colorado.edu/ ecen5633/Graduate TA:Graduate TA: MayureshMayuresh VarerkarVarerkar, Office Hours: , Office Hours: Thursday 5:30Thursday 5:30--8:00 PM, Lab room 2878:00 PM, Lab room 287

Course InfoCourse InfoCourse InfoCourse InfoGrading:Grading: (20%) HWs; (55%) Lab Exercises; (25%) Project presentation (20%) HWs; (55%) Lab Exercises; (25%) Project presentation ––During Final exam periodDuring Final exam periodDuring Final exam periodDuring Final exam period

The course is taught using the new The course is taught using the new Altera DE2 FPGA boardsAltera DE2 FPGA boardsNIOS 2, a 32 bit microcontroller from AlteraNIOS 2, a 32 bit microcontroller from AlteraAl CAD l Q 2 SOPC Ni 2 IDE (I dAl CAD l Q 2 SOPC Ni 2 IDE (I dAltera CAD tools: Quartus 2 , SOPC, Nios 2 IDE (Integrated Altera CAD tools: Quartus 2 , SOPC, Nios 2 IDE (Integrated Development Environment).Development Environment).

HWs:HWs: Due every 2 weeks Due every 2 weeks yyFour assignments totalFour assignments totalNo late assignmentsNo late assignmentsGenerally done in groups of twoGenerally done in groups of twoHW assignments and Labs will “overlap”HW assignments and Labs will “overlap”You must have You must have workingworking program for full creditprogram for full credit

Lab exercises:Lab exercises: Due every weekDue every weekTotal six lab exercisesTotal six lab exercises

Course InfoCourse InfoCourse Info Course Info Project:Project:jj

A group project is required (avg. group four persons)A group project is required (avg. group four persons)Detailed requirements are needed for presentation to the Detailed requirements are needed for presentation to the instructor.instructor.C l t l i ill th b f d t id tif thC l t l i ill th b f d t id tif thComplex system analysis will then be performed to identify the Complex system analysis will then be performed to identify the overall description and components necessary for overall description and components necessary for implementation.implementation.At the end of the semester during the final examination period, a At the end of the semester during the final examination period, a g p ,g p ,two minute two minute YouTubeYouTube video demonstration is required along with video demonstration is required along with a 10 minute powerpoint (PPT) description.a 10 minute powerpoint (PPT) description.A formal report is also required along with the source code.A formal report is also required along with the source code.Additional information on course web pageAdditional information on course web pageAdditional information on course web page Additional information on course web page http://ecee.colorado.edu/~ecen5633/http://ecee.colorado.edu/~ecen5633/

2010 Project2010 Project2010 Project2010 Project

Altera DE2 BoardAltera DE2 BoardOverviewOverview

Altera DE2 BoardAltera DE2 BoardAltera DE2 BoardAltera DE2 Board

FPGAFPGAFPGAFPGACyclone II EP2C35F672C6 with EPCS16 16Cyclone II EP2C35F672C6 with EPCS16 16--Mbit Mbit serial configuration device serial configuration device

MemoryMemory88--Mbytes SDRAM, 512K SRAM, 4 Mbytes FlashMbytes SDRAM, 512K SRAM, 4 Mbytes FlashSD Memory slotSD Memory slot

DisplaysDisplays16x2 LCD display16x2 LCD displayEight 7Eight 7--segment displayssegment displays

Altera DE2 BoardAltera DE2 BoardAltera DE2 BoardAltera DE2 Board

Switches and LEDsSwitches and LEDsSwitches and LEDsSwitches and LEDs18 toggle switches18 toggle switches18 red LEDs18 red LEDs18 red LEDs18 red LEDs9 green LEDs9 green LEDsFour debounced pushbutton switchesFour debounced pushbutton switchespp

ClocksClocks50 MHz crystal for FPGA clock input50 MHz crystal for FPGA clock inputy py p27 MHz crystal for video applications27 MHz crystal for video applicationsExternal SMA clock inputExternal SMA clock inputpp

Altera DE2 BoardAltera DE2 BoardAltera DE2 BoardAltera DE2 BoardI/O DevicesI/O Devices

Built-in USB-BlasterTM cable for FPGA configuration 10/100 Ethernet RS232 Video Out (VGA 10-bit DAC) Video In (NTSC/PAL/Multi-format)Video In (NTSC/PAL/Multi format) USB 2.0 (type A and type B) PS/2 mouse or keyboard port Line In/Out, Microphone In (24-bit Audio CODEC) Expansion headers (76 signal pins) Infrared portInfrared port

Introduction to Embedded SystemsIntroduction to Embedded SystemsIntroduction to Embedded SystemsIntroduction to Embedded Systems

Big PictureBig PictureBig PictureBig Picture

What are embedded systems?What are embedded systems?

Sophisticated functionality.Real-time operationReal-time operation.Low manufacturing cost.Low power.Designed to tight deadlines by g g ysmall teams.

Embedded SystemsEmbedded SystemsEmbedded SystemsEmbedded Systems

E b dd d t d iEmbedded system: any device that includes a programmable computer but is not itself a pgeneral-purpose computer, such as a personal computer (PC).

Examples:• Personal digital assistant (PDA).• Printer.• Cell phone.• Automobile: engine, brakes, etc.• Television.

H h ld li• Household appliances.

Basic Computer SystemBasic Computer SystemBasic Computer SystemBasic Computer System

CPUMemory I/OInterface

To I/O

BUS

CPU: Central Processor UnitI/O: Input/OutputMemory: Program and DataBus: Address signals, Control signals, and Data signalsBus: Address signals, Control signals, and Data signals

MicroprocessorMicroprocessor--Based SystemBased SystemMicroprocessorMicroprocessor Based SystemBased System

CPUMemory I/OInterface

To I/O

BUS

Microprocessore.g. Pentium 4

CPU: Central Processor UnitI/O: Input/OutputMemory: Program and DataBus: Address signals, Control signals, and Data signalsBus: Address signals, Control signals, and Data signals

MicrocontrollerMicrocontroller--Based SystemBased SystemMicrocontrollerMicrocontroller Based SystemBased System

CPUMemory I/OInterface

To I/O

BUS

Microcontrollere.g. Intel 8051

CPU: Central Processor UnitI/O: Input/OutputMemory: Program and DataBus: Address signals, Control signals, and Data signals

(Although a microcontroller may access external memory as well.)

ALTERA DE2 BOARDALTERA DE2 BOARDCYCLONE II

INPUTDevices

OutputDevices

Cyclone II(SOPC)(SOPC)

C/C++LLanguage

Code

Functional ComplexityFunctional ComplexityFunctional ComplexityFunctional Complexity

Often have to run sophisticated algorithmsOften have to run sophisticated algorithmsOften have to run sophisticated algorithms Often have to run sophisticated algorithms or multiple algorithms.or multiple algorithms.

Cell phone laser printer etcCell phone laser printer etcCell phone, laser printer, etc.Cell phone, laser printer, etc.Often provide complex user interfaces.Often provide complex user interfaces.Must be Must be ReliableReliable and and securesecureDesigned to tight deadlines by small Designed to tight deadlines by small teams.teams.

Design ProcessDesign ProcessDesign ProcessDesign Process

Requirements SpecificationRequirements SpecificationRequirements SpecificationRequirements SpecificationConceptualizationConceptualizationA l iA l iAnalysisAnalysisSynthesisSynthesis Iteration

VerificationVerificationDocumentationDocumentationDocumentationDocumentation

Design AbstractionDesign Abstraction

Design AbstractionDesign AbstractionDesign AbstractionDesign AbstractionExample: Design a “system” which will complement input Ap g y p p

AF(x)

Y = AF(x)

where A and Y are single bit valueswhere A and Y are single bit values

We can “describe” this design using a logical Truth Table

AA YY00 1100 1111 00

Levels of Design AbstractionLevels of Design AbstractionLevels of Design AbstractionLevels of Design Abstraction

Our goal in ECEN 4633/5633 is physical or hardware implementationsf th d iof the design.

1 5Vcc1

0

Design

Specs

a11

a22

3a3

4a4

b1

b2

b3

b4

5

6

7

8

Vcc1

GND

0

Hard-ware

DesignProcess

In ECEN 4633/5633, we “design” at several levels of “abstraction”of abstraction

Levels of Design AbstractionLevels of Design AbstractionLevels of Design AbstractionLevels of Design AbstractionExample: Design a “system” which will complement input ASystem Level:

A C/C++C d

Y = A

Code

C/C++ code:C/C++ code:

Y = ~A;

Levels of Design AbstractionLevels of Design AbstractionLevels of Design AbstractionLevels of Design AbstractionExample: Design a “system” which will complement input ABehavioral Level:

ANot A

Y = A

VHDL code:

Y <= not A;Y <= not A;

Levels of Design AbstractionLevels of Design AbstractionLevels of Design AbstractionLevels of Design AbstractionExample: Design a “system” which will complement input AGate Level:

p g y p p

A Y = A

InverterSymbol

Levels of Design AbstractionLevels of Design AbstractionLevels of Design AbstractionLevels of Design AbstractionExample: Design a “system” which will complement input ACircuit Level:

p g y p p

Vdd PFET

A Y = A

NFET

CMOS Technology

Levels of Design AbstractionLevels of Design AbstractionLevels of Design AbstractionLevels of Design AbstractionExample: Design a “system” which will complement input ADigital IC Design:

p g y p p

Y = A

VDD GND

Y A

VDD GND

AA

CMOS Technology

Levels of Design AbstractionLevels of Design AbstractionLevels of Design AbstractionLevels of Design AbstractionFabrication Level:

N+ N+P+P+

NWELL

PSUB

Summary of LevelsSummary of LevelsSummary of LevelsSummary of Levels

“System”“System”:: C/C++C/C++SystemSystem : : C/C++C/C++BehavioralBehavioral: : VHDL/VerilogVHDL/VerilogL i lL i l G tG tLogicalLogical: : GatesGatesElectronic CircuitElectronic Circuit: : TransistorsTransistorsIntegrated CircuitIntegrated Circuit: : IC LayoutIC LayoutFabricationFabrication:: IC ProcessingIC ProcessingFabricationFabrication: : IC ProcessingIC Processing

Microprocessors in EmbeddedMicroprocessors in EmbeddedMicroprocessors in Embedded Microprocessors in Embedded SystemsSystems

Ordinary microprocessor:Ordinary microprocessor: CPU plus onCPU plus on--chipchipOrdinary microprocessor: Ordinary microprocessor: CPU plus onCPU plus on chip chip cache units.cache units.

Microcontroller:Microcontroller: includes I/O devices, onincludes I/O devices, on--board board ,,memory.memory.

Digital signal processor (DSP):Digital signal processor (DSP): microprocessor microprocessor g g p ( )g g p ( ) ppoptimized for digital signal processing.optimized for digital signal processing.

Hard core vs. soft core.Hard core vs. soft core.Typical embedded word sizes: 8Typical embedded word sizes: 8--bit, 16bit, 16--bit, 32bit, 32--

bit.bit.

Embedded MicroprocessorsEmbedded MicroprocessorsEmbedded MicroprocessorsEmbedded Microprocessors

ARM, MIPS, Power PC, Freescale, 8051,ARM, MIPS, Power PC, Freescale, 8051,ARM, MIPS, Power PC, Freescale, 8051, ARM, MIPS, Power PC, Freescale, 8051, X86X86Various purposesVarious purposesVarious purposesVarious purposes

Networks Networks –– MIPSMIPSMobile phoneMobile phone –– ARM dominatedARM dominatedMobile phone Mobile phone ARM dominatedARM dominatedIndustrial Industrial –– Freescale ColdfireFreescale ColdfireSecurity Security –– 8051 based, Infineon8051 based, Infineonyy ,,High performance High performance –– X86, Intel Epic, other X86, Intel Epic, other VLIW and superscalarsVLIW and superscalars

Von Neumann CPU ArchitectureVon Neumann CPU ArchitectureVon Neumann CPU ArchitectureVon Neumann CPU Architecture

Memory holds data and instructionsMemory holds data and instructionsMemory holds data and instructions.Memory holds data and instructions.Central processing unit (CPU) fetches Central processing unit (CPU) fetches instructions from memoryinstructions from memoryinstructions from memory.instructions from memory.

Separation between CPU and memory Separation between CPU and memory distinguishes programmable computerdistinguishes programmable computerdistinguishes programmable computer.distinguishes programmable computer.

CPU registers: CPU registers: program counter (PC)program counter (PC)generalgeneral--purpose registerspurpose registers

Harvard ArchitectureHarvard ArchitectureHarvard ArchitectureHarvard Architecture

d t

address

CPU

data memory data

addressPC

program memory

address

instructions IRIR

RISC vs CISCRISC vs CISCRISC vs. CISCRISC vs. CISCComplex instruction set computer (Complex instruction set computer (CISCCISC):):p p (p p ( ))

many addressing modesmany addressing modesmost operations can access memorymost operations can access memoryvariable length instructionsvariable length instructionsgg

Reduced instruction set computer (Reduced instruction set computer (RISCRISC):):only load/store can access memoryonly load/store can access memoryfixedfixed length instructionslength instructionsfixedfixed--length instructions length instructions

Instruction set architectures (Instruction set architectures (ISAISA))–– characteristics:characteristics:Fixed vs. variable length.Fixed vs. variable length.Add i dAdd i dAddressing modes.Addressing modes.Number of operands.Number of operands.Types of operandsTypes of operands

Soft Core ProcessorsSoft Core ProcessorsSoft Core ProcessorsSoft Core ProcessorsAre soft, i.e. specified through field programming just like Are soft, i.e. specified through field programming just like p g p g g jp g p g g jprogrammable logic programmable logic

Shipped as hardware description files, which can be mapped Shipped as hardware description files, which can be mapped onto FPGA. e.g: Nios 2.onto FPGA. e.g: Nios 2.Are bundled with software development tools (compiler, Are bundled with software development tools (compiler, simulator, etc.)simulator, etc.)

Offer flexibility as microprocessor parameters can be Offer flexibility as microprocessor parameters can be y p py p ptuned to the application with tight ontuned to the application with tight on--chip interconnection chip interconnection with additional circuitry.with additional circuitry.Designs can be marketed quickly. You can test andDesigns can be marketed quickly. You can test andDesigns can be marketed quickly. You can test and Designs can be marketed quickly. You can test and validate many designs quickly without making any validate many designs quickly without making any specific board; no soldering and no wiring!specific board; no soldering and no wiring!

What is Nios 2?What is Nios 2?What is Nios 2?What is Nios 2?A 32A 32--bit soft core processor from Alterabit soft core processor from AlterappComes in three flavors: Fast, Standard, LightComes in three flavors: Fast, Standard, LightThe three cores trade FPGA area and power The three cores trade FPGA area and power consumption for speed of executionconsumption for speed of executionconsumption for speed of execution.consumption for speed of execution.Is a RISC, Harvard Architecture: Simple Is a RISC, Harvard Architecture: Simple instructions, separate data and instruction instructions, separate data and instruction , p, pmemories.memories.Has 32 levels of interrupts.Has 32 levels of interrupts.Uses the Avalon Bus interface (Avalon SwitchUses the Avalon Bus interface (Avalon SwitchUses the Avalon Bus interface (Avalon Switch Uses the Avalon Bus interface (Avalon Switch Fabric)Fabric)Programs compiled using GNU C/C++ toolchainPrograms compiled using GNU C/C++ toolchaing p gg p g

Nios 2 ArchitectureNios 2 ArchitectureNios 2 ArchitectureNios 2 Architecture

Three forms of Nios 2Three forms of Nios 2Three forms of Nios 2Three forms of Nios 2Nios II/fNios II/f——The Nios II/f “fast” core is designed for The Nios II/f “fast” core is designed for ggfast performance. As a result, this core presents fast performance. As a result, this core presents the most configuration options allowing you to the most configuration options allowing you to finefine--tune the processor for performance.tune the processor for performance.p pp pNios II/sNios II/s——The Nios II/s “standard” core is The Nios II/s “standard” core is designed for small size while maintaining designed for small size while maintaining performanceperformanceperformance.performance.Nios II/eNios II/e——The Nios II/e “economy” core is The Nios II/e “economy” core is designed to achieve the smallest possible core designed to achieve the smallest possible core i A l hi h li i d fi A l hi h li i d fsize. As a result, this core has a limited feature size. As a result, this core has a limited feature

set, and many settings are not available when set, and many settings are not available when the Nios II/e core is selected.the Nios II/e core is selected.

Selection in SOPC (System On a Programmable Chip):Selection in SOPC (System On a Programmable Chip):Se ect o SO C (Syste O a og a ab e C p)Se ect o SO C (Syste O a og a ab e C p)

SOPCSOPCSOPCSOPCSSystem ystem OOn a n a PProgrammable rogrammable CChip hip –– a hardware development tool.a hardware development tool.Used for integrating various hardware components together like:Used for integrating various hardware components together like:

Microprocessors, such as the Nios II processorMicroprocessors, such as the Nios II processorTimersTimersSerial communication interfaces: UART SPISerial communication interfaces: UART SPISerial communication interfaces: UART, SPISerial communication interfaces: UART, SPIGeneral purpose I/OGeneral purpose I/ODigital signal processing (DSP) functionsDigital signal processing (DSP) functionsCommunications peripheralsCommunications peripheralsInterfaces to offInterfaces to off--chip deviceschip devices

Memory controllersMemory controllersBuses and bridgesBuses and bridgesApplicationApplication--specific standard products (ASSP)specific standard products (ASSP)ApplicationApplication--specific integrated circuits (ASIC)specific integrated circuits (ASIC)ProcessorsProcessors

Generates files in Verilog or VHDL which can be added to the Generates files in Verilog or VHDL which can be added to the Quartus 2 project.Quartus 2 project.Qua tus p ojectQua tus p oject

Example Nios system:Example Nios system:Example Nios system:Example Nios system:

SOPC with Nios IISOPC with Nios IISOPC with Nios IISOPC with Nios II

Altera SOPC BuilderAltera SOPC BuilderAltera SOPC BuilderAltera SOPC Builder

Avalon Switch FabricAvalon Switch Fabric

Avalon Switch FabricAvalon Switch FabricAvalon Switch FabricAvalon Switch FabricProprietary interconnect specification used with Nios IIProprietary interconnect specification used with Nios II

Principal design goalsPrincipal design goalsLow resource utilization for Low resource utilization for bus logicbus logicSimplicitySimplicitySynchronous operationSynchronous operation

Transfer TypesTransfer TypesSlave TransfersSlave TransfersMaster TransfersMaster TransfersMaster TransfersMaster TransfersStreaming TransfersStreaming TransfersLatencyLatency--Aware TransfersAware TransfersBurst TransfersBurst TransfersBurst TransfersBurst Transfers

Avalon Switch FabricAvalon Switch FabricAvalon Switch FabricAvalon Switch FabricCustomCustom--Generated for PeripheralsGenerated for Peripheralspp

Contingencies are on a PerContingencies are on a Per--Peripheral BasisPeripheral BasisSystem is Not Burdened by Bus ComplexitySystem is Not Burdened by Bus Complexity

SOPC Builder Automatically GeneratesSOPC Builder Automatically GeneratesArbitrationArbitrationAddress DecodingAddress DecodingData Path MultiplexingData Path MultiplexingBus SizingBus SizingBus SizingBus SizingWaitWait--State GenerationState GenerationInterruptsInterruptsInterruptsInterrupts

Avalon Master PortsAvalon Master PortsAvalon Master PortsAvalon Master Ports

Initiate Transfers with Avalon Switch FabricInitiate Transfers with Avalon Switch FabricInitiate Transfers with Avalon Switch FabricInitiate Transfers with Avalon Switch FabricTransfer TypesTransfer Types

Fundamental Read Fundamental Read Fundamental WriteFundamental Write

All Avalon Masters Must Honor a waitrequest All Avalon Masters Must Honor a waitrequest signalsignalTransfer PropertiesTransfer Properties

LLLatencyLatencyStreamingStreamingBurstBurst

Avalon Slave PortsAvalon Slave PortsAvalon Slave PortsAvalon Slave Ports

Respond to Transfer Requests fromRespond to Transfer Requests fromRespond to Transfer Requests from Respond to Transfer Requests from Avalon Switch FabricAvalon Switch FabricTransfer TypesTransfer TypesTransfer TypesTransfer Types

Fundamental Read Fundamental Read Fundamental WriteFundamental Write

Transfer PropertiesTransfer PropertiesWait StatesWait StatesLatencyLatencyStreamingStreamingBurstBurstBurstBurst

Slave Read TransferSlave Read TransferSlave Read TransferSlave Read Transfer

clkA C D EB

clk

address,be_n

readn

address, be_n

chipselect

readdata readdata

Slave Write TransferSlave Write TransferSlave Write TransferSlave Write Transfer

A B C Dclk

address,be_n

writedata

address, be_n

writedata

A B C D

writen

chipselect

AssignmentsAssignments

AssigmentsAssigmentsAssigmentsAssigments

Suggested ReadingSuggested ReadingSuggested ReadingSuggested ReadingChapters 1Chapters 1--3 in textbook3 in textbook

Should be a quick reviewShould be a quick reviewShould be a quick reviewShould be a quick reviewDE2_UserManual on DE2_UserManual on http://ecee.colorado.edu/~ecen5633/http://ecee.colorado.edu/~ecen5633/pp

Can be used as a quick referenceCan be used as a quick reference

HW # 1, due by midnight September 3, 2010 HW # 1, due by midnight September 3, 2010 Lab #1, due by August 31 (at the start of lab)Lab #1, due by August 31 (at the start of lab)

Q ti ?Q ti ?Questions?Questions?