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8/12/2019 EDA ToolsUnit I

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Synthesis and Simulationusing HDLs

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Logic Synthesis

Logic Synthesis provides a link between a HDL and a netlist

Verilog was designed as a simulation language

VHDL was designed as a documentation and description language.

Both Verilog and VHDL were developed in the early 1980s

Logic synthesis tools were developed later

Graphic or text design entry methods are used to create a HDL behavioral

State diagrams, Graphical datapath descriptions, Truth tables, RAM/ROMtemplates and gate level schematics may also be used


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Logic Synthesis

After HDL description Logic synthesizer and a cell library are necess

proceed

Most synthesis software companies produce only software

Most ASIC vendors produce only cell libraries


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Logic Synthesis

Behavioral model is simulated to check the design meets the requirem

Logic synthesizer is used to generate a netlist, a structural model

Which contains only references to logic cells

Following logic synthesis the design is simulated again

Results are compared

Layout generation from the structural model produced by logic synth


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Inside a Logic Synthesizer

The logic synthesizer parses HDL description and builds an internal data structure

Logic minimization tries to minimize the structure

Logic optimization used a series of factoring, substitution, and elimination steps to simequations

Logic optimization attempts to minimize area and speed also.

The technology-decomposition step builds a generic network from the optimized logic

The generic network is in a technology-independent form

Next, The technology mapping

While performing logic mapping, the algorithms attempt to minimize area


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Verilog and Logic Synthesis

Verilog logic description starts with the keyword module

MODULE mychip_asic();

------

(Code to model ASIC I/O)

------

ENDMODULE

Top down approach


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Top down approach


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Verilog Modeling

MODULE mux (sel,a,b,z);

INPUT sel,a,b;

OUTPUT z;

REG z;

ALWAYS @ (sel,a,b)BEGIN

IF(sel) z


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Delays in Verilog

Synthesis tools ignore delay values


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Blocking and Non-blocking Assignme

Blocking assignment

Non-Blocking assignment


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Combinational Logic in Verilog


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Multiplexers in Verilog


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Verilog Case Statement


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Decoders in Verilog


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Priority Encoder in Verilog


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Arithmetic in Verilog


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Sequential Logic in Verilog

D-Flip Flop

ALWAYS@ (POSEDGE clock) Q= D;

D- Latch

ALWAYS @ (clock or D) if(clock) Q=D;


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Component Instantiation in Verilog


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VHDL and Logic Synthesis

IEEE VHDL nine valued system


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Combinational Logic Synthesis in VH


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Multiplexers in VHDL


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Decoders in VHDL


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Adders in VHDL


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Sequential Logic in VHDLWith a sensitivity list with and a EVENT plus a specific level


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Sequential Logic in VHDL

No sensitivity list with a wait until statement


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Component Instantiation in VHDL


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Performance Driven Synthesis

Many logic synthesizers allow the use of directives.

These directives become complex when we need to describe complex timinconstraints

Suppose if we want to improve timing performance of a Mux, First we depathcluster.

Next, we specify the required time for a signal to reach the output nodes

Finally, we specify the arrival time of the signal at all the inputs as 0ns

The logic optimization step will specify the logic network and then map it tlibrary while attempting to meet the timing constraints


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FSM Synthesis

There are three ways to synthesize FSMs

Omit any special synthesis directives and let the logic synthesizer operate on t

machine as though it were random logic

Use directives to guide the logic synthesis tool to improve or modify state ass

Use a special state machine compiler, separate from the logic synthesizer, to othe state machine


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Memory Synthesis

There are several approaches to memory synthesis:

Random logic using Flipflops and Latches

Register files in datapaths

RAM standard components

RAM compilers


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Simulation

Engineers used to prototype system to check their designs

Breadboarding was feasible when it was possible to construct system

few off-the-self TTL parts

It is impractical for prototyping an ASIC


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Types of Simulation

Behavioral Simulation

Functional Simulation

Static Timing Simulation

Gate-Level Simulation Switch-Level Simulation

Transistor-Level or Circuit Level Simulation


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Formal Verification

Logic synthesizer translate Behavioral model to a structural model

Formal verification can prove in the mathematical sense that two

representations are equivalent

If they are not, the software tell why and how the two representation


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Transistor Level Simulation

Sometimes we need to simulate circuits more accurate than switch le

simulation

We turn to simulators that can solve circuit equations exactly, given m

for the nonlinear transistors, and predict the analog behavior

This type of Transistor level simulation is costly

If is impossible to simulate more than a hundred logic cells using a c

level simulation


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