edge-triggered flip-flop, state table, state diagram flip-flop • contrast to pulse-triggered sr...
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![Page 1: Edge-triggered Flip-Flop, State Table, State Diagram Flip-Flop • Contrast to Pulse-triggered SR Flip-Flop • Pulse-triggered: Read input while clock is 1, change output when the](https://reader033.vdocument.in/reader033/viewer/2022052917/5ab0cea17f8b9a7e1d8b946b/html5/thumbnails/1.jpg)
Edge-triggered Flip-Flop, State Table, State Diagram
![Page 2: Edge-triggered Flip-Flop, State Table, State Diagram Flip-Flop • Contrast to Pulse-triggered SR Flip-Flop • Pulse-triggered: Read input while clock is 1, change output when the](https://reader033.vdocument.in/reader033/viewer/2022052917/5ab0cea17f8b9a7e1d8b946b/html5/thumbnails/2.jpg)
Edge-triggered Flip-Flop • Contrast to Pulse-triggered SR Flip-Flop
• Pulse-triggered: Read input while clock is 1, change output when the clock goes to 0. What happens during the entire HIGH part of clock can affect eventual output.
• Edge-triggered: Read input only on edge of clock cycle (positive or negative) • Example below: Positive Edge-Triggered D Flip-Flop
• On the positive edge (while the clock is going from 0 to 1), the input D is read, and almost immediately propagated to the output Q. Only the value of D at the positive edge matters.
D
C
S
C
R
D
Clock
Q
Q
![Page 3: Edge-triggered Flip-Flop, State Table, State Diagram Flip-Flop • Contrast to Pulse-triggered SR Flip-Flop • Pulse-triggered: Read input while clock is 1, change output when the](https://reader033.vdocument.in/reader033/viewer/2022052917/5ab0cea17f8b9a7e1d8b946b/html5/thumbnails/3.jpg)
Symbol
• Symbol of edge-triggered D flip-flop
D
C
D
C
Positive-edge triggered Negative-edge triggered
![Page 4: Edge-triggered Flip-Flop, State Table, State Diagram Flip-Flop • Contrast to Pulse-triggered SR Flip-Flop • Pulse-triggered: Read input while clock is 1, change output when the](https://reader033.vdocument.in/reader033/viewer/2022052917/5ab0cea17f8b9a7e1d8b946b/html5/thumbnails/4.jpg)
Flip-Flop Timing
• Set-up time: ts • Input needs to be stable before trigger
• Hold time: th • Input needs to be stable after trigger
• Propagation delay: tp • Some delay from trigger to output change
• Example: Negative edge triggered flip-flip
Clock
ts th
tp
![Page 5: Edge-triggered Flip-Flop, State Table, State Diagram Flip-Flop • Contrast to Pulse-triggered SR Flip-Flop • Pulse-triggered: Read input while clock is 1, change output when the](https://reader033.vdocument.in/reader033/viewer/2022052917/5ab0cea17f8b9a7e1d8b946b/html5/thumbnails/5.jpg)
Sequential Circuit Description
• Input Equations
• State Table
• State Diagram
• We’ll use the following example
![Page 6: Edge-triggered Flip-Flop, State Table, State Diagram Flip-Flop • Contrast to Pulse-triggered SR Flip-Flop • Pulse-triggered: Read input while clock is 1, change output when the](https://reader033.vdocument.in/reader033/viewer/2022052917/5ab0cea17f8b9a7e1d8b946b/html5/thumbnails/6.jpg)
Sequential Circuit Description
D
C
D
C
Clock
X A
A
B
B
Y
![Page 7: Edge-triggered Flip-Flop, State Table, State Diagram Flip-Flop • Contrast to Pulse-triggered SR Flip-Flop • Pulse-triggered: Read input while clock is 1, change output when the](https://reader033.vdocument.in/reader033/viewer/2022052917/5ab0cea17f8b9a7e1d8b946b/html5/thumbnails/7.jpg)
Sequential Circuit Description
D
C
D
C
Clock
X A
A
B
B
Y
input
output
Next state Present state
At the clock trigger, the next state
will be read and transferred to the
present state
![Page 8: Edge-triggered Flip-Flop, State Table, State Diagram Flip-Flop • Contrast to Pulse-triggered SR Flip-Flop • Pulse-triggered: Read input while clock is 1, change output when the](https://reader033.vdocument.in/reader033/viewer/2022052917/5ab0cea17f8b9a7e1d8b946b/html5/thumbnails/8.jpg)
Input Equations
Anext = ApresentX + BpresentX
Bnext = A’presentX
Y = (Apresent + Bpresent)X’
Next state in terms of
input and present state
Output in terms of input
and present state
![Page 9: Edge-triggered Flip-Flop, State Table, State Diagram Flip-Flop • Contrast to Pulse-triggered SR Flip-Flop • Pulse-triggered: Read input while clock is 1, change output when the](https://reader033.vdocument.in/reader033/viewer/2022052917/5ab0cea17f8b9a7e1d8b946b/html5/thumbnails/9.jpg)
State Table
Present State Input Next State Output
A B X A B Y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 1 0 0
![Page 10: Edge-triggered Flip-Flop, State Table, State Diagram Flip-Flop • Contrast to Pulse-triggered SR Flip-Flop • Pulse-triggered: Read input while clock is 1, change output when the](https://reader033.vdocument.in/reader033/viewer/2022052917/5ab0cea17f8b9a7e1d8b946b/html5/thumbnails/10.jpg)
State Diagram
00 01
11 10
0/0 1/0
0/1
1/0 0/1
1/0
1/0
0/1
![Page 11: Edge-triggered Flip-Flop, State Table, State Diagram Flip-Flop • Contrast to Pulse-triggered SR Flip-Flop • Pulse-triggered: Read input while clock is 1, change output when the](https://reader033.vdocument.in/reader033/viewer/2022052917/5ab0cea17f8b9a7e1d8b946b/html5/thumbnails/11.jpg)
Mealy and Moore Models
• Preceding Example: Output depends on present state and input. This is called the Mealy Model
• Another kind of circuit: Output only depends on present state. This is called the Moore Model
![Page 12: Edge-triggered Flip-Flop, State Table, State Diagram Flip-Flop • Contrast to Pulse-triggered SR Flip-Flop • Pulse-triggered: Read input while clock is 1, change output when the](https://reader033.vdocument.in/reader033/viewer/2022052917/5ab0cea17f8b9a7e1d8b946b/html5/thumbnails/12.jpg)
Example of Moore Model X
Y D
C
Clock
A Z
Anext = Apresent + XY
Z = Apresent
0/0 1/1
X Y Apresent Anext
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
00,01,10 11
00,01,10,11
![Page 13: Edge-triggered Flip-Flop, State Table, State Diagram Flip-Flop • Contrast to Pulse-triggered SR Flip-Flop • Pulse-triggered: Read input while clock is 1, change output when the](https://reader033.vdocument.in/reader033/viewer/2022052917/5ab0cea17f8b9a7e1d8b946b/html5/thumbnails/13.jpg)
Moore Model
Some
Combinational
Circuit Outputs
Inputs Some
Combinational
Circuit
Flip-flops
![Page 14: Edge-triggered Flip-Flop, State Table, State Diagram Flip-Flop • Contrast to Pulse-triggered SR Flip-Flop • Pulse-triggered: Read input while clock is 1, change output when the](https://reader033.vdocument.in/reader033/viewer/2022052917/5ab0cea17f8b9a7e1d8b946b/html5/thumbnails/14.jpg)
Mealy Model
Some
Combinational
Circuit Outputs
Inputs Some
Combinational
Circuit
Flip-flops
![Page 15: Edge-triggered Flip-Flop, State Table, State Diagram Flip-Flop • Contrast to Pulse-triggered SR Flip-Flop • Pulse-triggered: Read input while clock is 1, change output when the](https://reader033.vdocument.in/reader033/viewer/2022052917/5ab0cea17f8b9a7e1d8b946b/html5/thumbnails/15.jpg)
Mealy and Moore Model State Diagrams
00 01
11 10
0/0 1/0
0/1
1/0 0/1
1/0
1/0
0/1
0/0 1/1
00,01,10 11
00,01,10,11
Moore
input
state output
input
output
state
![Page 16: Edge-triggered Flip-Flop, State Table, State Diagram Flip-Flop • Contrast to Pulse-triggered SR Flip-Flop • Pulse-triggered: Read input while clock is 1, change output when the](https://reader033.vdocument.in/reader033/viewer/2022052917/5ab0cea17f8b9a7e1d8b946b/html5/thumbnails/16.jpg)
How to Design a Sequential Circuit
• 1. Specification
• 2. Formulation: Draw a state diagram
• 3. Assign state number for each state
• 4. Draw state table
• 5. Derive input equations
• 5. One D flip-flop for each state bit
![Page 17: Edge-triggered Flip-Flop, State Table, State Diagram Flip-Flop • Contrast to Pulse-triggered SR Flip-Flop • Pulse-triggered: Read input while clock is 1, change output when the](https://reader033.vdocument.in/reader033/viewer/2022052917/5ab0cea17f8b9a7e1d8b946b/html5/thumbnails/17.jpg)
Example
• Design a sequential circuit to recognize the input sequence 1101.
• That is, output 1 if the sequence 1101 has been read, output 0 otherwise.
A B C D
0/0
1/0 1/0
1/0
0/0
0/0 1/1
0/0
![Page 18: Edge-triggered Flip-Flop, State Table, State Diagram Flip-Flop • Contrast to Pulse-triggered SR Flip-Flop • Pulse-triggered: Read input while clock is 1, change output when the](https://reader033.vdocument.in/reader033/viewer/2022052917/5ab0cea17f8b9a7e1d8b946b/html5/thumbnails/18.jpg)
Assign States
• 4 states, so we need 2 bits
00 01 10 11
0/0
1/0 1/0
1/0
0/0
0/0 1/1
0/0
![Page 19: Edge-triggered Flip-Flop, State Table, State Diagram Flip-Flop • Contrast to Pulse-triggered SR Flip-Flop • Pulse-triggered: Read input while clock is 1, change output when the](https://reader033.vdocument.in/reader033/viewer/2022052917/5ab0cea17f8b9a7e1d8b946b/html5/thumbnails/19.jpg)
State Table
Present State Input Next State Output
A B X A B Y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 0
0 1 1 1 0 0
1 0 0 1 1 0
1 0 1 1 0 0
1 1 0 0 0 0
1 1 1 0 1 1
![Page 20: Edge-triggered Flip-Flop, State Table, State Diagram Flip-Flop • Contrast to Pulse-triggered SR Flip-Flop • Pulse-triggered: Read input while clock is 1, change output when the](https://reader033.vdocument.in/reader033/viewer/2022052917/5ab0cea17f8b9a7e1d8b946b/html5/thumbnails/20.jpg)
Input Equations
Anext = A’BX + AB’
Bnext = A’B’X + AB’X’ + ABX
Y = ABX
![Page 21: Edge-triggered Flip-Flop, State Table, State Diagram Flip-Flop • Contrast to Pulse-triggered SR Flip-Flop • Pulse-triggered: Read input while clock is 1, change output when the](https://reader033.vdocument.in/reader033/viewer/2022052917/5ab0cea17f8b9a7e1d8b946b/html5/thumbnails/21.jpg)
Circuit Diagram
D
C
D
C
Clock
X A
A
B
B
Y
Exercise:
Fill in the input to
Flip-Flop B