EE 466/586EE 466/586VLSI DesignVLSI DesignPartha Pande

School of EECSWashington State University

pande@eecs.wsu.edu

Lecture 7Static MOS Gate CircuitsStatic MOS Gate Circuits

CMOS Gate Sizing NAND and NOR gate sizing Follow board notes

B

A

A B

F

VDDVDD

A B

A

B

F

VDD

A

A

F

1

2 2 2

2

21 1

4

4

Inverter 2-input NAND 2-input NOR

Pseudo-NMOS Gate Sizing

Fanin and Fanout Considerations Gates with a large number of inputs

(high fan-in gates) Too high resistance Area penalty

Follow board notes Fan Out

Output driving capability

Fan Out

VTC of NAND Gates

If input A is held high while input B switched from low to high, the gate is equivalent to an inverter with a 2W pull-up device and a 2W pull-down device. The resulting transfer characteristic would shift to the left of the standard inverter.

VTC of NOR Gates

Static Complementary CMOSVDD

F(In1,In2,…InN)

In1In2

InN

In1In2InN

PUN

PDN

PMOS only

NMOS only

PUN and PDN are dual logic networks…

…

• The function of the PUN is to provide a connection between the output and Vdd anytime the output of the logic gate is meant to be 1

• Similarly the role of the PDN is to connect the output to GND when the output is meant to be 0

NMOS as PDN & PMOS as PUN NMOS device can pull the output all the way

down to GND, but the PMOS device can pull it down to Vtp

NMOS transmits a strong 0 PMOS transmits a strong 1

Complex CMOS Gate

OUT = D + A • (B + C)

DA

B C

D

AB

C

Constructing a Complex Gate

C

(a) pull-down network

SN1 SN4

SN2

SN3D

FF

A

DB

C

D

F

A

B

C

(b) Deriving the pull-up networkhierarchically by identifyingsub-nets

D

A

A

B

C

VDD VDD

B

(c) complete gate

Sequential Logic

2 storage mechanisms• positive feedback• charge-based

COMBINATIONALLOGIC

Registers

Outputs

Next state

CLK

Q D

Current State

Inputs

A latch is level sensitive

A register is edge-triggered

Latch versus Register Latch

Stores data depending on the level of the clock

D

Clk

Q D

Clk

Q

Registerstores data when clock rises

Clk Clk

D D

Q Q

Latches

In

clk

In

Out

Positive Latch

CLK

DG

Q

Out

Outstable

Outfollows In

In

clk

In

Out

Negative Latch

CLK

DG

Q

Out

Outstable

Outfollows In

Latch-Based Design

• N latch is transparentwhen = 0

• P latch is transparent when = 1

NLatch Logic

Logic

PLatch

Timing Definitions

tCLK

tD

tc 2 q

tholdtsu

tQ DATA

STABLE

DATASTABLE

Register

CLK

D Q

Timing Definitions Tsu (Setup time)

Incoming data must be stable before the clock arrives Thold (Hold time)

The length of time the data remains stable after the clock arrives for proper operation

If the data is stable before the setup time and continues to be stable after the hold time, the register will properly capture the data

Tclk-Q (clk to Q delay) This is the delay from the time the clock arrives to the point

at which the Q output stabilizes

Maximum Clock Frequency

FF’s

LOGIC

tp,comb

tclk-Q + tp,comb + tsetup = T

Positive Feedback: Bi-StabilityVi1 Vo2

Vo2 =Vi1

Vo1 =Vi2

Vo1

Vi25Vo1

Vi25Vo1

Vi1

A

C

B

Vo2

Vi1=Vo2

Vo1 Vi2

Vi2=Vo1 A, B – Two stable operating points

Meta-Stability

Gain should be larger than 1 in the transition region

A

C

d

B

V i25

V o1

Vi1 5Vo2

A

C

d

B

V i25

V o1

Vi1 5Vo2

Cross-Coupled Pairs

Forbidden State

S

S

R

QQ

Q

QRS Q

Q00 Q

101 0

010 1011 0R Q

NOR-based set-reset

Cross-Coupled NAND

S

QR

Q

M1

M2

M3

M4Q

M5S

M6CLK

M7 R

M8 CLK

VDD

Q

Cross-coupled NANDsAdded clock

This is not used in datapaths any more,but is a basic building memory cell