ee143 f2010 lecture 18 ic process integrationee143/fa10/lectures/lec_18.pdf · ee143 f2010 lecture...
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Professor N Cheung, U.C. Berkeley
Lecture 18EE143 F2010
1
IC Process Integration
Example IC Process Flows
• Simple resistor
• NMOS - Generic NMOS Process Flow
• CMOS - Generic CMOS Process Flow
Self-aligned Techniques
• LOCOS- self-aligned channel stop
• Self-aligned Source/Drain
• Lightly Doped Drain (LDD)
• Self-aligned silicide (SALICIDE)
• Self-aligned oxide gap
Advance MOS Techniques
• Twin Well CMOS , Retrograde Wells , SOI CMOS
Professor N Cheung, U.C. Berkeley
Lecture 18EE143 F2010
2
Self-aligned channel stop
with Local Oxidation (LOCOS)
Si3N4 CVD
pad oxide
Si
LOCOS Process Flow
Professor N Cheung, U.C. Berkeley
Lecture 18EE143 F2010
3
B+ channel
stop
implant
Si
thermal oxidation
(high temperature)
FOX
Self-aligned
channel stop pp
B
dose
~1013/cm2
Professor N Cheung, U.C. Berkeley
Lecture 18EE143 F2010
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If poly or metal lines lie on top of the Field Oxide (FOX), they will
form a parasitic MOS structure.If these lines carrying a high voltage,
they may create an inversion layer of free carriers at the Si substrate
and shorts out neighboring devices. The relatively highly doped Si
underneath (the “channel stop”) raises the threshold voltage of
this parasitic MOS. If this threshold voltage value is higher than
the highest circuit voltage, inversion will not occur.
SiO2
p-Si
metal
Comment: Field Oxide Channel Inversion
Inversion
Layer
Device 1Device 2
Professor N Cheung, U.C. Berkeley
Lecture 18EE143 F2010
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Comments : Non self-aligned alternative:
P.R.1
SiO2
P+ P+
SiP+ P+
SiO2
2
B+
3
Disadvantages1 Two lithography steps
2 Channel stop doping not FOX aligned
Professor N Cheung, U.C. Berkeley
Lecture 18EE143 F2010
6
Self-aligned Source and Drain
n+n+
poly-Si gate
As+
n+n+
As+
Off Alignment
Perfect Alignment
* The n+ S/D always follows gate
Professor N Cheung, U.C. Berkeley
Lecture 18EE143 F2010
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Comment: Non self-aligned Alternative
.n+n+ 2
.n+n+
Solution: Use
gate overlap
to avoid offset
error.
.n+n+ 1
Channel not linked to S/D
Stray
capacitance
Disadvantages: Two lithography steps, excess gate overlap capacitance
Professor N Cheung, U.C. Berkeley
Lecture 18EE143 F2010
8
Lightly Doped Drain (LDD)
LDD
(1E17-to 1E18/cm3)
Professor N Cheung, U.C. Berkeley
Lecture 18EE143 F2010
9
Lightly Doped Source/Drain MOSFET (LDD)
The n-pockets (LDD) doped to medium conc (~1E18) are used to
smear out the strong E-field between the channel and heavily doped n+
S/D, in order to reduce hot-carrier generation.
n+ n+n nSiO2
CVD oxide
spacer
p-sub
Professor N Cheung, U.C. Berkeley
Lecture 18EE143 F2010
10
n implant
for LDD
SiO2
CVD SiO2
Directional
RIE of CVD Oxide
CVD conformal
deposition SiO2
LDD Process Flow using Ion Implantation
Professor N Cheung, U.C. Berkeley
Lecture 18EE143 F2010
11
Spacer left when CVD SiO2
is just cleared on flat region.
nn
0.05mm
0.25mm
n+ n+
n+ implant
n n
Professor N Cheung, U.C. Berkeley
Lecture 18EE143 F2010
RIE-based Stringers / Spacers
Leftover material must be removed by overetching
Professor N Cheung, U.C. Berkeley
Lecture 18EE143 F2010
13
Self-Aligned Silicide Process (SALICIDE) using Ion
Implantation and Metal-Si reaction
n+n+
TiSi2 (metal)poly-gate
Metal silicides are metallic.
They lower the sheet resistance of S/D and the poly-gate
Professor N Cheung, U.C. Berkeley
Lecture 18EE143 F2010
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n+n+
SiO2
oxide spacer
SALICIDE Process Flow
Professor N Cheung, U.C. Berkeley
Lecture 18EE143 F2010
15
n+n+
SiO2
Ti
Ti deposition
Si
Ti
TiSi2
Ti
Ti
Selective etch to remove
unreacted Ti only
.
2
)700(
2
2
SiOwithreactnotwillTi
TiSiSiTi
Ctreatmentheat o
Professor N Cheung, U.C. Berkeley
Lecture 18EE143 F2010
16
Salicide Gate and Source/Drain
Professor N Cheung, U.C. Berkeley
Lecture 18EE143 F2010
17
Self-aligned Oxide Gap
n+
poly-I
poly-II
small oxide spacing < 30nm
inversion
charge layerpoly-I
substrate
Gate
oxide
poly-IIMOSFET
MOS
Capacitor
DRAM structure ( MOSFET with a capacitor)
V (plate)
For a small spacing
between poly-I and
poly-II, inversion
charges between
MOSFET and
Capacitor are
electrically linked. No
need for a separate
n+ island.
Thermal Oxide grown
conformal on poly-I
Professor N Cheung, U.C. Berkeley
Lecture 18EE143 F2010
Starting material: p-type wafer with NA = 1016 cm-3
Step 1: grow 500 nm of SiO2
Step 2: pattern oxide using the oxide mask (dark field)
Step 3: implant phosphorus and anneal to form an n-type
layer with ND = 1020 cm-3 and depth 100 nm
Step 4: deposit oxide to a thickness of 500 nm
Step 5: pattern deposited oxide using the contact mask (dark field)
Step 6: deposit aluminum to a thickness of 1 mm
Step 7: pattern using the aluminum mask (clear field)
Starting material: p-type wafer with NA = 1016 cm-3
Step 1: grow 500 nm of SiO2
Step 2: pattern oxide using the oxide mask (dark field)
Step 3: implant phosphorus and anneal to form an n-type
layer with ND = 1020 cm-3 and depth 100 nm
Step 4: deposit oxide to a thickness of 500 nm
Step 5: pattern deposited oxide using the contact mask (dark field)
Oxide mask (dark field)
Contact mask (dark field)
Al mask (clear field)
Three-mask process:
Process Flow Example : Resistor
Layout:
A A
Starting material: p-type wafer with NA = 1016 cm-3
Step 1: grow 500 nm of SiO2
Step 2: pattern oxide using the oxide mask (dark field)
Professor N Cheung, U.C. Berkeley
Lecture 18EE143 F2010
p-type Si
Step 2:
Pattern oxide
Step 3: Implant
& Anneal
oxide etchant
p-type Si
photoresist
patterned using
mask #1
phosphorus
blocked by oxide
phosphorus implant:
A-A Cross-Section
SiO2
phosphorus ions
after anneal of
phosphorus implant:n+ layer
p-type Si
lateral diffusion of phosphorus
under oxide during anneal
Professor N Cheung, U.C. Berkeley
Lecture 18EE143 F2010
n+ layer
p-type Si
Step 4: Deposit
500 nm oxide
n+ layer
p-type Si
Step 7:
Pattern metalAl
1st layer of SiO2
2nd layer of SiO2
Step 5:
Pattern oxide n+ layer
p-type Si
Open holes for metal contacts
Professor N Cheung, U.C. Berkeley
Lecture 18EE143 F2010
21
Substrate
Boron doped (100)Si
Resistivity= 20 -cm
Thermal
Oxidation
~100Å pad oxide
CVD Si3N4
~ 0.1 um
Lithography
Pattern Field Oxide
Regions
RIE removal of
Nitride and pad
oxide
Channel Stop
Implant:
3x1012 B/cm2
60keV
Thermal Oxidation
to grow 0.45um
oxide
Wet Etch
Nitrdie and
pad oxide
Ion Implant for
Threshold
Voltage control
8x1011 B/cm2 35keV
Thermal Oxidation
To grow 250Å
gate oxide
LPCVD
Poly-Si
~ 0.35um
Dope Poly-Si to n+
with Phosphorus
Diffusion source
Generic NMOS Process Flow Description
Professor N Cheung, U.C. Berkeley
Lecture 18EE143 F2010
22
Lithography
Poly-Si
Gate pattern
RIE
Poly-Si
gate
Source /Drain
Implantation
~ 1016 As/cm2 80keV
Thermal Oxidation
Grow ~0.1um oxide
on poly-Si
And source/drian
LPCVD
SiO2
~0.35um
Lithography
Contact
Window pattern
RIE removal of
CVD oxide and
thermal oxide
Sputter Deposit
Al metal
~0.7um
Lithography
Al interconnect
pattern
RIE etch of
Al metallization
Sintering at ~400oC in H2 ambient
to improve contact resistance
and to reduce oxide interface charge
Generic NMOS Process Flow Description (cont.)
Professor N Cheung, U.C. Berkeley
Lecture 18EE143 F2010
23
Generic NMOS Process Flow
active
device~5 mm
p-Si <100> 500mm
Boron-doped Si
20 -cm
<100>
NMOS Structure
Professor N Cheung, U.C. Berkeley
Lecture 18EE143 F2010
24
P.R.
SiO2
Si
nitride
SiO2
P.R.
Si
~0.1mm
keV
cmB
60
/103: 212
317 /103 cm
nitride
Professor N Cheung, U.C. Berkeley
Lecture 18EE143 F2010
25
Fox
p+ p+
keVcmB 35/105 211
Fox
p+p+
Professor N Cheung, U.C. Berkeley
Lecture 18EE143 F2010
26
Resist
n+n+
As+ 80keV, 1016/cm2
n+n+
Thermal oxide
Professor N Cheung, U.C. Berkeley
Lecture 18EE143 F2010
27
Al
CVD oxide
intermediate
oxide
n+n+
Si/SiO2
H2 anneal
~ 400oC
(forming gas
is 10% H2
and 90%
N2)
Al
Interface
States Passivation
n+ n+
Professor N Cheung, U.C. Berkeley
Lecture 18EE143 F2010
28
Basic Structure of CMOS Inverter
Professor N Cheung, U.C. Berkeley
Lecture 18EE143 F2010
29
A Generic
CMOS Process
P-well CMOS
Professor N Cheung, U.C. Berkeley
Lecture 18EE143 F2010
30
Pattern mask opening
For p-well implant
Shallow implantation
of boron
Diffusion drive-in
To form p-well in
oxidizing ambient
Remove masking oxide
Professor N Cheung, U.C. Berkeley
Lecture 18EE143 F2010
31
Pad oxide growth and CVD Si3N4.
Pattern field oxide regions
Blanket implant of Boron for p
channel stop inside p-well
Protect p-well regions with
photoresist.
Implant Ph to form n channel
stop outside p-well regions
LOCOS Oxidation
Thermal oxidation of gate SiO2
Professor N Cheung, U.C. Berkeley
Lecture 18EE143 F2010
32
Pattern poly-Si gates and poly lines
Protect ALL n-channel
transistors with photoresist.
Boron implantation to
form source/drain of p-
channel transistors and
contacts to p-well
CVD poly-Si
Professor N Cheung, U.C. Berkeley
Lecture 18EE143 F2010
33
Protect ALL p-channel
transistors with photoresist.
CVD SiO2
(Low-temperature oxide)
Pattern and etch contact
openings to source/drain, well
contact, and substrate contact.
Arsenic implantation to form
source/drain of n-channel
transistors and contacts to n-
substrate
Professor N Cheung, U.C. Berkeley
Lecture 18EE143 F2010
34
Metal 1 deposition
Pattern and etch
Metal 1 interconnects
CVD SiO2
Professor N Cheung, U.C. Berkeley
Lecture 18EE143 F2010
35
Pattern and etch contact
openings to Metal 1.
Metal 2 deposition.
Pattern, and etch Metal 2
interconnects.