EE166 Project

Frequency Dividers

Group Members

• Hengky Chandrahalim

• Toai Nguyen

• Mike Tjuatja

Inputs and Outputs Features

• Input– -1 Clk_In at 5V <200MHz– -1 RESET signal– -4 VDDs at 5V– -4 VSSs

Inputs and Outputs Features

• Outputs– -1 Output at 5V = Clk_In/2– -1 Output at 5 V = Clk_In/3

Key Specifications

• Skew DIV2-DIV3 < 1ns

• Symmetric Tr and Tf DIV2 < 800 ps

• Symmetric Tr and Tf DIV3 < 800 ps

• Duty Cycle : 45%-55%

• Output Load : 10pF

Top Level View of Schematic

Layout View

Extracted View of Layout

Divider Block

Divide by 2 Block

DFF Schematic

DFF Layout

Divide by 3 Block

Layout Divide by 3

Pulse Stretcher

Test Bench

• Test functionality of the circuit

• Test the outputs skew

• Test Tr and Tf of the outputs

• Test the duty cycle

• Test the driving capability

Schematic of the test bench

Functionality

Functionality

Outputs Skew

Duty Cycle Divide by 2

Duty Cycle Divide by3

Tr of Divide by2

Tf of Divide by2

Tr of Divide by 3

Tf of Divide by3

Conclusion• Process used for the design is AMI16• Total area used in the design is 1740.47 mil^2• The circuit is functional• Skew outputs is about 950 ps• Duty cycles 45%-55%• The circuit is capable of driving 20 pF load• Pavg=1/2 x CL x f x VDD^2

• Pavg=1/2 x 20pf x 100MHz x 25 = 25mW