ee247 lecture 13 - university of california, berkeleyee247/fa06/lectures/l13_f06_.pdf · eecs 247...
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EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 1
EE247Lecture 13
Today:– Data converters
• Static converter error sources– Offset & full-scale error– DNL & INL
• Measuring DNL & INL– Servo-loop– Code density testing
• Spectral testing
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 2
Lecture 13Administrative
• Midterm date change:– Since homeworks for lecture 1 to 14
would not be done and returned and solution posted by Oct. 24th one week shift
– New midterm date: Tues. Oct. 31st
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 3
Summary Last Lecture– Data converters
• ADC & DAC transfer curve• Frequency/time domain effects:
– Sampling– Aliasing– Reconstruction
• Amplitude quantization– Quantization error (noise)
• Static converter error sources– Offset & full-scale error– DNL & INL
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 4
Converter Offset ErrorADC DAC
Ref: “Understanding Data Converters,” Texas Instruments Application Report SLAA013, Mixed-Signal Products, 1995.
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 5
Converter Full Scale ErrorADC DAC
Actual full scale point
Ideal full scale point Ideal full scale
point
Full scale error
Actual full scale
point
Full scale error
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 6
Offset and Full Scale Errors
• Alternative specification in % Full Scale = 100% * (# of LSB value)/ 2N
• Gain error can be extracted from offset & full scale error
• Non-trivial to build a converter with extremely good gain/offset specs
• Typically gain/offset is most easily compensated by the digital pre/post-processor
• More interesting: Linearity measures DNL, INL
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 7
Offset and Full-Scale Error
-1 0 1 2 3 4 5 6 7 8
0
1
2
3
4
5
6
7
Dig
ital O
utpu
t Cod
e
ADC Input Voltage [LSB]
ADC characteristicsideal converter
Offset error
Full-scale error
Note:For further measurements (DNL, INL) connecting the endpoints & deriving ideal codes based on the non-ideal endpoints eliminates offset and full-scale error
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 8
-1 0 1 2 3 4 5 6 7 8 9
0
1
2
3
4
5
6
7
8ADC characteristicsideal converter
ADC Differential Nonlinearity
DNL = deviation of code width from
Δ (1LSB)
+0.4 LSB DNL error
-0.4 LSB DNL error
Endpoints connectedIdeal characteristics derived DNL measured
0 LSB DNL error
Dig
ital O
utpu
t Cod
e
ADC Input Voltage [Δ]
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 9
ADC Differential Nonlinearity
• Ideal ADC transition points equally spaced by 1LSB
• For DNL measurement, offset and full-scale error is eliminated
• DNL [k] (a vector) measures the deviation of each code from its ideal width
• Typically, worst-case DNL is reported
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 10
ExampleCompute Offset, Full Scale & Gain Error, & DNL
A 3bit ADC is designed to have an ideal LSB=0.1V
The measured transitions levels for the end product is shown in the table, compute offset, full scale, gain error, & DNL
1- Offset: (real transition-ideal)=-0.03V, -0.03/0.1LSB Offset=-0.3LSB
2- Full-scale error (real last transition-ideal)= 0.68-0.65=0.03V in LSB 0.03/0.1
Full-scale error= +0.3LSB
3-Gain error: Average code width (LSB size)LSB=(Last transition-first transition)/(2N-2)
LSB=(0.68-0.02)/6LSB= 0.11V
0.680.657
0.50.556
0.420.455
0.370.354
0.20.253
0.170.152
0.020.051
Real transition point [V]
Ideal transition point [V]
Transition #
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 11
ADC Differential NonlinearityExample
VFS=2Nx0.11V=0.88V4-Gain relative to ideal:
Gain=0.8/0.88=0.91
5- Find DNL:-Find all code widths:Width[k]=Transition[k+1]-
Transition[k]
- Divide code width by LSBDNL[k]=Width[k]-1
--0
--7
0.640.18/0.11=1.646
-0.270.08/0.11=0.735
-0.550.05/0.11=0.454
0.550.17/0.11=1.553
-0.730.03/0.11=0.272
0.360.15V/0.11V=1.361
DNL[LSB]
Code Width [LSB]
Code #
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 12
ADC Differential NonlinearityExample
-0
-7
0.646
-0.275
-0.554
0.553
-0.732
0.361
DNL[LSB]
Code #
Code #
DN
L [L
SB
}
0 1 2 3 4 5 6 7
1
0.5
0
-0.5
-1
Max.DNL
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 13
-1 0 1 2 3 4 5 6 7 8 9
0
1
2
3
4
5
6
7
8ADC characteristicsideal converter
ADC Differential NonlinearityExamples
-1 0 1 2 3 4 5 6 7 8 9
0
1
2
3
4
5
6
7
8ADC characteristicsideal converter
Non-monotonic(> 1 LSB DNL)
Missing code(+0.5/-1 LSB DNL)
Dig
ital O
utpu
t Cod
eADC Input Voltage [Δ]
Dig
ital O
utpu
t Cod
e
ADC Input Voltage [Δ]
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 14
ADC DNL• DNL=-1 implies missing code• For an ADC DNL < -1 not possible undefined• Can show:
• For a DAC DNL < -1 possible
al l iDNL[i] 0=∑
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 15
DAC Differential Nonlinearity
• To find DNL for DAC– Draw end-point line from 1st point to last– Find ideal LSB size– Compute segment sizes:
segment [m]=V[m]-V[m-1]
• Unlike ADC DNL, for a DAC DNL can be < -1LSB
segment[ m] V [ LSB]DNL[ m]
V [ LSB]
−=
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 16
DAC Differential Nonlinearity
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 17
Impact of DNL on Performance
• Same as a somewhat larger quantization error, consequently degrades SQNR
• How much – later in the course...• People sometimes speak of "DNL noise",
i.e. "additional quantization noise due to DNL"
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 18
ADC Integral Nonlinearity
• Straight line through the endpoints is usually used as reference,i.e. offset and full scale errors are eliminated in INL calculation
• Ideal converter steps found for the endpoint line
Difference between real & ideal transition points is INL -1 0 1 2 3 4 5 6 7 8
0
1
6
7
Dig
ital O
utpu
t Cod
e
ADC Input Voltage [Δ]
INL = deviation of codetransition from its ideal location
-1 LSB INL
2
3
4
5
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 19
ADC Transfer Curve
IdealReal
INL Curve
INLINLMax
INLMax
Input
OutputINL = deviation of codetransition from its ideal location
ADC Integral NonlinearityINL
• Most common End-point:
• INL is also a vector INL[k]If one INL # is reported then:
Worst case INL
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 20
ADC Transfer Function
IdealReal
INL Curve
INL
Input
OutputINL = deviation of code transition from its ideal location
ADC Integral NonlinearityBest-Fit
Best-FitA best-fit line (in the least-mean squared sense) fitted to the data
Ideal converter steps found then INL is measured
Note: Typically INL smaller for best-fit compared to end-point
ADC Transfer Curve
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 21
ADC Integral NonlinearityBest-Fit versus End-Point
• Best-Fit–A best-fit line (in the
least-mean squared sense)
– Ideal converter steps is found then INL is measured
-1 0 1 2 3 4 5 6 7 8
0
1
6
7
Dig
ital O
utpu
t Cod
e
ADC Input Voltage [Δ]
-1/2 LSB INL
2
3
4
5
+1/2 LSB INL
Best Fit
End-point INLmax =1LSBBest-fit INLmax =+-1/2LSB
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 22
ADC Integral Nonlinearity
m
i 1INL[ m] DNL[i]
==∑
Can derive INL by:1-
• Construct uniform staircase between 1st and last transition• INL for each code:
2-• Can show
INL is found by computing the cumulative sum of DNL
T[m] T[ideal ]INL[ m]
Step _Width[ideal ]−
=
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 23
ADC Differential & Integral NonlinearityExample
--0
--7
00.646
-0.64.-0.275
-0.37-0.554
0.180.553
-0.37-0.732
0.360.361
INL[LSB]
DNL[LSB]
Code #
Notice:INL(0) undefinedINL (2N-2) =0
m
i 1INL[ m] DNL[i]
==∑
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 24
ADC Differential & Integral NonlinearityExample
Code #
DN
L [L
SB
]
0 1 2 3 4 5 6 7
1
0.5
0
-0.5
-1
INL
[LS
B]
0 1 2 3 4 5 6 7
1
0.5
0
-0.5
-1
Max.DNL
Max.INL
--0
--7
00.646
-0.64-0.275
-0.37-0.554
0.180.553
-0.37-0.732
0.360.361
INL[LSB]
DNL[LSB]
Code #
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 25
DAC Integral Nonlinearity
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 26
DAC DNL and INL
* Ref: “Understanding Data Converters,” Texas Instruments Application Report SLAA013, Mixed-Signal Products, 1995.
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 27
Example: INL & DNL
Large INL & Small DNL Large DNL & Small INL
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 28
DAC Monotonicity• Monotonic if transfer curve slope always positive• Monotonicity guaranteed if
| INL | ≤ 0.5 LSB
• This implies| DNL | ≤ 1 LSB
• Note: Sufficient (but not necessary) condition
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 29
Non-Monotonic DACExample
000 001 010 011 100 101 110 111
DigitalInput
Analog Output [LSB]
7
6
5
4
3
2
1
0
segment[ m] V [ LSB]DNL[ m]
V [ LSB]
segment[4] V [ LSB]
DNL[4]V [ LSB]
0.5 11.5[ LSB]
12.5 1
DNL[5] 1.5[ LSB]1
−=
−
=
− −= = −
−== =
• DNL< -1LSB for a DACNon-monotonicity
• Question: When can non-monotonicity cause major problems?
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 30
Non-Monotonic ADCExample
• Code 011 associated with two transition levels !
• For non-monotonic ADC
DNL not defined @ non-monotonic steps
111
110
101
100
011
010
001
000
Digital Output
Analog input
0 Δ 2Δ 3Δ 4Δ 5Δ 6Δ 7Δ
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 31
How to measure DNL/INL?• DAC:
– Apply digital codes and use a good voltmeter to measure output
• ADC– Not as simple as DAC need to find "decision
levels", i.e. input voltages at all code boundaries• One way: Adjust voltage source to find exact code trip
points "code boundary servo"• More versatile: Histogram testing
Apply a signal with known distibution Analyze digital code distribution at ADC outputBack calculate DNL/INL
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 32
Code Boundary Servo
C1
ADCInputR2
C2
ADCUnder
Test
VREF
i1
i2
DigitalComp.
A<B
BA≥B
A
InputDigitalCode
ADCOutput
fS
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 33
Code Boundary Servo
AD
C D
igita
l Out
put
ADC Analog Input
111
110
101
100
011
010
001
000
Δ 2Δ 3Δ 4Δ 5Δ 6Δ 7Δ
• i1 and i2 are small, and C1 is large, so the ADC analog input moves a small fraction of an LSB each sampling period
• For a code input of 101, the ADC analog input settles to the code boundary shown
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 34
Code Boundary ServoGood DVM
C1
R2
C2
ADC
VREF
i1
i2
DigitalComp.
A<B
BA≥B
A
InputDigitalCode
ADCOutput
fS
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 35
Code Boundary Servo• A very good digital voltmeter (DVM)
measures the analog input voltage corresponding to the desired code boundary
• DVMs have some interesting properties– They can have very high resolutions (8½ decimal
digit meters are inexpensive)– To achieve stable readings, DVMs average
voltage measurements over multiple 60Hz ac line cycles to filter out pickup in the measurement loop
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 36
Code Boundary ServoIssues
• ADCs of all kinds are notorious for kicking back high-frequency, signal-dependent glitches to their analog inputs
• A magnified view of an analog input glitch follows …
Good DVM
R2
C2
ADC
VREF fS
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 37
Code Boundary Servo
• Just before the input is sampled and conversion starts, the analog input is pretty quiet
• As the converter begins to quantize the signal, it kicks back charge
time0 1/fS
anal
og in
put
start of conversion
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 38
Code Boundary Servo
• The difference between what the ADC measures and what the DVM measures is not ADC INL, it’s error in the INL measurement
• How do we control this error?
time0 1/fS
anal
og in
put
ADC converts this voltage
DVM measures the averageinput including the glitch
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 39
Code Boundary Servo
• A large C2 fixes this
• At the expense of longer measurement time
Good DVM
R2
C2
ADC
VREF fS
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 40
Histogram Testing
• Code boundary measurements are slow– Long testing time– May miss dynamic errors
• Histogram testing– Quantize input with known pdf (e.g. ramp or
sinusoid)– Measure output pdf– Derive INL and DNL from deviation of measured
pdf from expected result
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 41
Histogram Test Setup
Ramp
0
VFS
ADC PC
VFS
• Slow (wrt conversion time) linear ramp applied to ADC• DNL derived directly from total number of occurrences of each
code @ the output of the ADC
Time
fS
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 42
A/D Histogram Test Using Ramp SignalDigital Output
Analog input
Ramp
Time
nTs
ADCInput/Output
Example:Ramp slope: 10μV/μsec1LSB =10mVEach ADC code 1msec
fs =100kHz Ts=10μsec
n =1msec/10μsecn=100 samples/code
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 43
A/D Histogram Test Using Ramp Signal
Dig
ital O
utpu
t
Analog input
Ramp
Tim
e
nTs
ADCInput/Output
# of
Sam
ples
Per c
ode
Example:Ramp slope: 10μV/μsec1LSB =10mVEach ADC code 1msec
fs =100kHz Ts=10μsec
n =1msec/10μsecn=100 samples/code
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 44
Measuring DNL Error
• Ramp speed is adjusted to provide large number of output/code – e.g. an average of 100 outputs of each ADC code (for ~1/100 LSB resolution)
• Ramps can be quite slow for high resolution ADCs:• Example:
16bit ADC & 100conversion/code @100kHz sampling rate:
(65536 codes)(100 conversions/code)100000 conversions/sec
= 65.6 sec
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 45
Ramp Histogram Ideal 3-Bit ADC
-1 0 1 2 3 4 5 6 7 8
0
1
2
3
4
5
6
7
Dig
ital O
utpu
t Cod
e
A/D Characteristics [1]
ADC Input Voltage [1/Δ]
ADC characteristicsideal converter
0 1 2 3 4 5 6 70
20
40
60
80
100
120
140
160
180
200
ADC output codeC
ount
sADC Output Code
0 1 2 3 4 5 6 7ADC Input [Δ]
0 1 2 3 4 5 6 7
7
6
5
4
3
2
1
0
Dig
ital O
utpu
t Cod
e
200
160
120
80
40
0C
ode
Cou
nt
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 46
Ramp HistogramExample: 3-Bit Non-Ideal ADC
-1 0 1 2 3 4 5 6 7 8
0
1
2
3
4
5
6
7
Dig
ital O
utpu
t Cod
e
A/D Characteristics [3]
ADC Input Voltage [1/Δ]
ADC characteristicsideal converter
+0.4 LSB DNL
-0.4 LSB DNL
+0.4 LSB INL
0 1 2 3 4 5 6 70
20
40
60
80
100
120
140
160
180
200
ADC output code
Cou
nts
ADC Output Code0 1 2 3 4 5 6 7
ADC Input [Δ]0 1 2 3 4 5 6 7
7
6
5
4
3
2
1
0
Dig
ital O
utpu
t Cod
e
200
160
120
80
40
0
Cod
e C
ount
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 47
Example: 3-Bit Non-Ideal ADC DNL Extraction from Histogram
1. “Over-range bins”removed (0 and full-scale)
2. Compute average count/bin (100 in this case)
0 1 2 3 4 5 6 70
20
40
60
80
100
120
140
ADC output codeC
ount
s, E
nd b
ins
rem
oved
ADC Output Code0 1 2 3 4 5 6 7
140
120
100
80
60
40
20
0C
ode
Cou
nt
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 48
Example: 3-Bit Non-Ideal ADC DNL Extraction from Histogram
Normalize
3- Divide by average count/bin (ideal bins have exactly the average count, which, after normalization 1
0 1 2 3 4 5 6 70
20
40
60
80
100
120
140
ADC output code
Cou
nts,
End
bin
s re
mov
ed
ADC Output Code0 1 2 3 4 5 6 7
1.4
1.2
1
0.8
0.6
0.4
0.2
0
Nor
mal
ized
Cod
e C
ount
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 49
4- Subtract 1 from the normalized code count
5- Result is DNL (+-0.4LSB in this case)
0 1 2 3 4 5 6 7-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
ADC output codeD
NL
= C
ount
s / M
ean(
Cou
nts)
ADC Output Code0 1 2 3 4 5 6 7
0.4
0.2
0
-0.2
-0.4D
NL=
Cou
nts/
Mea
n (c
ount
s)
Example: 3-Bit Non-Ideal ADC DNL Extraction from Histogram
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 50
• DNL Histogram used to reconstruct the exact converter characteristics (having measured only the histogram)
• Width of all codes derived from measured DNL (Code=DNL + 1LSB)
• INL is then found (deviation from a straight line through the end points) or cumsumor DNLs -1 0 1 2 3 4 5 6 7 8
0
1
2
3
4
5
6
7
ADC Input Voltage
Rec
onst
ruct
ed C
hara
cter
istic
ADC Input Voltage [Δ]0 1 2 3 4 5 6 7
7
6
5
4
3
2
1
0
Rec
onst
ruct
ed O
utpu
t
Example: 3-Bit Non-Ideal ADC Static Characteristics Extracted from Histogram
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 51
Example: 3-Bit Non-Ideal ADC DNL and INL Extracted from Histogram Testing
1 2 3 4 5 6-1
-0.5
0
0.5
1
bin #
DN
L [L
SB]
1 2 3 4 5 6
-1-0.5
0
0.5
1
INL
[LS
B]
3-Bit converter DNL & INLfrom histogram testing
bin #-1 0 1 2 3 4 5 6 7 8
0
1
2
3
4
5
6
7
ADC characteristicsideal converter
+0.4 LSB DNL
-0.4 LSB DNL
+0.4 LSB INL
Dig
ital O
utpu
t Cod
e
ADC Input Voltage [Δ]
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 52
A/D Histogram Test Using Sinusoidal Signals
Sinusoid
At sinusoid midpoint crossings:dv/dt max.
least # of samples
At sinusoid amplitude peaks:dv/dt min.
highest # of samples
n1< n2
ADCInput/Output
Dig
ital O
utpu
t
Analog input
Tim
e
# of
Sam
ples
Per c
ode
n1Ts
n2Ts
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 53
Sinusoidal Inputs• Linear ramp generators not
readily available
• Sinusoidal generators more common
• Solution: use sinusoidal test signal
• Problem: ideal histogram is not flat but has “bath-tub shape”
• Need to correct for the shape0 1000 2000 3000 40000
50
100
150
200
250
Raw Histogram Data for a 12-Bit ADC
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 54
Example: DNL and INLExtracted from Sinusoidal Histogram Testing
0 500 1000 1500 2000 2500 3000 3500 4000-1
0
1
code
DN
L [L
SB]
DNL = +1.3 / -1 LSB, missing code if (DNL<-0.9)
0 500 1000 1500 2000 2500 3000 3500 4000-1
0
1
2
code
INL
[LSB
]
INL = +1.7 / -0.69 LSB
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 55
Correction for Sinusoidal PDF• References:
– [1] M. V. Bossche, J. Schoukens, and J. Renneboog, “Dynamic Testing and Diagnostics of A/D Converters,” IEEE Transactions on Circuits and Systems, vol. CAS-33, no. 8, Aug. 1986.
– [2] IEEE Standard 1057
• Is it necessary to know the exact amplitude and offset of sinusoidal input? No!
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 56
DNL/INL Code
function [dnl,inl] = dnl_inl_sin(y);
%DNL_INL_SIN
% dnl and inl ADC output
% input y contains the ADC output
% vector obtained from quantizing a
% sinusoid
% Boris Murmann, Aug 2002
% Bernhard Boser, Sept 2002
% histogram boundaries
minbin=min(y);
maxbin=max(y);
% histogram
h = hist(y, minbin:maxbin);
% cumulative histogram
ch = cumsum(h);
% transition levels
T = -cos(pi*ch/sum(h));
% linearized histogram
hlin = T(2:end) - T(1:end-1);
% truncate at least first and last
% bin, more if input did not clip ADC
trunc=2;
hlin_trunc = hlin(1+trunc:end-trunc);
% calculate lsb size and dnl
lsb= sum(hlin_trunc) / (length(hlin_trunc));
dnl= [0 hlin_trunc/lsb-1];
misscodes = length(find(dnl<-0.9));
% calculate inl
inl= cumsum(dnl);
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 57
DNL/INL Code Test
% converter model
B = 6; % bits
range = 2^(B-1) - 1;
% thresholds (ideal converter)
th = -range:range; % ideal thresholds
th(20) = th(20)+0.7; % error
fs = 1e6;
fx = 494e3 + pi; % try fs/10!
C = round(100 * 2^B / (fs / fx));
t = 0:1/fs:C/fx;
x = (range+1) * sin(2*pi*fx.*t);
y = adc(x, th) - 2^(B-1);
hist(y, min(y):max(y));
dnl_inl_sin(y);
-30 -20 -10 0 10 20 30-1
-0.5
0
0.5
1
codeD
NL
[LSB
]
DNL = +0.7 / -0.7 LSB, 0 missing codes (DNL<-0.9)
-30 -20 -10 0 10 20 30-0.20
0.20.40.60.8
INL
[LSB
]
INL = +0.7 / -0.0 LSB
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 58
Histogram Testing Limitations• The histogram (as any ADC test, of course) characterizes one
particular converter. Test many devices to get valid statistics.• Histogram testing assumes monotonicity
E.g. “code flips” will not be detected.• Dynamic sparkle codes produce only minor DNL/INL errors
E.g. 123, 123, …, 123, 0, 124, 124, … look at ADC output to detect
• Noise not detected E.g. 9, 9, 9, 10, 9, 9, 9, 10, 9, 10, 10, 10, …
Ref: B. Ginetti and P. Jespers, “Reliability of Code Density Test for High Resolution ADCs,” Electron. Lett., vol. 27, pp. 2231-3, Nov. 1991.
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 59
Example: Hiding Problems in the Noise
• INL 5 missing codes
• DNL "smeared out" by noise!
• Always look at both DNL/INL
• INL usually does not lie...
[Source: David Robertson, Analog Devices]
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 60
Why Additional Tests/Metrics?
• Static testing does not reveal all converter non-idealities
• Frequency dependence (fs and fin) ?– In principle we can vary fs and fin when performing histogram tests– Result of such sweeps is usually not very useful– Hard to separate error sources, ambiguity– Typically we use fs=fs
NOM and fin << fs /2 for histogram tests
• Frequency domain performance measurements Spectral testing– Apply one or more sinusoid waveforms at the input– Measure signal at the output, any other frequency components
other than the input add to non-idealities– Note that frequency domain non-idealities are a function of both
static (DNL, INL) and dynamic errors
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 61
DAC Lab Testingor Simulation
• Input sinusoid Need to have better purity compared to DAC linearity
• Spectrum analyzer need to have better linearity than DUT
VoutDAC SpectrumAnalyzer
SinusoidSignal
Generator
ClockGenerator
Device Under Test (DUT)Digital
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 62
Direct ADC-DAC Test
• Need DAC with much better performance compared to ADC under test
• Actually a good way to "get started"...
ADCVin Vout
DACSpecrumAnalyzer
SignalGenerator
ClockGenerator
Device Under Test (DUT)
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 63
DFT Test
ADCVin PCSignal
Generator
ClockGenerator
Device Under Test (DUT)
DataAcquisition
System
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 64
Analyzing ADC Output Signalvia DFT
• An ideal, infinite resolution ADC would preserve ideal, single tone spectrum
• Deviations reveal ADC non-idealities
⇒x(t) x(k)
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 65
Discrete Fourier TransformThe DFT of a block of N time samples
{x(k)} = {x(0), x(1), x(2),…,x(N-1)}
yields a set of N frequency bins
{Am} = {A0,A1,A2,…,AN-1}
where:
Am = Σn=0
N-1xn WN
mnm = 0,1,2,…,N-1
WN ≡ e-j2π/N
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 66
Discrete Fourier Transform (DFT) Properties
• DFT of N samples spaced Ts=1/fs seconds:– N frequency bins– Bin m represents frequencies at m * fs/N [Hz]
• DFT frequency resolution:– Proportional to fs/N in [Hz/bin]
• DFT with N=2p where p is an integer can be found using a computationally more efficient algorithm named:– FFT Fast Fourier Transform
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 67
DFT Magnitude Plots
• Because Am magnitudes are symmetric around fS/2, it is redundant to plot ⏐Am⏐’s for m >N/2
• Usually magnitudes are plotted on a log scale normalized so that a full scale sinewave of rms value aFS yields a peak bin of 0dBFS:
⏐Am⏐ (dBFS) = 20 log10⏐Am⏐
aFS N/2
0 fs/2 fs
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 68
Matlab ExampleNormalized DFT
fs = 1e6;
fx = 50e3;
Afs = 1;
N = 100;
% time vector
t = linspace(0, (N-1)/fs, N);
% input signal
y = Afs * cos(2*pi*fx*t);
% spectrum
s = 20 * log10(abs(fft(y)/N/Afs*2));
% drop redundant half
s = s(1:N/2);
% frequency vector (normalized to fs)
f = (0:length(s)-1) / N;
0 0.2 0.4 0.6 0.8 1x 10
-4-1
-0.5
0
0.5
1
Time
Ampl
itude
0 0.1 0.2 0.3 0.4 0.5
-300
-200
-100
0
Frequency [ f / fs]
Mag
nitu
de [
dB
FS ]
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 69
“Another” Example …
This does not look like the spectrum of a sinusoid …
0 1 2 3 4 5
x 10-5
-1
-0.5
0
0.5
1
Time
Sign
al A
mpl
itude
0 0.1 0.2 0.3 0.4 0.5-50
-40
-30
-20
-10
Frequency [ f / fs ]
Ampl
itude
[ d
BFS
]
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 70
DFT Periodicity• The DFT implicitly assumes that
time sample blocks repeat every N samples
• With a non-integer number of periods within the observation window, the input yields significant amplitude/phase discontinuity at the block boundary
• This energy spreads into all frequency bins as “spectral leakage”
• Spectral leakage can be eliminated by either
– An integer number of sinusoids in each block
– Windowing
0 0.2 0.4 0.6 0.8 1 1.2 1.4
x 10-4
-1
-0.5
0
0.5
1
Time
Sig
nal A
mpl
itude
0 0.2 0.4 0.6 0.8 1 1.2 1.4
x 10-4
-1
-0.5
0
0.5
1
Time
Sig
nal A
mpl
itude
Actual Signal
DFT Perceived Signal
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 71
Spectra
0 0.1 0.2 0.3 0.4 0.5-60
-50
-40
-30
-20
-10
Frequency [ f / fs ]
Am
plitu
de [
dB
FS ]
0 0.2 0.4 0.6 0.8 1 1.2 1.4x 10
-4
-1
-0.5
0
0.5
1
Time
Sig
nal A
mpl
itude
0 0.2 0.4 0.6 0.8 1 1.2 1.4
x 10-4
-1
-0.5
0
0.5
1
Time
Sig
nal A
mpl
itude
0 0.1 0.2 0.3 0.4 0.5-400
-300
-200
-100
0
Frequency [ f / fs ]
Am
plitu
de [
dB
FS ]
Integer number of cycles Non-integer number of cycles
EECS 247 Lecture 13: Data Converters © 2006 H. K. Page 72
Choice of Number of Cycles & Number of Samples
To overcome frequency spectrum leakage problem:
– Number of Cycles integer
– N/cycles = fs / fxnon-integer
– Preferable to have N power of 2
(FFT instead of DFT)
N/cycles = fs / fx=6 integer
-1
-0.5
0
0.5
1
Sig
nal A
mpl
itude
-1
-0.5
0
0.5
1
Sig
nal A
mpl
itude
N/cycles = fs / fx=5.55 non-integer
Time
Time