EE Electronics Circuit Design Digital Logic Gates 14.2nMOS Logic Families 14.3Dynamic MOS Logic Families 14.4CMOS Logic Families 14.5TTL Logic Families 14.6ECL Logic Families 14. Introduction to Digital Logic Families EE Electronics Circuit Design Digital Logic Gates Basic logic gates are summarized below. Note that logic circuits are represented in the forms :-Basic logic gates are summarized below. Note that logic circuits are represented in the forms :- 1.Logic Symbol1.Logic Symbol 2.Logic Equation2.Logic Equation 3.Truth Table3.Truth Table 4.Timing Diagram4.Timing Diagram EE Electronics Circuit Design 3 EE Electronics Circuit Design 4 EE Electronics Circuit Design 5 EE Electronics Circuit Design nMOS and pMOS, how they works nMOS will conduct or Q n (on) when V GS > 0 (high) pMOS will open or Q p (off) when V GS 0 (zero or positive) nMOS will open or Q n (off) when V GS 0 (zero or negative) pMOS will conduct or Q p (on) when V GS 0 (negative) 14.2nMOS Logic Families EE Electronics Circuit Design 7 nMOS NOR gate nMOS NOR gate, how it works EE Electronics Circuit Design Example: Draw nMOS Inverter gate and show how it works EE Electronics Circuit Design Example: Draw nMOS OR gate and show how it works EE Electronics Circuit Design nMOS NAND gate, how it works EE Electronics Circuit Design 14.3Dynamic MOS Logic Families When power consumption and physical size are prime design consideration, as in digital watches and calculators, Dynamic MOS logic is the one to meet those requirements. Power consumption is minimized by relying on the inherent capacitance of MOS transistors to store logic levels (to remain charged or discharged) and by using clock signals to turn on transistors for very brief interval of time only. nMOS gate with Substrate grounded, is a fundamental component of Dynamic logic circuits. It is completely symmetrical Drain and Source terminals are indistinguishable. Current can flow in either direction through the device. They can be named terminal 1 and 2 and C 1 and C 2 are the capacitance at each terminal. EE Electronics Circuit Design * When G is low nMOS will be off and no current will pass through it * When G is high nMOS will be on and Hi will pass through it to Lo capacitor Dynamic MOS, how it works EE Electronics Circuit Design 13 Dynamic MOS Inverter, how it works You have to use 2 clocks to invert 1 to You have to use 2 clocks to invert 0 to 1 Whenever Gate of nMOS is 1(>0) Q n will conduct (=on) Then transfer of charge Lo or Hi from one terminal to other terminal will take place Whenever Gate of nMOS is 0 (=0) Q n will open (=off) There will be no transfer of Lo or Hi from one terminal to the other Whenever 2 = 1 C 1 and C 2 will transfer Hi from one another Whenever 1 = 1 C 1 will be invert of V in EE Electronics Circuit Design 14 Dynamic MOS - NOR, how it works EE Electronics Circuit Design 15 Dynamic MOS - NAND, how it works EE Electronics Circuit Design 16 HW on Dynamic MOS 1(a)Dynamic MOS circuit shown below, what are the logic obtained at points K,L,M and Output after 1 and after 2 ? Fill up the logics (1 or 0) in the following table. (b)What is the overall logic that can perform by this given circuit? (c)Draw equivalent switching circuit and logic symbol of this circuit. ABK after 1 L after 2 M after 1 Output After EE Electronics Circuit Design 14.4CMOS Logic Families nMOS has disadvantage having delay when switch on and off due to one upper nMOS acting as resistive load when output changing from Lo to Hi and also lower nMOS acting as small R when output changing from Hi to Lo. See below. nMOS Inverter produce delay at the output EE Electronics Circuit Design CMOS has no or little delay when switch on and off due to one upper pMOS acting as switch when output changing from Lo to Hi and also lower nMOS acting as switch when output changing from Hi to Lo. See below. CMOS Inverter produce no significant delay at the output due to switching property of both MOSFET EE Electronics Circuit Design 19 CMOS - Inverter, how it works Whenever A is 0 V GS of Q p < 0 (Q p =on) and V GS of Q n =0 (Q n =off) then Output=V DD Whenever A is 1 V GS of Q p = 0 (Q p =off) and V GS of Q n > 0 (Q n =on) then Output=0 EE Electronics Circuit Design 20 CMOS NAND gate, how it works Q n is in series and Q p is in parallel = NAND Gate of Q n > 0 (Q n =on) Gate of Q n = 0 (Q n =off) Gate of Q p = 0 (Q p =on) Gate of Q p > 0 (Q p =off) When 1 present at both Input, Output will be 0When zero is present at any Input, Output will be 1 EE Electronics Circuit Design 21 CMOS NOR gate, how it works Q n is in Parallel and Q p is in series = NOR Gate of Q n > 0 (Q n =on) Gate of Q n = 0 (Q n =off) Gate of Q p = 0 (Q p =on) Gate of Q p > 0 (Q p =off) When 1 present at any Input, Output will be 0When 0 present at both Input, Output will be 1 EE Electronics Circuit Design TTL Logic Families 1. A = 1 (high = 5V) then (V BE1 = 0) 2. Q 1 opens 4. Q 2 conducts and produces = I C2 R C2 drop 1. A = low = 0V then (V BE1 = 0.7V) 2. Q 1 conducts 3. I B2 flows out of Q 2 4. Q 2 opens then I C2 R C2 no drop 5. Y = 1 (high= 5V) Transistor Transistor Logic (TTL) TTL Inverter gate, how it works 6. A = 0 is inverted to Y = 1 3. But PN junction current from Base to Collector of Q 1 (I D1 = I B2 flows) 5. If R C2 is chosen so that I C2 R C2 drop = 5V then Y=0 6. A = 1 is inverted to Y = 0 Advantage of TTL logic circuit is that input current is zero at high (5V) input and it is reverse at low (0V) input. Because of this many TTL gates can be fan-out to output of one gate. AQ1Q1 Q2Q2 Y 0 (0V)onoff1 (5V) offon0 (0V) EE Electronics Circuit Design AQ1Q1 Q2Q2 Q3Q3 Y 0 (0V)onoff F (Float) 1 (5V)offon 0 (0V) TTL Inverter gate (open Collector), how it works AQ1Q1 Q2Q2 Q3Q3 Y 0 (0V)onoff 1 (5V) offon 0 (0V) EE Electronics Circuit Design TTL NAND gate (open Collector), how it works ABQ1Q1 Q2Q2 Q3Q3 Y 00onoff 1 (5V) 01onoff 1 (5V) 10onoff 1 (5V) 11offon 0 (0V) EE Electronics Circuit Design TTL NAND Totem pole gate, how it works ABQ1Q1 Q2Q2 Q3Q3 Q4Q4 Y 00onoff on1 (5V) 01onoff on1 (5V) 10onoff on1 (5V) 11offon off0 (0V) This gate works faster because of Q 4 When it is on has no resistive delay. Q 4 Acts as a switch (no delay) Diode at the Emitter of Q 4 When it is on has an extra drop of 0.7V so that Base of Q 4 is 1.4V higher than Y which will secure Q 4 not to conduct when Q 3 is on EE Electronics Circuit Design TTL OR gate, how it works ABQ1Q1 Q2Q2 Q3Q3 Q4Q4 Q5Q5 Q6Q6 Q7Q7 Q8Q8 Y 00on off onoffon0 (0V) 01onoff on offonoff1 (5V) 10offon offonoffonoff1 (5V) 11off on offonoff1 (5V) EE Electronics Circuit Design A to Q 7 Emitter and B to Q 7 Base are both inverters 5. Q 9 base to output Y is inverter therefore Y = 0 6. If Y = 0 when two inputs A and B are equal it is (EX-OR LOGIC) TTL EXOR gate, how it works 2. If A and B are both 1 or 0, Q 7 Emitter and Q 7 Base will be both 0 or 1 3. When Q 7 Emitter and Q 7 Base are both 0 or 1, V BE (Q 7 ) = 0 making Q 7 off. 4. When Q 7 off, Q 8 also off. making Q 9 Base High = 1, 7. But when A=1 and B=0, Q 7 Emitter=0 and Base=1 making Q 7 to conduct and then Q 8 to conduct. Then Q 9 Base Low = 1, and Y=1 8. But when A=0 and B=1, Q 7 Emitter=1 and Base=0 making Q 7 to off but then Q 8 to conduct. Then Q 9 Base Low = 1, and Y=1 EE Electronics Circuit Design 28 Type NumberDescription 7400Quad 2-input NAND 7401Quad 2-input NAND open collector 7402Quad 2-input NOR 7403Quad 2-input NOR, open collector 7404Hex inverter 7405Hex inverter, open collector 7406Hex inverter, open collector to 30 (V) 7407Hex buffer/driver, open collector to 30 (V) 7408Quad 2-input AND 7409Quad 2-input AND, open collector 7410Triple 3-input NAND 7411Triple 3-input AND 7414Hex Schmitt-tngger inverters 7420Dual 4-input NAND 7421Dual 4-input AND 7427Triple 3-input NOR input NAND 7432Quad 2-input OR 7486Quad 2-input XOR TTL Device Listings EE Electronics Circuit Design ECL Logic Families The Emitter Coupled Logic (ECL) family operates at the highest speed of all of the logic families studied in this text.The Emitter Coupled Logic (ECL) family operates at the highest speed of all of the logic families studied in this text. This happens because none of the transistors are operated in saturation.This happens because none of the transistors are operated in saturation. Since propagation delays of 1 to 2 ns are achievable, ECL is useful in highspeed applications such as radar signal processors, computers, and data transmission.Since propagation delays of 1 to 2 ns are achievable, ECL is useful in highspeed applications such as radar signal processors, computers, and data transmission. There are fewer chips in the ECL family than in TTLThere are fewer chips in the ECL family than in TTL When one source voltage is larger than the other, the transistor associated with that higher voltage will be ON and the other transistor will be OFFWhen one source voltage is larger than the other, the transistor associated with that higher voltage will be ON and the other transistor will be OFF Differential Amplifier ON transistor will have low collector voltage and the OFF transistor will have high collector voltageON transistor will have low collector voltage and the OFF transistor will have high collector voltage Therefore output voltage of the BJT with larger input source will have smaller value which is INVERTER LOGICTherefore output voltage of the BJT with larger input source will have smaller value which is INVERTER LOGIC But output voltage at the collector of the other BJT will have larger value in which case is BUFFER LOGICBut output voltage at the collector of the other BJT will have larger value in which case is BUFFER LOGIC EE Electronics Circuit Design 30 The differential amplifier with input voltages are as follows: The differential amplifier with input voltages are as follows: Input voltage source voltage is applied to one of the transistor and the other transistor input voltage is a fixed internally generated reference voltage of (-1.3V)Input voltage source voltage is applied to one of the transistor and the other transistor input voltage is a fixed internally generated reference voltage of (-1.3V) Collector of the input BJT is the Inverter output and the collector of the other BJT is the Buffer output Collector of the input BJT is the Inverter output and the collector of the other BJT is the Buffer output Emitter Coupled Logic Logic level of the ECL is (-0.9V) for logic highLogic level of the ECL is (-0.9V) for logic high Logic level of the ECL is (-1.7V) for logic lowLogic level of the ECL is (-1.7V) for logic low EE Electronics Circuit Design 31 When Input logic is high ( -0.9V) 2. -V cc = -5.2V at point X 3. When V B1 = -0.9V (high) 5. But V B2X = -1.3-(-5.2) = 3.9V 6. V B1 > V B2 then Q 1 will be ON making V BE1 =0.8V 10. Q 1 will be ON & V C1 is low = Inverter Output due to drop at R 1 7. V R3 = =3.5V 8. Therefore V BE2 = =0.4V (cutoff Q 2 V BE < 0.5V) 9. Q 2 will be OFF = V C2 is high = Buffer Output 1. V B1 = -1.3V reference 4. V B1X = -0.9-(-5.2) = 4.3V EE Electronics Circuit Design 32 When Input logic is low ( -1.7V) 2. -V cc = -5.2V at point X 3. When V B1 = -1.7V (low) 5. But V B2X = -1.3-(-5.2) = 3.9V 6. V B1 < V B2 then Q 2 will be ON making V BE2 =0.8V 10. V C2 is low due to drop at R 2 7. V R3 = =3.1V 8. Therefore V BE1 = =0.4V (cutoff Q 1 V BE < 0.5V) 1. V B1 = -1.3V reference 4. V B1X = -1.7-(-5.2) = 3.5V 10. Q 2 will be ON & V C2 is low = Buffer Output due to drop at R 2 9. Q 1 will be OFF = V C1 is high = Inverter Output EE Electronics Circuit Design 33 Four-input ECL OR/NOR logic gate Differential Amplifier Emitter Follower If any of the input A or B or C or D is high, Q5 will be OFF making less drop at R C2 -0.9(high at C ) -1.3V0V-5.2V -1.7V(low) (high) EE Electronics Circuit Design 34 Two-input ECL OR/NOR logic gate Emitter Follower -1.3V0V-5.2V -1.7V(low)NOR (high) OR If any of the input A or B is high, Q 3 will be OFF making less drop at R (high) Differential Amplifier EE Electronics Circuit Design 35 Type NumberDescription 10100/10500Quad 2-input NOR with strobe 10101/10501Quad OR/NOR 10102/10502Quad 2-input NOR 10103/10503Quad 2-input OR 10104/10504Quad 2-input AND 10105/10505Triple input OR/NOR 10106/10506Triple input NOR 10107/10507Triple 2-input exclusive OR/exclusive NOR 10109/10509Dual 4-5 input OR/NOR 10110Dual 3-input 3-output OR 10111Dual 3-input 3-output NOR 10113/10513Quad exclusive OR 10117/10517Dual 2-wise 2-3-input OR-AMD/OR-AND- invert 10118/10518Dual 2-wide 3-input OR-AND 10119/ wide input OR-AND 10121/ wide OR-AND/OR-AND-invert 10123Triple i bus driver ECL Device Listings