ee6378 power management circuitsee6378 power management ...traylor/ece473/pdfs/bandgap.pdf · the...
TRANSCRIPT
EE6378 Power Management CircuitsEE6378 Power Management Circuits
Lecture 4: Voltage References g
I t t P f H i LInstructor: Prof. Hoi Lee
Mixed-Signal & Power IC LaboratoryMixed Signal & Power IC LaboratoryDepartment of Electrical Engineering
The University of Texas at Dallas
Introduction
Here, we will learn to build a reference voltage to provide a stable and accurate supply voltage. The voltage reference is an electronic circuit to provide an accurate and stable DC voltage that is very insensitive to the change in supply voltage andthat is very insensitive to the change in supply voltage and temperature
How accurate is a voltage reference? E.g. Weston cell is anHow accurate is a voltage reference? E.g. Weston cell is an electrochemical device which provides a reproducible voltage of 1.018636 V at 20oC with a small temperature coefficient of 40 ppm/oC. For integrated circuit implementation, active solid-state de ices can achie e a tempco of 1 4 ppm/oC if appropriatedevices can achieve a tempco of 1-4 ppm/oC if appropriate compensation technique is employed
NoteNote• To minimize error due to self-heating, voltage reference usually
operates with modest current (e.g. < 1mA)• Tempco = temperature coefficient, usually expressed in ppm/oC
EE6378 Lecture 4 © 2009 H. Lee pg. 2
p p , y p pp(parts per million/oC or 10-6/oC
Overview
Performance Requirements
Zener Diode Voltage Reference
Bandgap Voltage References
Bandgap Voltage References Implemented in CMOS technologies
EE6378 Lecture 4 © 2009 H. Lee pg. 3
Performance Parameters (1)
The primary requirements of a voltage reference are accuracy and stability. Some qualitative parameters are:
Load Regulation = ΔVo/ΔIo (usually expressed in mV/mA or mV/A) or
Load Regulation = 100(ΔVo/ΔIo) (in %/mA or %/A)
Line Regulation = ΔVo/ΔVin (usually expressed in mV/V) or
Line Regulation = 100(ΔVo/ΔVin) (in %/V)
Power Supply Rejection Ratio (PSRR) is a measure of the ripple in the reference voltage due to the ripples in the supply voltage
ro
ri
V
VPSRR 10log20= (in dB)
EE6378 Lecture 4 © 2009 H. Lee pg. 4
Performance Parameters (2)
Example of line regulation / supply-voltage dependence at VDD = 3.3, 4.15 and 5V (step size of 0.85V)
VDD=5V
VDD=4.15V
VDD=3.3V
VmVVVVVVV
C
DDrefDDref /7.14335
176.1201.1
335
)3.3()5(
is 27T at regulation Line o
=−
==−=
=
EE6378 Lecture 4 © 2009 H. Lee pg. 5
3.353.35 −−
Performance Parameters (3)
The maximum (Vref(max)) and minimum (Vref(min)) reference voltages are 1.1761V and 1.1731V, respectively. The reference voltage at T = 27oC (V ) i 1 1761V Th t i / C b f d b(Vref) is 1.1761V. The tempco in ppm/oC can be found by
CppmTTV
VV O
ref
refref /5.25)0100(
10
1761.1
1731.11761.1
)(
10Tempco
6
minmax
6(min)(max) =
−×
−=
−×
−=
EE6378 Lecture 4 © 2009 H. Lee pg. 6
TTVref )0100(1761.1)( minmax
Overview
Performance Requirements
Zener Diode Voltage Reference
Bandgap Voltage References
Bandgap Voltage References Implemented in CMOS technologies
EE6378 Lecture 4 © 2009 H. Lee pg. 7
Review on Zener Diode Voltage Reference
The Zener diode described in Lecture 2 can be considered as a voltage reference. Since the breakdown voltage due to Zener breakdown mechanism has a negative temperature coefficient, and the breakdown voltage due to the avalanche multiplication has a positive coefficient, the reference voltage is somewhat independent of the change of temperature
Lzs
zsZK
zs
sin
zs
zo I
rR
rRV
rR
RV
rR
rV
+−
++
+=
zszszs
zo
rR
r
ΔV
ΔV
+== Regulation Line
zs
zs
L
o
zsin
rR
rR-
ΔI
ΔV
rRΔV
+==
+
Regulation Load
EE6378 Lecture 4 © 2009 H. Lee pg. 8
Improved Zener Diode Reference (1)
In the case of Zener diode, the output voltage Vo heavily depends on the load current IL, which in most cases are not good. It would be better if we could shield the Vz from the influence of the load. This z
can be done with the help of an op amp as shown below. This method refers to self regulation which shifts the burden of line and load regulations from the diode to the op amp
EE6378 Lecture 4 © 2009 H. Lee pg. 9
Improved Zener Diode Reference (2)
B i tiBy inspection,
.102.6)39
241()1(
1
2 Vk
kV
R
RV zo =+=+=
The output voltage is also adjustable via R2
The load current IL is supplied from the .102.6)
39
241()1(
1
2 Vk
kV
R
RV zo =+=+=
391 kR
L ppopamp such that the current flowing through the Zener diode is almost constant at
Since the diode current is independent
.15.13.3
2.60.10
3mA
kR
VVI zoz =
−=
−=
pof the load current, the diode voltage is insensitive to the loadR3 can be raised to avoid unnecessary power wastage and self-heating effects
EE6378 Lecture 4 © 2009 H. Lee pg. 10
power wastage and self heating effects
Load Regulation (1)
The load regulation is directly related to the output impedance. To find Ro, we suppress the input source Vz and apply the test-voltage technique. By voltage divider formula:divider formula:
vRrR
rRv
in
inN
21
1
//
//
+=
Summing currents at the output node
0=−−
+−
+ NN vAvvvi
Eliminating vN and solving for the Ro=v/I, we obtain
02
=++orR
i
1
2121
where
)]//1/()//[(1
Rb
r
rRRRrrRrA
rR
o
ininoo
oo
=≈
+++++=
EE6378 Lecture 4 © 2009 H. Lee pg. 11
21 where
1 RRb
Ab ++
Load Regulation (2)
Typically rin is in the MΩ range or greater, R1 and R2 are in kΩ range and ro is on the order of 102 Ω. The t /R / d R / thterms ro/R1, ro/rin, and R2/rin can thus be ignored to yield Ro≈ro/(1+Ab)
The load regulation R r /(1+Ab)The load regulation Ro≈ro/(1+Ab) which is much smaller than the Zener diode voltage reference without opampp p
Since ro and A are frequency dependent, so are the load regulation. In general, load regulation tends to degrade with frequency
EE6378 Lecture 4 © 2009 H. Lee pg. 12
Thermal Stability (1)
Thermal stability is one of the most demanding performance requirement of voltage references due to the fact that semiconductor components are strongly influenced by temperature
The for ard bias oltage V and c rrent I of a silicon pn j nctionThe forward-bias voltage VD and current ID of a silicon pn junction, which forms the basis of the diodes and BJTs, are related as VD=VTln(ID/IS), where VT is the thermal voltage and IS is the saturation current. Their expressions arep
where
)/exp( and / 03
TGST VVBTIqkTV −==
k=1.381×10-23 is Boltzmann’s constant
q=1.602 ×10-23 C is the electron charge
T is the absolute temperaturep
B is a proportionality constant
VG0 = 1.205V is the bandgap voltage for silicon
EE6378 Lecture 4 © 2009 H. Lee pg. 13
Thermal Stability (2)
The temperature coefficient (TC) of the thermal voltage:
CmV/08620)(TC o==∂
=kV
V TT CmV/0862.0)(TC ==
∂=
qTVT
)3
(
)ln3(][ln
)ln()(TC 0
0
kVVV
VT
VVI
I
VIV
V DGT
G
DS
D
DT +−
=−∂
=∂
+∂
=
Assume VD=650mV at 25oC, we get TC(VD) ≈ -2.1mV/oC.
)-()ln()(TCqTT
VTT
VIT
V TTS
D +=∂
−=∂
+∂
=
TC(VT) have a positive tempco and TC(VD) have a negative tempco, so these two equations form the basis of two common approaches to thermal stabilization, namely, thermal compensated Zener diode , y, preferences and bandgap references
EE6378 Lecture 4 © 2009 H. Lee pg. 14
Thermally Compensated Zener Diode Reference
Idea of thermally compensated Zener diode is to connect a forward-biased diode in series with a Zener diode having an equal but opposing tempco as shown below
Since TC(Vz) is a function of Vz and Iz. We can fine tune Iz to drive the tempco of the composite device to zero. In this case, a 7.5mA is p p ,used to give a reference voltage of Vz = 5.5+0.7 = 6.2V with tempco ranging from 100ppm/oC to 5ppm/oC
EE6378 Lecture 4 © 2009 H. Lee pg. 15
Overview
Performance Requirements
Zener Diode Voltage Reference
Bandgap Voltage References
Bandgap Voltage References Implemented in CMOS technologies
EE6378 Lecture 4 © 2009 H. Lee pg. 16
Bandgap Voltage Reference (1)
Since the best breakdown voltages of the Zener diode references range from 6 to 7V, they usually require supply voltages on the order of 10V to operate. This can be a drawback in systems powered from l li h V Thi li i i i b b dlower supplies, such as 5V. This limitation is overcome by bandgap voltage references, so called because their output is determined primarily by the bandgap voltage of silicon VG0 = 1.205V
EE6378 Lecture 4 © 2009 H. Lee pg. 17
Bandgap Voltage Reference (2)
Addition of the voltage drop V of a base-emitterAddition of the voltage drop VBE of a base-emitter junction, which has a negative tempco, to a voltage proportional to the thermal voltage VT, which has a
iti t t t f lt hi hpositive tempco, to generate a reference voltage, which is independent of temperature
EE6378 Lecture 4 © 2009 H. Lee pg. 18
Fundamentals
As TC(VBE) ≈ -2.1mV/°C and TC(VT) = 0.0086mV/°C, then zero tempco is achieved at a particular temperature (e.g. T=300K):
12)(
0)()(|)( i.e. 300
−
=⋅+=
+=
BE
TBEKBG
TBEBG
VTC
VTCKVTCVTC
KVVV
If for a particular transistor with certain bias current such that VBE =
4.24086.0
1.2
)(
)( ==
−=⇒
T
BE
VTC
VTCK
If for a particular transistor with certain bias current such that VBE = 650mV, then
V. 28.1)0259.0(4.2465.0 =+=+= TBEBG KVVV
Note that VT = kT/q ∝ T, i.e. VT is proportional to absolute temperature. We call VT a Proportional To Absolute Temperature voltage, or in short, PTAT voltage
EE6378 Lecture 4 © 2009 H. Lee pg. 19
Bandgap Voltage Reference Circuit (1)
From the figure, the emitter area of Q1 is n times as large as the emitter area of Q2, then Is1/Is2 = n
By op amp action with identical collector resistances, the collector currents are also identical, i.e. IC1 = IC2. Ignore the base currents we have KV = R (I +I ) = 2R I
)ln()ln(11
12123 nV
II
IIVVVIR T
SC
SCTBEBE ==−=
currents, we have KVT = R4(IC1+IC2) = 2R4I
)ln()ln(11
12123 nV
II
IIVVVIR T
SC
SCTBEBE ==−=
Combine two equations give
T nRVR
K )ln(22 44 ==
TBETBEBG
T
VnR
RVKVVV
nRRV
K
)ln2(
)ln(2
3
422
33
+=+=⇒
==
EE6378 Lecture 4 © 2009 H. Lee pg. 20
Bandgap Voltage Reference Circuit (2)
F th i di i fFrom the previous discussion, for a zero tempco voltage reference VBG, K ≈ 24, with n = 4, then
8.84ln2
4.24
2ln23
4 ≈==K
R
R
Note that I = VTln(n)/R3 ∝ VT, I is a PTAT current
EE6378 Lecture 4 © 2009 H. Lee pg. 21
Brokaw Cell
Brokaw cell is commonly used bandgap-cell li ti i it d i h i th firealization circuit and is shown in the figure
The function of op amp is replaced by Q3, Q4 and Q5. Q3 and Q4 form a current mirror to enforce the collector currents of Q1 and Q2 are identical
The emitter follower Q5 raises the reference voltage to Vref = (1+R1/R2)VBG
EE6378 Lecture 4 © 2009 H. Lee pg. 22
Stability of a Bandgap Reference
In a bandgap reference, there exists 2 feedback loops, 1 positive loop and 1 negative loop.
For the negative loop (the outer loop),)(
/1
/1
121
12 sAgRR
gR
m
m
+++
=Gain Loop Negative
)(/1
GainLoopNegati e 12 sAgR m+
For the positive loop (the inner loop),
)(/1
Gain LoopNegative121
12 sAgRR
g
m
m
++=
For stability, we must have a negative
)(/1
/1Gain Loop Positive
11
1 sAgR
g
m
m
+=
loop gain magnitude > positive loop gain magnitude. This is true as ((a+c)/(b+c))>(a/b) for b>a
EE6378 Lecture 4 © 2009 H. Lee pg. 23
Stability of Simple Brokaw Cell (1)
If we neglect R3, then clearly Q1 and Q2 form a differential pair with positive and negative terminals tied togetherp g g
Above is the way to break the loop for measuring loop gain. The circuit should have a DC closed loop and AC open loop. The DC closed loop is for biasing and the AC loop is to measure loop gain
EE6378 Lecture 4 © 2009 H. Lee pg. 24
p g p p g
Stability of Simple Brokaw Cell (2)
With the presence of R3, the positive loop looks like an amplifier with degenerated emitter ⇒ the gain is smaller than that with R3. Therefore, negative loop gain magnitude > positive loop gain magnitude, i.e. stability requirement is satisfiedCc is the compensation capacitor. Here, dominant pole compensation is employed
EE6378 Lecture 4 © 2009 H. Lee pg. 25
compensation is employed
Overview
Performance Requirements
Zener Diode Voltage Reference
Bandgap Voltage References
Bandgap Voltage References Implemented in CMOS technologies
EE6378 Lecture 4 © 2009 H. Lee pg. 26
CMOS Bandgap References (1)
CMOS is the dominant technology for both digital and analog circuit design nowadaysanalog circuit design nowadays
Independent bipolar transistors are not available in CMOS technology
CMOS voltage reference, however, can be achieved by making use of the concept of voltage reference. These CMOS circuits rely on using well transistors TheseCMOS circuits rely on using well transistors. These devices are vertical bipolar transistors that use wells as their bases and the substrate as their collectors
EE6378 Lecture 4 © 2009 H. Lee pg. 27
CMOS Bandgap References (2)
These vertical bipolar well transistors have reasonable current gain (≈ 25), but very high series base resistance (≈ 1kΩ/ ) due to the fact that the base contact is far away from the basethat the base contact is far away from the base
The maximum collector current is thus limited to less than 0.1mA to minimize errors due to the base resistance
EE6378 Lecture 4 © 2009 H. Lee pg. 28
CMOS Bandgap References (3)
Two possible implementations:
F l i th ll CMOS i l t ti h t i V f thFor example, in the n-well CMOS implementation, what is VBG of the reference circuit?
EE6378 Lecture 4 © 2009 H. Lee pg. 29
CMOS Bandgap References (4)
Assume the op amp has very large gain and very small input currents such that its
= +2 2BG EB RV V V
and very small input currents such that its input terminals are at the same voltage, then
EBEBEBR VVVV Δ=−= 123
V V V V
Since the current through R1 is the same as in R
= − = Δ3 2 1R EB EB EBV V V V
as in R3
= = = Δ31 1 11 3
1 3 3 3
or RRR R EB
VV R RV V V
R R R R1 3 3 3R R R R
12
3BG EB EB
RV V V
R= + Δ
EE6378 Lecture 4 © 2009 H. Lee pg. 30
CMOS Voltage References (5)
In CMOS realization, the bipolar transistors are often taken the same size, and different current densities (IC/IS) are realized by taking R1 greater than R2, which causes I2 to be greater than I1:
2 11 2 1 1 2 2
1 2
or R R
I RV V I R I R
I R= ⇒ = =
22 1
1
ln( )EB EB EB
IkTV V V
q I
R R R RkT
Δ = − =
1 1 1 12
3 2 3 2
ln( ) with ln( )BG EB
R R R RkTV V K
R q R R R⇒ = + =
EE6378 Lecture 4 © 2009 H. Lee pg. 31
Example
Find the resistances of a bandgap voltage reference based on the CMOS n-well process where I1 = 5μA, I2 = 40μA and VEB = 0.65V at
300 1 2T = 300K. Assume VBG = 1.24V
Ans. R1 = 118kΩ, R2 = 14.8kΩ and R3 = 10.1kΩ
EE6378 Lecture 4 © 2009 H. Lee pg. 32
Other CMOS References
Current mirror enforces equal currents at M1, M2 and M3
Voltage clamping by M4 and M5 to enforce V1=V2
PTAT loop formed by Q1, Q2 and R1
ln( ) /I V N R=
Cascode current mirror or other
1
23
1
ln( ) /
ln( )
T
ref EB T
I V N R
RV V N V
R
=
= + ⋅
Cascode current mirror or other forms for better current matching at different supply voltages
EE6378 Lecture 4 © 2009 H. Lee pg. 33
Current Mirror with Op Amp
In CMOS reference using current mirror with op amp, an op amp is used to enforce the drain voltage ofenforce the drain voltage of M1 the same as of M2. This allows a better current matching of drain currents ofmatching of drain currents of M1 and M2
EE6378 Lecture 4 © 2009 H. Lee pg. 34
Error Sources in Voltage-Reference Design
Current mirror
Voltage-clamping circuitVoltage clamping circuit
BJT emitter area ratio (BJT matching)
Resistor ratio (resistor matching)Resistor ratio (resistor matching)
Base current
Base resistanceBase resistance
Systematic offset at different supply voltages
Random offset of devicesRandom offset of devices
Temperature gradient within a chip
EE6378 Lecture 4 © 2009 H. Lee pg. 35
Design Considerations: BJTs
Closely packed common-centroid layout
L N d id i ifi h d h l i hLarge N does not provide significant change due to the logarithm relation
Generally, N=8 is chosen based on chip area consideration
EE6378 Lecture 4 © 2009 H. Lee pg. 36
Design Considerations: Resistors
Matching is important to obtain an accurate resistance ratio
Square-like common-centroid layoutlayout
EE6378 Lecture 4 © 2009 H. Lee pg. 37
Typical Low-Voltage Implementation
Error-amplifier current mirror enforces VA = VB
Min VDD = VREF + |Vov,M2|
Offset voltage → errorOffset voltage → error
Offset voltage = function of VTH, mobility and transistor size →mobility and transistor size →temperature dependent
Use simple amplifierp p
Reduce both systematic and random offset
EE6378 Lecture 4 © 2009 H. Lee pg. 38
Offset Voltage Consideration
1
2
ln( )
( )[ ln( ) ]
T OFFV N VI
R
RV V V N V
+=
⇒ + +
A l N i d t i i i
22
1
( )[ ln( ) ]ref EB T OFFV V V N VR
⇒ = + ⋅ +
A larger N is used to minimize the required R2/R1, and the effect of the amplifier offset
I hiIncrease chip area
EE6378 Lecture 4 © 2009 H. Lee pg. 39
Base Resistance Consideration
Large base resistance of parasitic vertical BJT
Diode-connected BJT ≠ VEB
As mentioned before, I < 0.1mA
Not due to low-power design, but due to reduce voltage across RB
On layout, more N-well contacts to reduce RB
EE6378 Lecture 4 © 2009 H. Lee pg. 40
Base Current Compensation
β is small in CMOS technology
IC ≠ IE and IC is a function of β
Introduced β in IC causes extra errors and temperature dependencedependence
Base current compensation by a dummy transistor Q1Ddummy transistor Q1D
IE of Q1 = I + I/βI of Q1 = IIC of Q1 = I
Q1D must match with Q1
EE6378 Lecture 4 © 2009 H. Lee pg. 41
Resistor Trimming
R i i b fi d bResistor ratio can be fine-tuned by using a series of resistor network associated with fuse
By burning the fuse, the resistor value can be adjusted to fine-tune th f lt d ththe reference voltage and the temperature with zero tempco to a particular value
EE6378 Lecture 4 © 2009 H. Lee pg. 42
Buffered Voltage Reference
Series-shunt feedbackSeries shunt feedback
High output current to drive resistive load
Low output resistance
Isolation to reduce cross-talk through reference circuit
EE6378 Lecture 4 © 2009 H. Lee pg. 43
Current Source Generated by a Voltage Reference
Series-series feedback
I = VREF/R
VMIN = Vov + VREF
EE6378 Lecture 4 © 2009 H. Lee pg. 44
MIN ov REF
CMOS Bandgap Reference with Sub-1-V Operation (1)
R1 R2 & R3 of same material
3 22
2 1
( )( ( )ln( ) )REF EB T
R RV V N V
R R= + ⋅
R1, R2 & R3 of same material
Good matching R1 and R2 for optimizing tempcooptimizing tempco
Good matching R2 and R3 for dj ti th l f Vadjusting the value of VREF
M1, M2 & M3 of equal W, L
VREF ≈ 0.5-0.7 V for matching VDS of M1-M3 at different VDD
EE6378 Lecture 4 © 2009 H. Lee pg. 45
DD
CMOS Bandgap Reference with Sub-1-V Operation (2)
Native NMOST : V = 0 2VNative NMOST : VTHN = 0.2V
Not available in standard CMOS technologiesCMOS technologies
EE6378 Lecture 4 © 2009 H. Lee pg. 46
Low-Voltage Design Problem of Error Amplifier
Worst case (smallest) VEB at maximum operational temperature
Worst case (largest) VEB and |VTHP| at minimum temperaturetemperature
VEB > VTHN + 2Vov
Low-VTHN (<0.4V) technology
B d ff t i V
| THP| p
VEB < VDD - |Vthp| - 2|Vov|
VDD(min) = VEB + |VTHP| + 2Vov
EE6378 Lecture 4 © 2009 H. Lee pg. 47
Body effect increases VTHN
References
H. Banba, et. al. “A CMOS bandgap reference circuit with sub-1-V operation,” IEEE Journal of Solid-State Circuits, vol. 34, pp. 670-674, May 1999.
K. N. Leung, et. al. “A sub-1-V 15-ppm/°C CMOS bandgap voltage reference without requiring low threshold voltage device,” IEEE Journal of Solid-State Circuits, vol. 37, pp. 526-530, Apr. 2002.
P. K. T. Mok, et. al. “Design considerations of recent advanced low-voltage low-temperature-coefficient CMOS bandgap voltage reference,” IEEE Custom Integrated Circuits Conference, Sep. 2004, pp. 635-642.
EE6378 Lecture 4 © 2009 H. Lee pg. 48