eeeb273 1213s1 test2

7/23/2019 Eeeb273 1213s1 Test2

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College of EngineeringDepartment of Electronics and Communication Engineering

Test 2

SEMESTER 1, ACADEMIC YEAR 2012/2013

Subject Code : EEEB273

Course Title : Electronics Analysis & Design II Date : 3 August 2012

Time Allowed : 1.5 hours

Instructions to the candidates:

1. Write your Name and Student ID number. Circle your section number.

2. Write all your answers using pen. DO NOT USE PENCIL except for the diagram.

3. ANSWER ALL QUESTIONS.

4. WRITE YOUR ANSWER ON THIS QUESTION PAPER. 5. For BJT, use V T = 26 mV where appropriate.

6. Use at least 4 significant numbers in all calculations.

NOTE: DO NOT OPEN THE QUESTION PAPER UNTIL INSTRUCTED TO DO SO.

GOOD LUCK!

Question No. 1 2 3 Total

Marks

Name:

Student ID Number:

Section: 01/02/03/04/05 A/B

Lecturer: Dr Jamaludin / Dr Azni Wati

/ Dr Fazrena Azlee

7/23/2019 Eeeb273 1213s1 Test2


EEEB273 Semester 1, 2012/2013 Test 2

Question 1 [40 marks]

The circuit parameters for the differential amplifier shown in Figure 1 are V +

= 5 V, V ¯

= −−−−5 V, A cm

= −−−−0.28, and I Q = 240 µµµµA. The NMOS transistor parameters are V TN = 0.4 V, k’ n = 100 µµµµA/V 2

,

(W/L) n = 8, and λ λλ λ n = 0.018 V-1

. The PMOS transistor parameters are V TP = −−−−0.4 V, k’ p = 40 µµµµA/V2,

(W/L) p = 10, and λ λλ λ p = 0.02 V-1

.

a) Determine the maximum common-mode voltage input, v cm(max), that can be applied

such that the transistors are still biased in saturation region. [6 marks]

b) Draw the ac equivalent circuit for the differential-mode input (v1 = +v d /2 and v2 = − −− − v d /2).

Indicate the resultant ac currents in all transistors. [6 marks]

c) Determine the output resistance R o of the differential amplifier. [5 marks]

d) Calculate the small-signal differential-mode voltage gain A d = v o /v d . [5 marks]

e) Suggest one way to increase the differential-mode voltage gain and show your new circuit

and justify the change(s). [6 marks]

f) Find the one-sided output voltage (v o) taken at v D2 of the differential amplifier when v1 =

(0.10 + 0.05 sin ωωωωt) mV and v2 = (−−−−0.10 + 0.05 sin ωωωωt) mV. [12 marks]

Figure 1

7/23/2019 Eeeb273 1213s1 Test2



Answers for Question 1

(a) V SG3 = [√√√√( I D3 / K n)] - V TP

= [√√√√( I Q /2)/[( k’ p /2)(W/L) p]] - V TP

= [√√√√(120µµµµ)/[(40µµµµ /2)(10)]] + 0.4

= 1.175 V

v cm(max) = V +

- V SG3 - V DS1(sat) + V GS1

= V +

- V SG3 - (V GS1 - V TN ) + V GS1 = V +-V SG3 + V TN

= 5 - 1.175 + 0.4

= 4.225 V

(b)

3

3

1/2

1

1

1

1/2

1/21/2

1/2 1/2

7/23/2019 Eeeb273 1213s1 Test2



Answers for Question 1 (Cont.)

(c)

r o2 = 1/(λ λλ λ n I D) = [(0.018)(120µµµµ)]-1

= 463 kΩΩΩΩ

r o4 =1/(λ λλ λ p I D) = [(0.02)(120µµµµ)]-1

= 416.7 kΩΩΩΩ

R o = r o2| || || || | r o4 = 219.3 kΩΩΩΩ

(d) R o = r o2| || || || | r o4 = 219.3 kΩΩΩΩ

g m = 2√√√√[ K n I D] = 2 √√√√ [( k’ n /2)(W/L) n( I Q /2)]

=2 √√√√ [( 100µµµµ /2)(8)(120µµµµ)] = 0.4382 mA/V2

A d = g m R o = (0.4382m)(219.3k) = 96.09

(e)

Increase voltage gain by using cascode active load.

A d = g m R o

Previous R o = r o2| || || || | r o4

New circuit R o = r o2| || || || | R o(active load) = r o2| || || || | g m r o4 r o6 ≅ ≅≅ ≅ r o2

The new R o is larger than the previous one.

2

1

2

1

-transistor type PMOS

-within cascode connections

-connection with diff-amp

1

2

2

1

2

2

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(f) v d = v1 - v2

= (0.10 +0.05 sin ωωωωt) - (−−−−0.10 +0.05 sin ωωωωt)

= 0.20 mV v cm = (v1 + v2)/2

= [(0.10 +0.05 sin ωωωωt) + (−−−−0.10 +0.05 sin ωωωωt)]/2

= 0.05 sin ωωωωt mV

vO = A d v d + A cmv cm

= (96.09)(0.2mV) + (-0.28)(0.05 sin ωωωωt mV)

= (19.22 – 0.014 sin ωωωωt) mV

2

1

1

2

1

1

1

2

1

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Figure 3

For a simplified class-AB output stage with BJTs in Figure 3, given that V CC = 5 V and R L = 1 k.

For each transistor, the reverse-bias saturation current is I S = 2 x 10-15

A.

a)

What are two disadvantages of class-AB output stage compared to the class-B output

stage? [4 marks]

b) What is the advantage of class-AB output stage compared to the class-B output stage?

[2 marks]

c) Determine the value of V BB that produces iCn = iCp = 1.1 mA when v I = 0 V. What is the

power dissipated in each transistor? [6 marks]

d) For vO = -3.6 V, determine i L, iCn, iCp, and v I . Reiterate your calculation twice for iCn and

iCp. What is the power dissipated in Q n, Q p, and R L? [18 marks]


a) i) Required power handling capability of Qs in class-AB will be slightly larger than class-B.

ii) Power Conversion Efficiency () will be less than class-B.[2 marks for each answer]

b) Eliminating crossover distortion in the class-B. [2 marks]

7/23/2019 Eeeb273 1213s1 Test2




c)

iCn = I S exp(V BEn / V T )

V BEn = V T ln(iCn / I S) [1]

= (0.026) ln (1.1x10-3

/ 2x10-15

) = 0.70286 V [0.5, 0.5]

V BB = 2 V BE [1] = 2 x 0.70286 = 1.40572 V [0.5, 0.5]

PQ = iCn vCE [1]

= (1.1m)(5V – 0V) = 5.5 mW [0.5, 0.5]

d)

For vO = -3.6 V, i L = vO / R L [1]

= (-3.6V)/(1 k) = -3.6 mA [0.5, 0.5]

Approximation: iCp | i L | = 3.6 mA [1]

v EBp = V T ln(iCp / I S) [0.5]= (0.026) ln(3.6x10

-3 / 2x10

-15) = 0.73369 V [0.5]

v BEn = V BB - v EBp [1]

= 1.40572 – 0.73369 = 0.67203 V [0.5]

iCn = I S exp(V BEn / V T ) [1]

= (2x10-15

) exp(0.67203 / 0.026) = 0.336026 mA [0.5]

Then, finally iCp iCn - i L [1]

= (0.336026m) - (-3.6m) = 3.936026 mA [0.5]

v EBp = V T ln(iCp / I S)

= (0.026) ln(3.936026x10-3

/ 2x10-15

) = 0.73601 V [0.5]

v BEn = V BB - v EBp

= 1.40572 – 0.73601 = 0.66971 V [0.5]

iCn = I S exp(V BEn / V T )

= (2x10-15

) exp(0.66971 / 0.026) = 0.307341 mA [0.5]

iCp = iCn - i L

= (0.307341m) - (-3.6m) = 3.907341 mA [0.5]

v I = vO - v EBp + V BB /2 [1]

= (-3.6) - 0.73601 + 1.40572/2 = -3.63315 V [0.5]

Power:

For Q n: PQn = iCn vCEn [1]

= (0.307341m)(5-(-3.6)) = 2.643 mW [0.5, 0.5]

For Q p: PQp = iCp v ECp [1]

= (3.907341m)(-3.6-(-5)) = 5.470 mW [0.5, 0.5]

For R L: P RL = i2 L R L [1]

= (-3.6 mA) 2

(1 k) = 12.96 mW [0.5, 0.5]

7/23/2019 Eeeb273 1213s1 Test2




Figure 3

Refer to Figure 3. It is given that I Q = I R4 = I R6 = 0.4 mA, and I R7 = 2 mA. Neglect base currents

and assume V BE(on) = 0.7 V for all transistors except Q8 and Q9 in the Widlar circuit.

a) List all transistors and resistors forming the biasing stage of the circuit in the Figure 3?[3 marks]

b) Calculate the common-mode input range. State your assumptions. [7 marks]

c) Calculate overall gain of the circuit. Assume = 100 and V A = . It is given that the gain of

the Darlington Pair can be calculated using [18 marks]

d) Comment on the loading effect of the output stage onto the gain stage. [2 marks]

( )354

2 ||2 i

T

RV R RV

I

A

=

7/23/2019 Eeeb273 1213s1 Test2




a)

Q7, R1, Q8, R2, Q9 and R3. [0.5 mark each]

b)V cm(max) = V C 1, assume V CE(min) = V BE(on) [1]

V C 1 = V +

- I C 1 RC = 10 - (0.2m)(20k) = 6 V [2]

V cm(min) = V - + V BE1 + V BE8 [2]

assume neglect V R2 [0.5]

V cm(min) = -10 + 0.7 + 0.7 = -8.6 V [1.5]

c)

[2]

[2]

[2]

[0.5]

[1.5]

[0.5]

[0.5]

[1]

[2]

[0.5]

[0.5]

[1]

[1]

[1]

[2]

d)

Since Ri3 >> R5, the output stage does not load down the gain stage [2]

−==

32

3

21

2321 ....

o

o

o

oovvd d

v

v

v

v

vv

v A A A A

( )

( )

8.751307k)||m/2)(20k 70.7(

mA/V70.7)026.02 /(m4.0)2 /(

k 1307)k 5.6)(101(k 650

k 650m4.0 / )026.0()100( /

k 5.6m4.0 / )026.0)(100( /

1

2

1

2

2

4

2

3

44

432

22

1

==∴

=×==

Ω=+=

Ω==≅

Ω===

++=

=

=

d

T Qm

i

RT

RT

i

iC m

d

od

A

V I g

R

I V r

I V r

r r R

R Rg

v

V A

β

β

β

π

π

π π

( ) ( )[ ]

( ) ( )[ ]

( ) ( )

2918)1)(5.38)(8.75(

1

5.38M8.52k 5)026.0(2

m4.0

2

M8.52k 51001k 3.1k 5.161001k 5.6

k 3.1m2 / )026.0)(100( /

k 5.6m4.0 / )026.0)(100( /

11

3

354

2

3

76

65

76653

==

≈

===

Ω=+++++=

Ω===

Ω===

+++++=

d

v

i

T

Rv

i

RT

RT

i

A

A

R RV

I A

R

I V r

I V r

Rr Rr R

β

β

β β

π

π

π π

7/23/2019 Eeeb273 1213s1 Test2



Appendix: BASIC FORMULA

BJT MOSFET

CQ

Ao

T

CQ

m

CQ

T

m

C B E

B E C

V v

S C

V v

S C

I

V r

V

I g

I

V r

r g

iii

iii

e I i

e I i

T EB

T BE

=

=

=

=

+=

+=

==

=

=

β

β

β β α

β α

π

π

signalSmall;

1

pnp;

npn;

/

/

( )

DQ

o

DQnTN GSQnm

p

p

TPSG p D

TPSGSD

nn

TN GS n D

TN GS DS

I r

I K V V K g

L

W k K

V vK i

V vv

L

W k K

V vK i

V vv

λ

1

22

signalSmall;

2

][

(sat)

MOSFETP;

2

][

(sat)

MOSFETN;

'

2

'

2

≅

=−=

⋅=

+=

+=

−

⋅=

−=

−=

−

eeeb273 1213s1 test2

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