eitan yaakobi, laura grupp steven swanson, paul h. siegel, and jack k. wolf flash memory summit,...
DESCRIPTION
SLC, MLC and TLC Flash 3 High Voltage Low Voltage 1 Bit Per Cell 2 States SLC Flash High Voltage Low Voltage 2 Bits Per Cell 4 States MLC Flash High Voltage Low Voltage 3 Bits Per Cell 8 States TLC FlashTRANSCRIPT
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Eitan Yaakobi, Laura Grupp Steven Swanson, Paul H. Siegel, and Jack K. Wolf
Flash Memory Summit, August 2011
University of California San Diego
Error-Correcting Codes for TLC Flash
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Outline
Flash Memory Structure Partial Cell Usage in TLC Flash ECC Comparison for TLC Flash New ECC Scheme for TLC Flash
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SLC, MLC and TLC Flash
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High Voltage
Low Voltage
1 Bit Per Cell2 States
SLC Flash
011010000001101100110111
01
00
10
11
0
1
High Voltage
Low Voltage
2 Bits Per Cell4 States
MLC Flash
High Voltage
Low Voltage
3 Bits Per Cell8 States
TLC Flash
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Flash Memory Structure
A group of cells constitute a page A group of pages constitute a block
• In SLC flash, a typical block layout is as follows
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page 0 page 1page 2 page 3page 4 page 5
.
.
.
.
.
.page 62 page 63
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Flash Memory Structure In MLC flash the two bits within a cell DO NOT belong
to the same page – MSB page and LSB page Given a group of cells, all the MSB’s constitute one
page and all the LSB’s constitute another page
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Row index
MSB of first 214 cells
LSB of first 214 cells
MSB of last 214 cells
LSB of last 214 cells
0 page 0 page 4 page 1 page 51 page 2 page 8 page 3 page 92 page 6 page 12 page 7 page 133 page 10 page 16 page 11 page 17
⋮ ⋮ ⋮ ⋮ ⋮
30 page 118 page 124 page 119 page 12531 page 122 page 126 page 123 page 127
01
10
00
11
MSB/LSB
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Flash Memory Structure - TLC
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Row index
MSB of first 216
cells
CSB of first 216
cells
LSB of first 216
cells
MSB of last 216 cells
CSB of last 216 cells
LSB of last 216 cells
0 page 0 page 11 page 2 page 6 page 12 page 3 page 7 page 132 page 4 page 10 page 18 page 5 page 11 page 193 page 8 page 16 page 24 page 9 page 17 page 254 page 14 page 22 page 30 page 15 page 23 page 31
⋮ ⋮ ⋮ ⋮ ⋮
62 page 362 page 370 page 378 page 363 page 371 page 37963 page 368 page 376 page 369 page 37764 page 374 page 382 page 375 page 38365 page 380 page 381
MSB Page CSB Page LSB Page MSB Page CSB Page LSB Page
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Experiment Description We checked several flash memory TLC blocks For each block the following steps are repeated
• The block is erased• A pseudo-random data is written to the block• The data is read and compared to find errors
Remarks:• We measured many more iterations than the
manufacturer’s guaranteed number of erasures• The experiment was done in laboratory conditions and
related factors such as temperature change, intervals between erasures, or multiple readings before erasures were not considered
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Raw BER Results
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Raw BER Results
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011010000001101100110111
High Voltage
Low Voltage
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Partial Cell State Usage
Store either one or two bits in every cell• For one bit, only the MSB pages• For two bits, only the MSB and CSB pages
Two cases:• The partial storage is introduced at the beginning• The partial storage is introduced after 2000 normal
program/erase cycles
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011010000001101100110111
High Voltage
Low Voltage
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Partial Cell State Usage - BER
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ECC Comparison
We evaluated different ECC schemes BCH Codes LDPC Codes
• Gallager Codes• Protograph-based low-density convolutional codes• AR4JA protograph-based LDPC codes• LDPC codes taken from MacKay’s database of
sparse graph codes
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ECC Comparison R ≈ 0.8
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ECC Comparison R ≈ 0.9
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ECC Comparison R ≈ 0.925
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New ECC Scheme for TLC Flash
Errors are corrected in each page independently In particular, in a group of MSB, CSB, and LSB
pages sharing the same group of cells, errors are still corrected independently
Goal: to correct errors in a group of pages together
If a cell is in error, then with high probability one of the bits in the cell is in error
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011010000001101100110111
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New ECC – Encoder
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s2 ∊GF(2)r2
C2 EncoderpMSB = (p1,…,pn)
pCSB = (c1,…,cn)
pLSB = (l1,…,ln)
ϕu = (u1,…,un) ∊GF(4)n
C1 Encoders1 ∊GF(4)r1
From every group of three pages we generate one page over GF(4)
Use two codes• A code over GF(4) – encodes the new page over GF(4)• A binary code – encodes the MSB pages
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New ECC – Encoder
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s2 ∊GF(2)r2
C2 EncoderpMSB = (p1,…,pn)
pCSB = (c1,…,cn)
pLSB = (l1,…,ln)
ϕu = (u1,…,un) ∊GF(4)n
C1 Encoders1 ∊GF(4)r1
From every group of three pages we generate one page over GF(4)
Use two codes• A code over GF(4) – encodes the new page over GF(4)• A binary code – encodes the MSB pages
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New ECC - Insights If there is a cell error, then with high probability at most one
of the bits in the cell is in error The code over GF(4) find these one-bit cell-errors However, it is still possible to see 2-bit and 3-bit cell errors After the first stage, if a cell has 2- or 3-bit cel-errors, then all
the bits are in error The second code, working on the MSB bits, finds these errors
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p’MSB = (p’1,…,p’n)
p’CSB = (c’1,…,c’n)
p’LSB = (l’1,…,l’n)
ϕu’ = (u’1,…,u’n) ∊GF(4)n
C1 Decoder
s1 ∊GF(4)r1
e’ = (e’1,…,e’n) ∊GF(4)nψ
p’’MSB = (p’’1,…,p’’n)
p’’CSB = (c’’1,…,c’’n)
p’’LSB = (l’’1,…,l’’n)
C2 Decoder
s2 ∊GF(2)r2
e’’ = (e’’1,…,e’’n) ∊GF(2)n
+MSB Page
CSB Page
LSB Page
+ +
New ECC – Decoder
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Summary Partial Cell Usage in TLC Flash ECC Comparison for TLC Flash New ECC Scheme for TLC Flash More analysis of codes and error behavior -
COME TO BOOTH #115!
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Acknowledgements
Aman Bhatia, Brian K. Butler, Aravind Iyengar, and Minghai Qin for their help in processing the error measurement results and, in particular, for the LDPC code performance simulations
Jeff Ohshima and Hironori Uchikawa for their collaboration and support from Toshiba
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