electronic circuits, elct 604 spring semester 2018 · 2018. 5. 15. · iet, electronics department...

IET, Electronics Department

Electronic Circuits (ELCT 604)

Final Exam Spring 2018 Dr. Eman Azab

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Electronic Circuits, ELCT 604

Spring Semester 2018 Final Exam

Instructions: Read Carefully Before Proceeding.

1- No programmable/storing calculators, book or other aids are permitted for this test.

2- Write your solutions in the space provided. If you need more space, write on the

back of the sheet containing the problem.

3- Answer all questions.

4- Read all the problems carefully before starting, and start with the easiest question

you find.

5- This exam booklet contains 14 pages, including this one. This exam consists of

four questions.

6- When you are told that time is up, stop working on the test.

7- Total time allowed for this exam is 180 min.

Good Luck

Question Number 1 2 3 4 Total

Maximum Score 40 45 40 25 150

Obtained Score

Bar Code




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Formula Sheet

1. MOS-FET: Modes of Operation

a. Cutoff:

IDS = 0 b. Linear

IDS = K ((VGS − VT)VDS −VDS

2

2)

c. Saturation

IDS =K

2(VGS − VT)2

Where: 𝐾 =𝑘𝑛

′ 𝑊

𝐿

2. BJT: Modes of Operation

Mode I-V Characteristics

Cutoff 𝐼𝐶 = 𝐼𝐸 = 𝐼𝐵=0

Active (Forward) 𝑉𝐵𝐸 = 0.7 𝑉, 𝐼𝐸 = 𝐼𝐶 + 𝐼𝐵,𝐼𝐶 = 𝛽𝐹𝐼𝐵

Saturation 𝑉𝐶𝐸 = 0.2 𝑉, 𝐼𝐸 = 𝐼𝐶 + 𝐼𝐵

Reverse Active 𝑉𝐵𝐶 = 0.5 𝑉, 𝐼𝐶 = 𝐼𝐸 + 𝐼𝐵, 𝐼𝐸 = 𝛽𝑅𝐼𝐵




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3. Small Signal Model

𝑔𝑚,𝑀𝑂𝑆 = √2𝐾𝐼𝐷𝑆 , 𝑟𝑑𝑠 =𝑉𝐴

𝐼𝐷𝑆=

1

𝜆𝐼𝐷𝑆

𝑔𝑚,𝐵𝐽𝑇 =𝐼𝐶

𝑉𝑇 , 𝑟𝜋 =

𝛽

𝑔𝑚, 𝑟𝑜 =

𝑉𝐴

𝐼𝐶, 𝑉𝑇 = 25𝑚𝑉

4. Feedback Amplifiers

𝐴𝐹𝐵 =𝐴

1 + 𝐴𝛽𝐹𝐵

𝑅𝐹𝐵,𝑆𝑒𝑟𝑖𝑒𝑠 = 𝑅(1 + 𝐴𝛽𝐹𝐵)

𝑅𝐹𝐵,𝑆ℎ𝑢𝑛𝑡 =𝑅

(1 + 𝐴𝛽𝐹𝐵)

𝑆𝑒𝑛𝑠𝑖𝑡𝑖𝑣𝑖𝑡𝑦 =𝑑𝐴𝐹𝐵

𝐴𝐹𝐵=

𝑑𝐴

𝐴

1

(1 + 𝐴𝛽𝐹𝐵)

Figure 1 MOS-FET Model Figure 2 BJT Model




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Problem 1: (Feedback Amplifiers: 40 Marks)

The circuit diagram of a two-stage CMOS voltage amplifier with feedback topology is

shown in Figure 1;

1. Define and explain the two stages implementation (6 marks)

2. Find expressions for the transistors DC currents at Zero DC input voltage (as a

function in the biasing current sources ISS1 and ISS2) (3 marks)

3. Identify the feedback topology (3 marks)

4. Derive the feedback network gain (βFB) expression (6 marks)

5. Derive expressions for the Open-loop and Closed-loop: voltage gain, input and

output resistance (20 marks)

6. Suggest a voltage signal processing application for this circuit (2 marks)

Figure 1 Two-Stage CMOS Voltage Amplifier with Feedback topology




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Problem 2: (Op-amp Design & Power Amplifiers: 45 Marks)

Figure 2 illustrates the internal structure of the IC “OPA2314” from “Texas Instruments”

Company. This IC is a CMOS multi-stage op-amp that operates at wide common mode

input & output voltage ranges. The DC biasing circuit block is used to make sure that the

op-amp output is not distorted.

1. Identify and explain the op-amp stages. (10 marks)

2. Write the DC drain currents for each transistor as a function in the biasing currents

(Iref1, Iref2, IB1 and IB2) at zero DC differential input voltage & design the biasing

current sources using NMOS/PMOS simple current sources. (10 marks)

3. Derive the expression for the op-amp differential mode voltage gain at the mid-

band, input and output resistances. (20 marks)

Derive the gain Under the following conditions:

Do not neglect the Early effect

You can assume the matching conditions between the circuit’s transistors

based on your course knowledge

Assume that the output stage gain is unity

4. Simplify & Draw the equivalent circuit model for the given op-amp (5 marks)

Bonus: (Additional 10 marks)

o Explain why this op-amp can work for a wide common mode input voltage range

o Sketch the op-amp output voltage vs. its input voltage. State clearly on the graph

the output stage transistors’ mode of operation.

Figure 2 IC OPA2314 simplified circuit diagram




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Problem 3: (Differential Amplifiers: 40 marks)

Figure 3 shows an enhancement NMOS differential amplifier, assume that the circuit

parameters are: K = 400 μA/V2, VT = 1 V, λ = 0.02 V−1, R1 = 51 kΩ, R2 = 100 kΩ, RS =

7.5kΩ, and RD = 36 kΩ. Calculate the following:

1. The DC drain currents at zero DC input voltage “vS” (10 marks)

2. The differential mode mid-band voltage gain “(vO2 -vO1)/vS”, input and output

resistances. (15 marks)

3. The common mode mid-band voltage gain; i.e. connect M1 and M2 gates together

and apply “vS” as an input voltage signal (7.5 marks)

4. The common mode rejection ratio “CMRR” of the amplifier (7.5 marks)

Figure 3 NMOS Differential Amplifier




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Problem 4: (Current mirrors: 25 marks)

Figure 4 shows a famous current source circuit called “Wilson Current Source”. Derive

expressions for the circuit’s:

1. Current gain “IOUT/IIN” (7.5 marks)

2. Output resistance (Use small signal model, DO NOT use intuitive method) (10

marks)

3. Systematic Error (ignoring Early effect) (2.5 marks)

4. Minimum Input & Output Voltages for proper operation (5 marks)

Figure 4 Wilson BJT current source




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electronic circuits, elct 604 spring semester 2018 · 2018. 5. 15. · iet, electronics department...

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