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Electronic Packaging and

Manufacturing

Level - I Packaging

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Level – I Packaging: Chip to Chip Carrier

Chip carrier

Housing for the thin and fragile chip

Purpose

Protects the chip from environment and abusive handling

Facilitates interconnections from the chip to the pads/holes on the

circuit board

Provides pins/pads for that serve as bases for solder joints

Also involved in the heat transfer process as the first step in the

heat flow path from source to sink

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Chip carrier

Parts of Chip Carrier

Chip

Case

Leads and lead frame

Chip to package bond

Bonding wires

Lid

Many different chip carriers exist

today but they all more or less

conform to this parent structure

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I/O count – Rent’s Rule

The need for pin-outs is

defined by Rent’s rule

a is a proportionality constant –

normally between 0.5 & 1.5

b is a constant that depends on the

functionality of the package

b

GOI aNN /

Examples:

– For low end memory chips, a=6 and b=0.12

– For high end, high-speed mainframe computer logic, a=1.4 and b=0.63

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Key design features of a chip carrier

I/O count

Modern VLSI or ULSI chips have thousands of gates thereby requiring large number of I/Os

Hermeticity

Ensures reliable operation

Entry of moisture is avoided - can cause corrosion of pins, wires

Organic materials that out-gas (release volatiles) with time are not used

Heat Dissipation

Modern circuitry result in very high heat fluxes

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Types of chip carriers

Based on materials

Plastic

Ceramic

Tape

Based on connections

Through hole

Surface Mount

Leadless

Based on I/O layout

Peripheral

Area Array

Flip chip

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Ceramic chip carriers

Ceramic cases

High Cost

Used for products with

Higher I/O count

Stringent hermeticity requirements

Bonding material – Eutectic solder of gold and silicon

Inorganic – does not release volatiles

Melting point is 390ºC

Thermal conductivity is 296 W/m-K

Aids in heat transfer from chip to case

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Ceramic Package – assembly process

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Ceramic Chip Carriers

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Plastic Encapsulated Microcircuit

(PEM)

Consists of an integrated circuit chip physically attached to a leadframe,

electrically interconnected to input-output leads, and molded in a plastic that is

in direct contact with the chip, leadframe, and interconnects.

Used for products with

Low powers

Moderate I/O count

Lenient hermeticity requirements

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PEM Assembly Flowchart

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Dual Inline Package (DIP)

First package (invented in

1960s)

Both plastic and ceramic

Low wattage chips

Fully encapsulated

Pins inserted in holes

• Attached to the underside of the

board by wave soldering

Advantages

Robust pins and connections

Automated assembly – pick and

place machines

Width of pins is increased near

the body – provides a shoulder

Disadvantages

Poor area efficiency

Limited wireability

Limited I/O count (100

mil pitch) mech14.weebly.com

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Types of leads

Pin-in-hole Gull wing type leads

J type leads mech14.weebly.com

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Other Peripheral Packages - SMT

Surface Mount Technology Lower pitch – higher I/O count

No holes required – better wiring

Both sides of the board can be used

Small Outline Package (SOP) Well-suited to 24 – 48 pin memory with space constraints

Similar to DIP with copper lead frames

Quad Flat Pack (QFP) Plastic and ceramic

Lead frames go around the entire periphery

Higher pin counts (up to 300)

There is a push for thin QFPs or TQFP for portable PCs

Ceramic QFPs are used for higher temperature or humid applications

Handling problems – only connections on one side are made simultaneously

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Peripheral packages

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Area Array Packages

Utilizes the entire bottom side of the carrier for

interconnections instead of only the perimeter.

Since area available is higher, it is possible to have

Higher I/O count

Increased lead pitch

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Pin Grid Array (PGA)

Pin Grid Array

Substitute for DIPs

Can handle large I/O count

Usually ceramic body

Pins go into vias (holes)

For high power Surface area below chip is

used for heat sink

Disadvantages Higher cost

Area efficieny is poor as pin pitch is 100 mils

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CPGA package

Source: https://i.stack.imgur.com/H88EF.jpg Source: Intel

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Utilizes small solder balls for connection between

component and motherboard

Active chip can be interconnected to the package by

wire bonding or flip chip technology

Ball Grid Array (BGA)

Bruce Guenin, Electronic Cooling, 2002

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Source: Practical Components

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Advantages of Ball Grid Array (BGA)

Advantages

Improved electrical performance due to shorter distance between

chip and the solder balls

Improved thermal performance by use of thermal vias incorporated

in the substrate

Occupies less board real estate (less package area per I/O)

Reduced handling-related lead damages due to use of solder balls

instead of metal leads.

When reflow attached to boards, the solder balls self align leading

to higher manufacturing yields.

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Disadvantages of Ball Grid Array

Disadvantages

Difficult to inspect formed solder joint after assembly

X-Ray technique used normally – but not effective in determining if a joint is ‘cold’ or ‘wet’.

Other techniques involve fibreoptic light and optical instruments

Keep-out area required in board for such techniques

Source: http://www.bga.net

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Land Grid Array (LGA)

A land grid array (LGA) is an integrated circuit design

involving a square grid of contacts that are connected to other

components of a printed circuit board. The term refers to a

"socket design" where certain components are disconnected

from the actual circuit board and integrated into the board’s structure in particularly new ways. In contrast to most other

designs, LGA configurations have pins in the socket rather

than on the chip.

Definition: Technopedia

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Land Grid Array (LGA)

Source: Wikipedia Source: Intel 771 socket

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Land Grid Array (LGA)

No solder joints/balls

Uses lands and connection pads

Pins on the socket side

Designed for lesser lead usage allowing for better

Restrictions of Hazardous Substances (RoHS)

Advantages

Ease of assembly/disassembly

Thinner and lighter packages

Short electrical path

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Lead Configurations

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Chip scale package (CSP)

A CSP is any package that has a

footprint no greater than 1.2 times

that of the IC

Importance is high due to cell

phones and PDAs

Its greatest advantage is size

reduction

The name, CSP, does not give

details about package construction

The main types of CSP are:

flex circuit interposer

rigid substrate interposer

custom lead frame

wafer-level assembly

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Types of CSPs

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Packaging Efficiency

Packaging efficiency is defined as

Examples:

DIP: 2%

QFP: 5%

BGA/CSP: 30-80%

Bare chip: 100%

Size Package

Size ICEfficiency

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Area efficiency of different packages

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What next?

The best package is no package at all!

Can the manufacturer (semiconductor fab) ship chips with BGAs or flex connectors on a tested and burned-in wafer?

This is called a wafer-level flip chip

The trends for Japanese consumer products show that packages are area arrays, thin and light. Most become wafer-level accessible.

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Flip Chip

A chip packaging technique in which the active area of the chip is "flipped over" facing downward. Instead of facing up and bonded to the package leads with wires from the outside edges of the chip, any surface area of the flip chip can be used for interconnection, which is typically done through metal bumps of solder, copper or nickel/gold. These "bumps" or "balls" are soldered onto the package substrate or the circuit board itself and underfilled with epoxy. The flip chip allows for a large number of interconnects with shorter distances than wire, which greatly reduces inductance.

Source: https://www.pcmag.com/encyclopedia/term/43310/flip-chip

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Flip Chip

Source: https://www.pcmag.com/encyclopedia/term/43310/flip-chip

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Flip Chip - introduction

Bare semiconductor chips are turned upside down and

bonded directly into the motherboard or chip carrier

Connections are made through solder bumps and (solder wettable) pads

High I/O count

All connections can be made simultaneously

Top surface (back side of the chip is available for heat dissipation.

First introduced by IBM in 1962.

Path breaking technology invention

Introduced for ceramic substrates (Solid Logic Technology)

Converted in 1970 to C4 (Controlled Collapse Chip Connection) for ICs

Initially used for peripheral packages but quickly progressed to area

arrays

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Flip Chip - process

Source: Wikipaedia

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Why use Flip Chip?

Small size

Reduced board area, less height, lesser weight

Improved performance – high speed

Eliminating bond wires reduces the delaying inductance and capacitance

Shortens the path by a factor of 25 to 100

Great I/O flexibility

Rugged

With “underfill”, flip chips behave like small blocks of cured epoxy

Availability of materials, equipment and services

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1st level connections

Automated wire bonding

Thermo compression

Ultra sonic

Thermo sonic

Tape automated bonding

Flip chip bonding

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Wire bonding

Wirebonding is an electrical interconnection technique using thin wire and

a combination of heat, pressure and/or ultrasonic energy. Wirebonding is a

solid phase welding process, where the two metallic materials (wire and

pad surface) are brought into intimate contact. Once the surfaces are in

intimate contact, electron sharing or interdiffusion of atoms takes place,

resulting in the formation of wirebond.

Process Pressure Temperature

(C)

Ultrasonic Energy Wire Pad

Thermo-

compression

High 300-500 No Au Al, Au

Ultrasonic Low 25 Yes Au, Al Al, Au

Thermosonic Low 100-150 No Au Al, Au

Two basic wirebonding methods

Ball bonding

Wedge Bonding mech14.weebly.com

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Ball Bonding

Components

Wire

Capillary

Electronic Flame Off (EFO) system

Uses T/C or T/S bonding

Temperature range is 100-500°C

Fine gold wire (75m) normally used

used where the pad pitch is greater than 100m mech14.weebly.com

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Ball Bonding (cont.)

Capillary

Finished bonds mech14.weebly.com

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Wedge Bond

Name is based on shape of the tool

Wire fed at 30-60o from the horizontal bonding surface through a hole in the back of a bonding wedge

Process used is normally U/S or T/S

Al wire – U/S bonding process

Au wire – T/S bonding process

Can be used for smaller pitches Speed is low

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Wedge Bond

Process Wire pinned against die pad

U/S or T/S bond is formed

Wedge ascends and forms the loop

Descends on the substrate and forms the second bond

Wire torn after second bond using clamp tear (wedge stationary) or table tear (clamp stationary)

Source: http://www.westbond.com/wedge_bond_guide.htm

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Video links

https://www.youtube.com/watch?v=xAw7CzuyrV0

https://www.youtube.com/watch?v=mQP9J4iYYtA

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Tape Automated Bonding (TAB)

Process of mounting a die on a flexible tape made of polymer

material, such as polyimide

Mounting is done such that the bonding sites of the die,

usually in the form of bumps or balls made of gold or solder,

are connected to fine conductors on the tape, which provide

the means of connecting the die to the package or directly to

external circuits.

Sometimes the tape on which the die is bonded already

contains the actual application circuit of the die.

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Tape Automated Bonding (TAB)

https://www.youtube.com/watch?v=X104jJNTvuc

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Flip chip bonding

Bumping the die

Attachment to

substrate

Epoxy Underfill

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Flip chip bonding - steps

Formation of solder bumps on the front face of the die/chip Under bump metallization (UBM)

Solder deposited over the UBM by evaporation, electroplating, screen printing solder paste, or needle-depositing

Bumped die placed on substrate pads Wetted controlled collapse interconnection

Solid state bond – uses T/C or T/S bonding techniques

Solder flux helps in removal of oxide and ensures perfect wetting

Under-chip space filled with a non-conductive "underfill" adhesive joining the entire surface of the chip to the substrate

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Bumping the die

Formation of solder bumps on the front face of the die/chip Under bump metallization (UBM)

Solder deposited over the UBM by evaporation, electroplating, screen printing solder paste, or needle-depositing

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Under Bump Metallization

Under Bump Metallization (UBM) is an essential step

where the connection pads are coated/sputtered with a

metallic layer

IC connection pads typically Al (oxidation, non wettable, non – solderable)

UBM layer produces a good bond to the aluminum pad, hermetically seals

the aluminum, and prevents the potential of diffusion of metals into the IC

package

Methods

dry vacuum sputter method combined with electroplating - multi-metal

layers sputtered in a high temperature evaporation system

Electroless Nickel/Immersion Gold (ENIG) - consists of wet chemical

processes

http://www.uyemura.com/under-bump-metallization-to-reduce-wafer-processing-costs.htm

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Bumping process

Source: Dorogi et al. (2006) “Advances in Metal Deposition for Wafer Bumping”, Solid State Technology

Source: http://www.practicalcomponents.com

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Solder Bumps

http://www.faradaysolutionsllc.com/images/solder-bumps.gif

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Attachment to the Substrate

Bumped die placed on substrate pads Solder is “reflowed” – typically using hot air reflow

soldering process

Solder flux helps in removal of oxide and ensures perfect wetting

Image: Wikipaedia

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Flip Chip - process

Source: Wikipaedia

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Underfill

Underfill needle-dispensed along the edges of each chip

drawn into the under-chip space by capillary action

heat-cured to form a permanent bond

Why is underfill required? compensate for any thermal expansion difference between the chip

and the substrate - mechanically "locks together" chip and substrate so that differences in thermal expansion do not break or damage the electrical connection of the bumps.

protects the bumps from moisture or other environmental hazards

provides additional mechanical strength to the assembly

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Underfill steps

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Underfill Process

Capillary Flow Injection Flow

Compression Flow

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Summary

Flip Chip Technology – one of the most significant

advances in Electronic Packaging

3 steps

UBM

Attachment to substrate

Underfill

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Advanced Packaging

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Advanced Packaging

Incessant need for faster,

lighter cheaper and better

electronics

Shrinkage in footprint and

form factor

Need for advanced designs,

methods

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Multi-chip Module (MCM)

Multiple chips on the same substrate/package

Source: Intel Corporation

Source:

https://arstechnica.com/gaming/2012/10/nintendo-

does-its-own-wii-u-teardown-shows-off-multichip-

module-design/

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System on a Chip (SoC)

Multiple functions are

implemented on a single die

Highest performance at lowest power

extremely complex

Possibilities

one or more processor cores, memory

blocks, peripheral functions, and

hardware accelerators, all created on

the same piece of silicon

digital logic, memory, and analog/RF

functions all on the same die

Source: https://www.eetimes.com/document.asp?doc_id=1279540

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System in Package (SiP)

Chip-scale package (CSP) devices mounted on a common

substrate used to connect them all together.

Substrate and its components then placed in a single package

Possibilities

can include analog, digital, and radio frequency (RF) dice in the same

package, where each die is implemented using that domain's most appropriate

technology process

Source: https://www.eetimes.com/document.asp?doc_id=1279540

Source: Octavo Systems Source: STATS ChipPAC

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2.5D integration

Silicon interposer placed between the SiP substrate and the die, where this

silicon interposer has through-silicon vias (TSVs) connecting the

metallization layers on its upper and lower surfaces. Substrate and its

components then placed in a single package

Advantages

Overcomes the problem of mismatch in wiring tracks in die and SIP substrate

Increase in capacity and performance

Source: https://www.eetimes.com/document.asp?doc_id=1279540

Xilinx Virtex-7 2000T

Source: http://www.techdesignforums.com

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3D integration

Mount two or more dies on top of each other

Source: GIAN course by Prof. A Dasgupta, 2018

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Package on Package (PoP)

Source: GIAN course by Prof. A Dasgupta, 2018

Allow one peripheral package on top of another

Tessera Folded Package

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Summary – Advanced Packaging

Multi Chip Module (MCM)

System on a Chip (Soc)

System in Package (SiP)

2.5D and 3D integration

Package on Package (PoP)

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Summary – 1st level packaging

Interconnect technology

Types of packages

Wire bonding

Tape Automated Bonding

Flip Chip Bonding

Advanced Packaging

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References:

“Packaging of Electronic Systems”, James W. Dally, McGraw-Hill Education,

1990

“Fundamentals of Microsystems Packaging: R. R. Tummala, McGraw Hill, 2001

Essentials of Electronbic Packaging – A Multidisciplinary Approach”, P

Vishwanadham, ASME Press, 2011

Chanchani R., Integration Technologies – An Overview. In: Lu D., Wong C. (eds)

Materials for Advanced Packaging. Springer, Boston, MA, 2009

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