EML 4561Introduction to Electronic Packaging

W. Kinzy Jones, Professor MME

MWF 11:00-11:50

Jones@fiu.edu

305-393-0506(mobile)

305-348-4663 (office)

Notes on the field• I am Past President and Fellow, IMAPS, The

Microelectronics and Packaging Society• Research in advanced packaging, 1st Level

Assembly, Thermal Management, Components and Electronic Materials- Funded over $7MM in past 15 years

• Electronic packaging is a application field that crosses over many disciplines. There are 80,000 ME working in the field. Conferences/journals by ASME, IEEE, ASM, IMAPS, etc.

• All former graduate student hired prior to graduation!

Outline• Technological Drivers• Design Process

– Electrical Consideration– Mechanical Constraints– Thermal Management– Material Science Fundamentals

• Interconnect Technology – Laminate technology – Ceramic Processes ( thick film, cofire ceramic)– Thin Film Deposited

Outline (Cont.)

• Components– Active components technologies– Passive Components technologies– IC Packaging ( from DIP to System-on-package (SOP))

• Assembly– First Level Assembly ( wire bonding, flip chip)– Soldering– Manufacturing Processes

• Reliability– MIL Standards– Reliability Projections

Introduction to Microsystems Packaging

Definition of Packaging

Board

IC

Packaging is a

Bridge from ICto System

It Controls:• >90% size

• Performance

• Cost

• Reliability

Packaging Hierarchy

Microsystems Technologies

System Packaging Involves Electrical, Mechanical and Materials Technologies

Analogy Between Human and Electronics

Trend to Convergent Microsystems

Discrete Systems

Past Future

Packaging

MEMS

Microelectronics Photonics

RF

Bioelectronics

ConvergentMicrosystems

Building Block of Microsystems Packaging

1975 1995 2015

Year

1

10

100

1000

10000WW S/C Revenue ($B)

Trend to Convergent Systems

BusinessesHost-based computingMainframeDumb terminalFew vendors / architecture

Mainframes

Transistors / chip

1B

1M

10M

100M

10B

100K

10K

1K

100B

PCs

PCs / Servers

Businesses & some peopleClient-server computingLocal area connectionText/graphical interfaceMany vendors / few architectures

Today

All businesses, people, objectsNetwork computingWide area / bandwidthGraphical, voice, multimedia, etc.Many vendors / platforms

Internet

Source: Russ Lange, IBM Microelectronics

• Wireless• Wired

Convergent Systems

What are Convergent Microminiaturized Microsystems (CMM)?

• Convergent: Two or more functions• Microminiaturized: >1000x volume

reductions• Microsystems: systems with micro-scale

technologies

Trend to Convergent Microminiaturized Systems (CMM)

• Functional – Data and Voice

• Technology – Digital, RF, Analog

and Optical

• Product– Computer, consumer

and telecom

Video Cell Phone

CONSUMERELECTRONICS

Medical Implant/ Diagnostic Monitor/

Communicator

MEDICAL

The Invention of the First IC

Moore ’s Law: Doubles Every 18 Months

Source: Hal Lasky, IBM Microelectronics

CMOS with Copper Wiring and Silk

Silicon- on- Insulator (SOI)

Conventional Bulk CMOS

Silicon on Insulator (SOI)

Source: Hal Lasky, IBM Microelectronics

Silicon- Germanium BICMOS

• SiGe Offers– Cost/Performance for High

Frequency Devices

– 300-500% Performance Gain

– Low Noise, High Linearity

– Lower Power than Bipolar

– Equivalent Speed to GaAs at a Fraction of the Power

Source: Hal Lasky, IBM Microelectronics

SOC Advances

SOI

SiGe

Cu - low KMoore’s Law

SOC Presents Integration Limits in RF RF is Bottleneck for Highly Integrated

Wireless Systems

• Future wireless systems have to be portable and battery-powered

• Reduction of size, weight, power cost

• High level of integration

• Passive components in RF front-end are difficult to integrate, expensive and bulky

RF is Bottleneck

Traditional Front-ends are Bulky

Several GaAs or Si bipolar RF chips

Expensive external passive RF and IF bandpass filters

Many discrete passives: inductors, capacitors, resistors

DSP

Timing recovery

demodulation symbol

decoding- - -

LNA

LO1 LO2

ADC

High-QIF BPF

Front-End ICs are Mixed ICs

Complete Single-chip Integration Not Feasible

Technology scaling allows CMOS RFBUT: lower performance than e.g. GaAs, some blocks cannot be integrated

On-chip inductorsBUT: low Q

LNA LO

ADC

Mixed-signal integration in CMOS BUT: substrate noise coupling

FIR

900

ADC FIR

DSP

Timing recovery

demodulation symbol

decoding- - -

Single chip Integration with High Performance Not Feasible

Front-End IC’s are Mixed IC’s

Traditional Front-ends are Bulky

Single Chip Integration with High Performance Not Feasible

RF is Bottleneck for Highly Integrated Wireless Systems

• Future wireless = portable, battery powered

• Reduced size, wt., power cost• Highly integrated

• Passive comp. in RF front-end: difficult integration, expensive, bulky

SOC Presents Fundamental Digital Limits

~ 100 ps~ 1 ps.05 m

~ 1 ps~ 10 ps1.0 m

Response Time

Lint = 1mm

MOFSET Intrinsic Switching Delay

Technology Generation

Results in Major Delay Problem

Del

ay (a

u)

Technology Generation

MOS Gate

Local Wire<100um

Global Wire>1 mm

SOC ChallengesMajor Delay Problems

Summary

Fundamental Digital LimitsIntegration RF Limits

• Fundamental• Design & Verification Complexity• Test Complexity• Process Complexity• Mixed Function Costs• Wafer Fab Costs• Legal Problems• Time-to-market

SOC: Integration of Two or More Mixed Functions in a Single IC

(a) (b)Slide # 26

SOC Expectations

Source: Hal Lasky, IBM Microelectronics

RF-IC

OE-IC

ASICS

U Processor

DRAMStorage

Capacitance

FlashHigh Voltage

Tunnel Oxides

SRAMDense FeaturesImaging

Light Sensitive Devices

DSPSystem Integration

VLSI is Progressing Beyond the Needs of Individual Components

Bulky Size

1970 1980 1990 2000

Year

1

2

3

4

Total System-levelPackaging

Semiconductor Cost

What is Wrong with Current Packaging for Tomorrow’s Needs?

Higher Cost

Poorer Reliability

• Active ICs 10%• Passives: 90%

• IC: PPB• Systems Pkg: PPM

Cellular PhoneWeight Trend

Barrier to all future systems

Lower Performance

What is SOP, SIP, or Board?

A.) Today’s Board: Interconnect Components

RF IC Digital IC

Substrate

Optical IC

IC

B.) SIP: Stacked Chip/Package for Reduced Form Factors

Flash

RAM

mPIC

Package

Super IC Stack (ASET) Package (Fujitsu) Stacked IC (Amkor)

C.) SOP: Optimizes Functions Between ICs and Package

RF IC Opto IC Digital IC

Package with Opto, RF, Digital Functions

RF Opto Electrical

3-D ICs

What are SOC, SIP, and SOP?• SOC: System on Chip

– Highly integrated and mixed signal IC with partial system functions in one component

• SIP: System in Package– 3-D IC or Package Assembly– Requires Systems Board

• SOP: System on Package– Microminiaturized system-level board with two or more embedded

RF, digital, analog and optical functions– Best of on-chip and package integration for cost, performance, size

and reliability– Similar to SOC but total system function in a microminiaturized

board

SOP: SIP + SOC+Systems Board

• 3 -D Stacking of ICS or Package Structures, Similar to PWB– Macro dimensions– Vertical stack up– Testable

• 3 -D Build up, similar to IC Fabrication– Micro to Nano dimensions– Sequential build up and test

similar to MCM-D and IC– Wafer to IC concept for high

yield

SIP SOP

MEMS Ga-As SIPSOC

SOCMEMS SIPGa-As

Why SOP?• SOC is complex to design and test, expensive

to Fabricate, long time-to-market and presents fundamental limits.

• IC company’s dream for decades. No complete system has been shipped to date.

• SOP optimizes the best of IC and package integration for cost, performance, size and reliability.

• Faster turn-around and faster time-to-market.• Provides full system solution today that SOC

provides tomorrow.• SIP is a 3-D IC or package, not a complete

system

Industrial &

Medical

11%

$105B

Military

9%

$ 8.7B

Automotive

5%

$ 48B

Business Equip

38%

$ 383B

Communications

26%

$ 259B

Consumer

26%

$112B

Information Technology is a Trillion $ Industry

Microsystems & Packaging is 25% of IT

Source: Prismark

MSP Market ($320 B)

Microelectronics ($165B)

Systems Packaging ($125B)

Opto & MEMS ($30B)

Information Technology and Microsystem Markets

Bil

lion

$/Y

ear

Hardware and Software Markets

Functions of Packaging

Package Interconnections

Core Technologies• Substrates, circuit boards• Interconnect• Passive components• Active components• Packaging

Traditionally these were treated as discrete elements Advanced applications require integrated approach of

System Level Packaging

Substrates and Circuit Boards• Printed Circuit Board (PCB), Printed Wiring Board (PWB)

– Epoxy-glass composite, copper– FR-4, FR = fire retardant– Advanced Resins

• Polyimide • BT = bismaleimide traizine• CE = cyanate ester

• Ceramic substrates– Aluminum oxide, aluminum nitride, beryllium oxide, glass-ceramic– Interconnect metals - W, Mo, Au, Cu, Ag

• Multichip Modules– MCM-D,C,L

• Platform – Support interconnect and components– Thermal path away from ICs– Withstand mechanical stresses and vibrations

Packaging Evolution

?

Microelectronic Density Trends

logic

microprocessors

Rent’s Rule

Packaging Evolution

I/O Density Trends

Chip

Package Evolution

Packaging Trends (Cont.)

Assembly Processes• Board Fabrication

– Single layer– Multilayer– PCB– Flex– Ceramic

• Populating the board– Pick and place– Insertion– Die attach

• Soldering– Solder paste reflow– Wave solder– Solder bump reflow

• Encapsulation

SIA Roadmap for Chip Interconnections, 1995

CMOS Device Trends

Buda et al, 42 CPMT, pp36-41, 1992

NEMI Roadmap, 1996

Packaging trends in Automotive Electronics

Packaging trends in Consumer Electronics

iNEMI Roadmap, 2009

NEMI Roadmap for Packaging Trends in High-Performance Systems

High Performance Systems, iNEMI 2009

Interconnect Density, Std. PWB

.1mm = 4 mils

Thermal Cooling Requirements

Types of First Level Packages

Chip-Scale Packages

Types of Ball Grid Arrays

Flip Chip Assembly

Chip

Substrate

Example- Controlled Collapse Chip Connection-C4 (IBM) assembly on ceramic substrate

Solder• Primary functions

– Electrical connection between component and interconnect– Mechanical attachment of component to board– Thermal path from component to board

• Alloys of various compositions and melting points• Lead-Tin solder most common

– Eutectic composition: 63% Tin, 47% Lead– 60/40 or 2% silver added

• Solder paste for screen printing, pressure dispensing– Alloy particles– Flux and activator chemicals– Vehicle to control viscosity

• Wave soldering– Foam or spray flux– Preheat board– Turbulent wave to spread solder– Laminar wave to smooth

Effect of Underfill on Temp Cycling Performance

With filler, 27ppm

Functions of a Multichip Package

Illustrations of MCM Types

Low Temperature Cofired Ceramics with Buried

Components

Packaging Efficiency

Packaging Considerations that Effect the Electrical Performance

Interconnects Worsen:

• Signal Integrity• Performance: switching, speed• Reliability• Form, fit, and function- weight, volume,

power

Interconnects Can Have Very Important Electrical Properties

• Property• Self-inductance• Capacitance to ground• transmission line

• Mutual Inductance, capacitance

• Resistance, loss

• Possible Impact• Ground bounce• Delay, power sag• Propagation delay,

reflection• Cross-talk, noise

• Damping, ringing, power sag

Drivers for Reduction of Interconnect Length

• Directly reduces inductance, capacitance, resistance and delay

• Indirectly reduces switching time, power, size, ringing, ground bounce, and power sag

Electrical Fundamentals

• Resistance ( ohms). Relates Ohms law relationship between current and voltage, V=IR. Resistivity, , is a materials property, in ohm-meters. Resistance, R = Length x / cross-sectional area of conductor

• Capacitance (farads) relates to the ability to store charge. Capacitance for a parallel plate capacitor is proportional to the dielectric constant,K, times the area of the plate/ thickness of dielectric.

• Inductance ( henry)- relates to the voltage generated to oppose a change in current

Basic Resistance Equation

• Resistance R = L / A = L /wt = L/w Rs

where Rs is defined as the sheet resistivity, is resistivity, L is the length and A is the cross sectional area of the conductor/resistor

• A square ( L=W ) for a fixed thickness of material has a fixed resistance per square, independent of size. A square anything

Capacitance is• In the insulation between more than one conductor• Orders of Magnitude higher outside the chip than

inside• The dominate determinant of digital speed

Dielectric Constants of Some Insulators

Dielectric Material Type DielectricConstant, K

FR-4 epoxy 4.8

PTFE floropolymer 2.8

Alumina ceramic 9.0

PVF2 Polymer 12.0

air 1.0

Capacitance of Electrically Short Interconnections

• Capacitance is the sum of all output capacitance of all drivers to that interconnect, the input capacitance of all receivers, and the distributed capacitance to ground of the interconnection

Switching Time, Power

• If a step voltage is applied to an RC network, the time delay is proportional to RC. If the capacitor is charged from zero to full charge, the energy dissipated, W, is independent of R and equals CV2/2. But energy is also power X time delay. If we operate twice as fast, the circuit will dissipate twice the power.

Inductance• Opposes a change in current by generating a back

voltage. If the current change is positive, the back voltage subtracts from the voltage applied, causing a power sag.

• The voltage is equal to the inductance times the rate of change of the current , VL= L di/dt

• Self inductance exists in every wire, trace, wire bond, solder joint, etc..It is minimized by large, short conductors, or a sheet conductor as a ground or power plane.

• Example: If we switch 1 amp in 5 nsec on a 1” trace with 7.8 nH, we generate a back voltage of 1.6 volts.

Crosstalk

• There is a mutual capacitance between two adjacent insulated conductors that couples a fraction of one voltage to the other

• There is also mutual inductance, functioning as a transformer by generating a voltage in each when the current changes in the other.

• This is crosstalk. Can be minimized by design (keep talkers and listeners apart) and use of ground/power traces between talkers/listeners

Ground Bounce, Power Sag

• Cause: Common-mode impedance, usually inductive• Digital devices require most of their power supply

current during switching. Clocked signals switch together, so there could be a large total surge

• The inductance in the power and ground leads causes ground bounce and power sag.

Bypass ( decoupling) Capacitors

• To reduce power sag and ground bounce, add decoupling capacitors. Value should be 20-100 nF/sq.cm of silicon. Decoupling capacitors should have low parasitic inductance.

• Capacitors serve as local energy reserves and need to be close to the power/ground leads

RLC Circuit Switching

• The voltage step sent down an interconnect can be distorted badly by the R, C, and L on the interconnect

• This distortion can be removed by the right balance of the values of R,L and C. When R = 2* sqrt(L/C), critical damping occurs

• If R is above critical damping, switching slows down; if below, ringing of the signal occurs

Critical Damping

Transmission Lines• Any interconnect whose length is over a

small fraction of the wavelength of the signal it carries acts like both a transmission line and an antenna radiating or receiving noise

• As speed increase, the lumped analysis of L,R,and C components must be replaced by the distributed network of L,R, and C.

• Property shielded interconnects minimize the effect of antenna properties, but the transmission properties remain

Transmission Line Properties

• A transmission line appears as a string of small inductors and capacitors, with seven principal properties:

• length L, inductance per unit length, capacitance per unit length, impedance (Z), attenuation, propagation velocity, and time delay

Transmission Line Equations

Transmission line traces

• Matched impedance systems require containment of the electrical fields. This has lead to designs including the stripline, the microstrip, the buried microstrip. Additionally, for multilayer routing, vias must be considered

• Stripline microstrip

Microstrip Design for 50 Impedance

Traveling Waves on an Infinite Line• Switching on a DC source voltage, V, :

–draws the same current as a resistor of value Zo connected to V.

– current flows down the line at the propagation velocity, while the current progressively charges up the line capacitance to voltage V. Hence a voltage step V also travels down the line.

–Draws current indefinitely due to an infinitely long line

–The source only sees a resistive load Zo continuously drawing current

Traveling Waves on an Unterminated Line• When the line is unterminated ( R is infinite):

– Kirchoff’s current law still applies at the far end: the sum of current entering the end must equal the current leaving the end. But there is no load to draw current from the end node.

– Therefore, an equal reflected current wave is generated that travels back toward the source.

– This reflected current wave requires an extra voltage source, V, to propel it, so the voltage at the far end steps up to 2V.

– This increased voltage travels back towards the source along with the reflected current.

– What happens at the source depends on the source’s internal impedance

– The waves can on occasion reflected back and forth several times

Lines Traveling Waves Capacitively Terminated

• The problem of reflection is compounded by capacitance at the ends.

• When a transmission line drives a capacitor, the extra capacitance causes:– reflections, since the line is now mismatched– ringing for some drivers, since there is no

longer critical damping• CMOS inputs are essentially capacitive.

AC Termination

• To minimize power dissipation, a series capacitor,C, can be added to the terminating resistor

• This terminated the line only when a voltage transition occurs and allows no DC power dissipation in R

• The value of C must be selected carefully, either by simulation or experimentation to minimize the effect of capacitively terminated lines.

When Interconnections are Electrically Significant

• When interconnects degrade switching time• When the signals are not correctly damped• When large amounts of current switch• In the time domain, when the line propagation

delay approaches the driver switching time. Propagation delay is proportional to length

• In the frequency domain, when the wavelength of the signal ( including harmonics) are not long compared to the length of the interconnect ( for 100 Mhz- over a few centimeters)

Packaging• What packaging provides:

• Interconnection• Power Distribution• Thermal Management• Environmental Protection

• What the package is made from--materials, parts

• What is used to design and fabricate packages:

• Facilities and Equipment• Manufacturing and Design Tools

• Process by which the package is produced over time

Technology Drives

• Increases in semiconductor complexity from decreased feature size

• Corresponding increases in systems speed• Increase in input/output (I/O) density• Increase in power density (W/cm2)

Levels of Packaging• 1st Level Connection

– IC to Common Circuit Base– Wirebonds or solder bumps to package base

• 2nd Level Connection– Common Circuit Base to Circuit Board– Package leads soldered to PCB

• 3rd Level Connection– Assembly of multiple boards into larger assembly– Video card, modem, game port on a PC motherboard

• 4th and 5th Level Connections– System level assembly with several 3rd Level subassemblies– Motion control, visual alignment, user interface, etc. in manufacturing equipment