emt 241/3 introduction to ic layout semester ii 2007/08 school of microelectronic engineering...
TRANSCRIPT
EMT 241/3 INTRODUCTION TO
IC LAYOUT
Semester II 2007/08
School of Microelectronic Engineering
Universiti Malaysia Perlis
Razaidi [email protected]
04 979 8253 (office)
019 4464645 (mobile)
IC Design Lab, Level 9, Bangunan KWSP, Kangar, Perlis
TEACHING ENGINEER
Module Aims
Teaching Plan EMT251
Learning Outcomes
Students will be able to analyze CMOS transistor characteristics.
Students will be able to produce the layout design of a circuit based on the design rules specified.
Students will be able to design and simulate logic circuits at transistor level.
Students will be able present their mini project individually in a viva session.
Course Contents
• Transistor structures– Bipolar– nMOS– pMOS – CMOS.
Course Contents
• Static CMOS logic circuit design– pMOS and nMOS representations as switches – Design of Simple gates– complex logic gates
Course Contents
• Introduction to Layout – Masks and layout drawing as circuit
representations – Sticks diagram – Design rules – Multilayer interconnections
Course Contents
• Chip Design Concepts– Building blocks– chip layout – Design Rules Check – Layout versus Schematic
Lab 1, Week3 : Introduction to Zeni tools
Lab 2, Week4 : Netlist
Lab 3, Week5 : Schematic design
Lab 4, Week6 : Layout design
Lab 5, Week7 : Design Rules Check (DRC)
Lab 6, Week8 : Layout Versus Schematic (LVS)
Lab 7, Week9 : Parasitic Extraction (PEX)
Week15: Viva & Presentation
Laboratory (IC Design Lab, Jalan Sarawak)
1) Kang, Sung-Mo and Leblebici, Yusuf, CMOS Digital Integrated Circuits- Analysis and Design, McGraw-Hill, 2005 (Text book).
2) Hodges, David A. et al, Analysis and Design of Digital Integrated Circuits in Deep Submicron Technology, Mc-Graw-Hill, 2004.
3) Neil H.E. Weste and Daid Harris, CMOS VLSI Design- A Circuits and Systems Perspective, Prentice Hall, 2005.
4) Uyemura, J. P., Introduction to VLSI Circuits and Systems, John Wiley, 2002.
5) Rabaey, J. M. et al, Digital Integrated Circuits – A Design Perspective, 2nd Edition, Prentice Hall, 2002.
Reading Lists
Tutorials Sessions
Tutorial I• Netlist
Tutorial II• Schematic
Tutorial III• Layout
Theoretical Test
Test 1• TBA
Test 2• TBA
Examinations
• 6 Questions
Answer 5 Questions
Three (03) hours
Assessments
Course Work – 50%Tests (2) : 20%Assignment :5%
Lab :5%Mini project:10%Lab Test: 10%
Final Exam – 50%
Expectations
Attend classes and labs.Find out what you’ve missed if you’re
absent.Come earlier than the lecturer/engineers.Log on to portal regularly.Ask lecturer/engineers whenever have any
problems related with the subject.
WHAT IS IC?
ICs on PCB
IC Package
Inside ICWafer
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IC Layout
IC Schematic
Why VLSI?
• Integration improves the design– Lower parasitics = higher speed– Lower power consumption– Physically smaller
• Integration reduces manufacturing cost - (almost) no manual assembly