enabling the ai era with new materials

Applied Materials External Use

Enabling the AI Era with New MaterialsFirst Material Change in the Transistor Contact and Interconnect in 20 years

Kevin MoraesVice President, Product Management

Semiconductor Products Group

June 5, 2018

*All trademarks used in this document that are not owned by Applied, are the property of the respective owners.

| Applied Materials External Use

Forward-Looking Statements

This presentation contains forward-looking statements, including those regarding Applied’s

products, industry outlooks, technology transitions, and other statements that are not

historical facts. These statements are subject to risks and uncertainties that could cause

actual results to differ materially from those expressed or implied by such statements and

are not guarantees of future performance. Information concerning these risks and

uncertainties is contained in Applied’s most recent Form 10-Q and other filings with the

SEC. All forward-looking statements are based on management's current estimates,

projections and assumptions, and Applied assumes no obligation to update them.

2

| Applied Materials External Use3

PC + Internet Era

Mobile +Social Media Era

AI +Big Data Era

AI: The Biggest Computing Wave Yet


Challenge: “Classic” Moore’s Law is Slowing

Source: Computer Architecture: A Quantitative Approach, Sixth Edition, John Hennessy and David Patterson, December 2017, Applied Materials internal analysis

Chart is for illustrative purposes only, not to scale.

4

Perf

orm

an

ce (

vs V

AX

-11/7

80)

as m

ea

su

red b

y t

he

SP

EC

inte

ge

r b

en

ch

mark

s

3.5%

per

year12%

per

year

23% per

year

52% per year

25% per

year

1978 1982 1986 1994 1998 2006 2010 20181990 2002 2014

Limits of Dennard Scaling

Limits of Parallelism of Amdahl’s Law

End of “Classic” Moore’s Law

Pe

rfo

rma

nc

e (

vs

VA

X-1

1/7

80

) a

s m

ea

su

red

by t

he

SP

EC

in

teg

er

be

nch

ma

rks

100,000

1

10

100

1,000

10,000


‘90s ‘00s ‘10s ‘20s

AI Era Needs Materials Engineering

Poly-Si, W, Al

High-k Metal Gate

Mate

rials W, Cu W, Cu (Co Encapsulation) Cu (w/ Co), Co, New Metals

Materials-Enabled

Patterning

Planar

FinFET

Gate-All-Around

Arc

hitectu

re

Lithography

Self-Aligned Double/Quadruple Patterning (SADP, SAQP)

EUV (+SADP, SAQP)Scalin

g

5


“Classic” Moore’s Law

shrinking of a small number

of easy-to-integrate

materials simultaneously

improves chip performance,

power, area/cost (PPAC)

Single Process Systems

“Classic” Moore’s Law hits

physical limits of original

materials; more challenging

new materials enable PPAC

to continue

Integrated Process Systems

Exotic new material

combinations systematically

engineered at the atomic

scale to enable AI with novel

architectures and devices

Integrated Materials

Solutions

Era 1 Era 2 Era 3

Materials

Systems

6

AI Era Requires New Materials and System Strategies


Virtually Every Chip Engineered on Applied’s Platforms

Endura®Centura® Producer®

Launched 1990

>5,000 Shipped

Launched 1998

~5,000 Shipped

Launched 1982

>6,000 Shipped

7


Evolution of Applied’s Materials Engineering Platforms

PVD PVD

ALD

CVD CVD

ALD

PVD

CLEAN CLEAN

PVD

PVD PVD

PVD

Endura®: Single Process System Endura: Integrated Process System

Four Unique Processes in Vacuum

8


Applied: Largest Set of Materials Engineering Capabilities

Dual Damascene

Packaging Plating

RF PVD

MC PVD

DC PVD

Ionized PVD

Pulsed DC

Next Gen RP Epi

RP Epi

ATM Epi

Plasma Doping

Medium Current

High Current

High Energy

Mask Blank Cleans

CMP Pre-Clean

Brush Box

IPA Marangoni SRD

Standard

Dual Mode

Triple Platens

Dual Platen

RP Thermal

Decoupled Plasma Backside Thermal

Laser Anneal

ATM Thermal

Laser Anneal

UV CureSpatial ALD

Thermal CVD w Plasma

Radical Enhanced ALD

ALD Funnel

Thermal CVD

A B

Radical Enhanced Plasma

CCP Plasma

ICP Plasma

Chemical Clean

Spatial ALD

A B

ALD funnel

Thermal CVD

Radical Enhanced CVD

HD Plasma CVD

Plasma Enhanced CVD

Optical Wafer Inspection

eBeam Review

eBeam Metrology

eBeam Inspection

Optical Mask

Inspection

DepositModify

and AnnealAnalyze

DRY CLEANS DEGAS PVD

METAL

CVD/ALD EPI PLATING

Dielectric

CVD/ALD POLISHING Etch WET CLEANS IMPLANT

NITRIDATION/

OXIDATION ANNEALS

METROLOGY/

INSPECTION

CleanPlanarize, Etch and

Wet Remove

Radical Enhanced

CCP Etch

ICP Etch

Mask Etch

9


The First Conducting Material Change in 20 years

▪ Lower resistance at small dimensions

▪ Excellent gap fill capability

▪ Works with thinner barriers

▪ Improved reliability versus copper

▪ Production-friendly technology

27

Cobalt

Co58.9332

10


Tungsten Contacts and Copper Local Interconnects

Bottleneck Transistor Performance

11

Transistor Contact

Transistor

Interconnect Layers

(M2 – M10+)

Source: TechInsights 2017 report on Samsung 10LPE FinFET

Local Interconnects

(M0 – M1)

Cobalt Unlocks Performance of Transistors at 7nm and Below

≥10nm ≤7nm


8nm

3nm

Physical limit

16m

11nm

6nm

0

4

8

12

16

20

810121416182022

Co

nd

ucti

ng

Meta

l W

idth

(n

m)

Transistor Contact Critical Dimension (nm)

Tungsten Transistor Contacts Have Hit Scaling Wall

Cobalt Contacts Enable Transistor Performance in the AI Era

12

Tungsten Contact

Cobalt Contact

3.7x Increase in

Conducting Volume


0 10 20 30 40

Lin

e R

esis

tivity (

µΩ

-cm

)

Trench Critical Dimension (nm)

Applied Materials Internal Resistivity Benchmark

Cross Over at ~10nm CD

Co

Cu

Copper wires have

lower resistance

Cobalt

wires have

lower

resistance

Copper Local Interconnects Now Throttle Performance

Replacing Copper with Cobalt Unlocks Full Potential of Transistors at 7nm Foundry Node

13

Less Scattering and Vertical Resistance for Cobalt Dual Damascene


1.00

1.05

1.10

Cobalt

1

10

100

Tra

nsis

tor

Co

nta

ct

Resis

tan

ce

(No

rmalized

Oh

ms)

Cobalt Reduces Contact Resistance and Lessens Variability

14

15nm transistor contact to Si

87%Median: 1.05

Variability: 0.06

Median: 8.59

Variability: 10.32


0

4

8

12

16

48121620

Transistor Contact (nm)

Sig

na

l S

pe

ed

Im

pro

ve

me

nt

(%)

Compares Cobalt with

Tungsten Transistor Contacts

Excludes Via and M1 effects

Cobalt Delivers Up to 15% Chip Performance Improvement

15

Transistor

Contact Plug

Via

M1 Line Current

OUTIN

Inverter

Applied is Assessing Design Impact of

New Materials using EDA Simulations

Cobalt Improves Circuit PerformanceSimulation Based on Ring Oscillator

Benefits of Cobalt Increase

as Critical Dimensions Shrink


Cobalt Breakthrough Enabled by Integrated Materials Solution

16

PVD Co

ALD TiN

CVD Co

PVD Ti

Anneal

PVD Co

Analyze

Solution Utilizes/Leverages Four Applied Material Platforms

Planarize

Surface Preparation

Reflexion LK Prime®

Endura®

Producer®

PROVisionTM


Applied’s SAM Opportunity is Growing

17

Foundry Node

1 Layer

~10 Layers

1 Layer

Transistor

28nm

~1 - 3 Layers

1 Layer

Transistor

~11- 13 Layers

7nm

*Includes transistor contact, interconnects and anneal; excludes metal gate, CMP, and inspection

SAM Increases

~2.7x*


Summary: Enabling the AI Era with New Materials

18

▪ AI is the biggest computing wave yet

▪ Need for performance is accelerating just as

Moore’s Law is slowing

▪ Materials engineering is the way forward

Applied will help enable the AI era

▪ Broadest set of materials engineering technologies

▪ Our proven platforms enable multiple processes

to be integrated under vacuum

▪ Applied’s Integrated Materials Solutions allow

new materials and structures to be brought to

market faster and better than ever before

enabling the ai era with new materials

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