energy measurment ic
TRANSCRIPT
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Copyright Cirrus Logic, Inc. 2011(All Rights Reserved)http://www.cirrus.com
CS5463
Single Phase, Bi-directional Power/Energy IC
Features
Energy Data Linearity: 0.1% of Readingover 1000:1 Dynamic Range
On-chip Functions:- Instantaneous Voltage, Current, and Power
- IRMSand VRMS, Apparent, Reactive, and Active
(Real) Power
- Active Fundamental and Harmonic Power
- Reactive Fundamental, Power Factor, and Line
Frequency
- Energy-to-pulse Conversion
- System Calibrations and Phase Compensation
- Temperature Sensor
Meets accuracy spec for IEC, ANSI, JIS.
Low Power Consumption
Current Input Optimized for Sense Resistor.
GND-referenced Signals with Single Supply
On-chip 2.5 V Reference (25 ppm/C typ)
Power Supply Monitor
Simple Three-wire Digital Serial Interface
Auto-boot Mode from Serial E2PROM
Power Supply Configurations:VA+ = +5 V; AGND = 0 V; VD+ = +3.3 V to +5 V
Description
The CS5463 is an integrated power measure-ment device which combines two analog-to-digital converters, power calculationengine, energy-to-frequency converter, and a
serial interface on a single chip. It is designed toaccurately measure instantaneous current and
voltage, and calculate VRMS, IRMS, instanta-neous power, apparent power, active power, and
reactive power for single-phase, 2- or 3-wirepower metering applications.
The CS5463 is optimized to interface to shunt re-sistors or current transformers for current
measurement, and to resistive dividers or poten-tial transformers for voltage measurement.
The CS5463 features a bi-directional serial inter-face for communication with a processor and a
programmable energy-to-pulse output function.Additional features include on-chip functionality
to facilitate system-level calibration, temperaturesensor, voltage sag detection, and phase
compensation.
ORDERING INFORMATION:See Page 45.
VA+ VD+
IIN+
IIN-
VIN+VIN-
VREFIN
VREFOUT
AGND XIN XOUT CPUCLK DGND
CS
SDO
SDI
SCLK
INT
VoltageReference
SystemClock
/KClock
Generator
SerialInterface
E-to-F
PowerMonitor
PFMON
x1
RESET
DigitalFilter
Calibration
MODE
PowerCalculation
Engine
4th Order Modulator
2nd OrderModulator
TemperatureSensor
DigitalFilter
PGA
HPFOption
HPFOption
E1
E2
E3
x10
APR 11
DS678F3
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TABLE OF CONTENTS1. Overv iew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52. Pin Descript ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63. Characteristics & Specif ications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144.1 Digital Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144.2 Voltage and Current Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144.3 Power Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144.4 Linearity Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5. Funct ional Descript ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165.1 Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.1 Voltage Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165.1.2 Current Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2 IIR Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165.3 High-pass Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165.4 Performing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165.5 Energy Pulse Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.5.1 Active Energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175.5.2 Apparent Energy Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185.5.3 Reactive Energy Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185.5.4 Voltage Channel Sign Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185.5.5 PFMON Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195.5.6 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.6 Sag and Fault Detect Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195.7 No Load Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195.8 On-chip Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195.9 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205.10 System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205.11 Power-down States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.12 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205.13 Event Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.13.1 Typical Interrupt Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215.14 Serial Port Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.14.1 Serial Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215.15 Register Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225.16 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.16.1 Start Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235.16.2 SYNC0 and SYNC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235.16.3 Power-up/Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235.16.4 Power-down and Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235.16.5 Register Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.16.6 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256. Register Descr iption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266.1 Page 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1.1 Configuration Register ( Config ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266.1.2 Current and Voltage DC Offset Register ( IDCoff, VDCoff ) . . . . . . . . . . . . 276.1.3 Current and Voltage Gain Register( Ign, Vgn ) . . . . . . . . . . . . . . . . . . . . 276.1.4 Cycle Count Register ( Cycle Count ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276.1.5 PulseRateE Register ( PulseRateE ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276.1.6 Instantaneous Current, Voltage, and Power Registers ( I , V , P ) . . . . . . 28
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6.1.7 Active (Real) Power Register( PActive ) . . . . . . . . . . . . . . . . . . . . . . . . . . 286.1.8 RMS Current & Voltage Registers ( IRMS, VRMS ) . . . . . . . . . . . . . . . . . . 286.1.9 Epsilon Register( e ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286.1.10 Power Offset Register ( Poff ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296.1.11 Status Register and Mask Register ( Status , Mask ) . . . . . . . . . . . . . . . 29
6.1.12 Current and Voltage AC Offset Register( VACoff , IACoff ) . . . . . . . . . . . 306.1.13 Operational Mode Register ( Mode ). . . . . . . . . . . . . . . . . . . . . . . . . . . . 306.1.14 Temperature Register ( T ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316.1.15 Average and Instantaneous Reactive Power Register( QAVG, Q ) . . . . 316.1.16 Peak Current and Peak Voltage Register( Ipeak, Vpeak) . . . . . . . . . . . . 316.1.17 Reactive Power Register( QTrig ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326.1.18 Power Factor Register ( PF ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326.1.19 Apparent Power Register ( S ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326.1.20 Control Register ( Ctrl ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336.1.21 Harmonic Active Power Register( PH ) . . . . . . . . . . . . . . . . . . . . . . . . . 336.1.22 Fundamental Active Power Register( PF ) . . . . . . . . . . . . . . . . . . . . . . 336.1.23 Fundamental Reactive Power Register( Q
H) . . . . . . . . . . . . . . . . . . . . 34
6.1.24 Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346.2 Page 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.2.1 Energy Pulse Output Width ( PulseWidth ) . . . . . . . . . . . . . . . . . . . . . . . . 356.2.2 No Load Threshold ( LoadMin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356.2.3 Temperature Gain Register( TGain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356.2.4 Temperature Offset Register( TOff ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.3 Page 3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366.3.1 Voltage Sag & Current Fault Duration Registers . . . . . . . . . . . . . . . . . . . 36
6.3.2 Voltage Sag & Current Fault Level Registers . . . . . . . . . . . . . . . . . . . . . . . 36
7. System Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377.1 Channel Offset and Gain Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.1.1 Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377.1.1.1 Duration of Calibration Sequence . . . . . . . . . . . . . . . . . . . . . 37
7.1.2 Offset Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377.1.2.1 DC Offset Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . 377.1.2.2 AC Offset Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . 38
7.1.3 Gain Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387.1.3.1 AC Gain Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . 387.1.3.2 DC Gain Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . 39
7.1.4 Order of Calibration Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . 397.2 Phase Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397.3 Active Power Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8. Auto-boot Mode Using E2PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.1 Auto-boot Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408.2 Auto-boot Data for E2PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408.3 Which E2PROMs Can Be Used? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9. Basic Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4110. Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4411. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4512. Environmental, Manufacturing, & Handling Information . . . . . . . . . . . . . . . . . 4513. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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LIST OF FIGURES
Figure 1. CS5463 Read and Write Timing Diagrams.................................................................. 12
Figure 2. Timing Diagram for E1, E2, and E3.......................................................................................13
Figure 3. Data Measurement Flow Diagram. .............................................................................. 14
Figure 4. Power Calculation Flow. .............................................................................................. 15
Figure 5. Active and Reactive Energy Pulse Outputs ................................................................. 17
Figure 6. Apparent Energy Pulse Outputs .................................................................................. 18
Figure 7. Voltage Channel Sign Pulse outputs ........................................................................... 18
Figure 8. PFMON Output to Pin E3....................................................................................................... 19
Figure 9. Sag and Fault Detect ................................................................................................... 19
Figure 10. Oscillator Connection................................................................................................. 20
Figure 11. CS5463 Memory Map ................................................................................................ 22
Figure 12. Calibration Data Flow ................................................................................................ 37
Figure 13. System Calibration of Offset ...................................................................................... 37
Figure 14. System Calibration of Gain. ....................................................................................... 38
Figure 15. Example of AC Gain Calibration ................................................................................ 38
Figure 16. Example of AC Gain Calibration ................................................................................ 38
Figure 17. Typical Interface of E2PROM to CS5463................................................................... 40
Figure 18. Typical Connection Diagram (Single-phase, 2-wire).................................................. 41
Figure 20. Typical Connection Diagram (Single-phase, 3-wire).................................................. 42
Figure 19. Typical Connection Diagram (Single-phase, 2-wire Isolated from Power Line)...... 42
Figure 21. Typical Connection Diagram (Single-phase, 3-wire No Neutral Available)............. 43
LIST OF TABLES
Table 1. Current Channel PGA Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 2. E2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 3. E3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4. Interrupt Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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1. OVERVIEW
The CS5463 is a CMOS monolithic power measurement device with a computation engine and an ener-gy-to-frequency pulse output. The CS5463 combines a programmable gain amplifier, two Ana-log-to-Digital Converters (ADCs), system calibration, and a computation engine on a single chip.
The CS5463 is designed for power measurement applications and is optimized to interface to a currentsense resistor or transformer for current measurement, and to a resistive divider or potential transformerfor voltage measurement. The current channel provides programmable gains to accommodate various in-put levels from a multitude of sensing elements. With single +5 V supply on VA+/AGND, both of theCS5463s input channels can accommodate common mode plus signal levels between (AGND - 0.25 V)and VA+.
The CS5463 also is equipped with a computation engine that calculates instantaneous power, IRMS,VRMS, apparent power, active (real) power, reactive power, harmonic active power, active and reactivefundamental power, and power factor. The CS5463 additional features include line frequency, current andvoltage sag detection, zero-cross detection, positive-only accumulation mode, and three programmablepulse output pins. To facilitate communication to a microprocessor, the CS5463 includes a simplethree-wire serial interface which is SPI and Microwire compatible. The CS5463 provides three out-puts for energy registration. E1, E2, and E3 are designed to interface to a microprocessor.
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2. PIN DESCRIPTION
Clock Generator
Crystal Out
Crystal In
1,24 XOUT, XIN The output and input of an inverting amplifier. Oscillation occurs when connected toa crystal, providing an on-chip system clock. Alternatively, an external clock can be supplied to
the XIN pin to provide the system clock for the device.
CPU Clock Outpu t 2 CPUCLK Output of on-chip oscillator which can drive one standard CMOS load.
Control Pins and Serial Data I/O
Serial Clock Input 5 SCLK A Schmitt-trigger input pin. Clocks data from the SDI pin into the receive buffer and outof the transmit buffer onto the SDO pin when CS is low.
Serial Data Output 6 SDO Serial port data output pin.SDO is forced into a high-impedance state when CS is high.
Chip Select 7 CS Low, activates the serial port interface.
Mode Select 8 MODE- High, enables the auto-boot mode. The mode pin has an internal pull-down resistor.
Energy Output 18,21,22 E3,E1, E2 Active-low pulses with an output frequency proportional to the selected power. Con-figurable outputs for active, apparent, and reactive power, negative energy indication, zero cross
detection, and power failure monitoring. E1, E2, E3 outputs are configured in the Operational
Modes Register.
Reset 19 RESET A Schmitt-trigger input pin. Low activates Reset, all internal registers (some of whichdrive output pins) are set to their default states.
Interrupt 20 INT- Low, indicates that an enabled event has occurred.
Serial Data Input 23 SDI- Serial port data input pin. Data will be input at a rate determined by SCLK.
Analog Inputs/Outputs
Differential Voltage Inputs 9,10 VIN+, VIN- Differential analog input pins for the voltage channel.
Differential Current Inputs 15,16 IIN+, IIN- Differential analog input pins for the current channel.
Voltage Reference Output 11 VREFOUT The on-chip voltage reference output. The voltage reference has a nominal magni-tude of 2.5 V and is referenced to the AGND pin on the converter.
Voltage Reference Input 12 VREFIN The input to this pin establishes the voltage reference for the on-chip modulator.
Power Supply Connections
Positive Digital Supply 3 VD+ The positive digital supply.
Digital Ground 4 DGND Digital Ground.
Positive Analog Supply 14 VA+ The positive analog supply.
Analog Ground 13 AGND Analog ground.
Power Fail Monitor 17 PFMON The power fail monitor pin monitors the analog supply. If the analog supply does notmeet or falls below PFMONs voltage threshold, a Low-supply Detect (LSD) event is set in the
status register.
12
11
10
9
8
7
6
5
4
3
2
1
13
14
15
16
17
18
19
20
21
22
23
24
AGND Analog Ground
VA+ Positive Analog Supply
IIN- Differential Current Input
IIN+ Differential Current Input
PFMON Power Fail Monitor
E3 High Frequency Energy Output
RESET Reset
INT Interrupt
E1 Energy Output 1
SDI Serial Data Input
XIN Crystal In
E2 Energy Output 2
VREFINVoltage Reference Input
VREFOUTVoltage Reference Output
VIN-Differential Voltage Input
VIN+Differential Voltage Input
MODEMode Select
CSChip Select
SDOSerial Data Ouput
SCLKSerial Clock
DGNDDigital Ground
VD+Positive Digital Supply
CPUCLKCPU Clock Output
XOUTCrystal Out
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3. CHARACTERISTICS & SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
ANALOG CHARACTERISTICS Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.
Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 C.
VA+ = VD+ = 5 V 5%; AGND = DGND = 0 V; VREFIN = +2.5 V. All voltages with respect to 0 V.
MCLK = 4.096 MHz.
Notes: 1. Applies when the HPF option is enabled.
2. Applies when the line frequency is equal to the product of the Output Word Rate (OWR) and the valueof epsilon ().
Parameter Symbol Min Typ Max Unit
Positive Digital Power Supply VD+ 3.135 5.0 5.25 V
Positive Analog Power Supply VA+ 4.75 5.0 5.25 V
Voltage Reference VREFIN - 2.5 - V
Specified Temperature Range TA -40 - +85 C
Parameter Symbol Min Typ Max Unit
Accuracy
Active Power All Gain Ranges
(Note 1) Input Range 0.1% - 100% PActive - 0.1 - %
Average Reactive Power All Gain Ranges
(Note 1and 2) Input Range 0.1% - 100%QAvg - 0.2 - %
Power Factor All Gain Ranges
(Note 1and 2) Input Range 1.0% - 100%
Input Range 0.1% - 1.0%
PF -
-
0.2
0.27
-
-
%
%
Current RMS All Gain Ranges
(Note 1) Input Range 0.2% - 100%
Input Range 0.1% - 0.2%
IRMS -
-
0.2
1.5
-
-
%
%
%
Voltage RMS All Gain Ranges
(Note 1) Input Range 5% - 100%VRMS - 0.1 - %
Analog Inputs (Both Channels)
Common Mode Rejection (DC, 50, 60 Hz) CMRR 80 - - dB
Common Mode + Signal All Gain Ranges -0.25 - VA+ V
Analog Inputs (Current Channel)
Differential Input Range (Gain = 10)
[(IIN+) - (IIN-)] (Gain = 50) IIN-
-
500
100
-
-
mVP-PmVP-P
Total Harmonic Distortion (Gain = 50) THD 80 94 - dB
Crosstalk with Voltage Channel at Full Scale (50, 60 Hz) - -115 - dB
Input Capacitance (Gain = 10)
(Gain = 50)IC
-
-
32
52
-
-
pF
pF
Effective Input Impedance EII 30 - - kNoise (Referred to Input) (Gain = 10)
(Gain = 50) NI-
-
22.5
4.5
-
-
VrmsVrms
Offset Drift (Without the High Pass Filter) OD - 4.0 - V/C
Gain Error (Note 3) GE - 0.4 %
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ANALOG CHARACTERISTICS (Continued)
Notes: 3. Applies before system calibration.4. All outputs unloaded. All inputs CMOS level.
5. Measurement method for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 5 V, a 150 mV(zero-to-peak) (60 Hz) sinewave is imposed onto the +5 V DC supply voltage at VA+ and VD+ pins. The+ and - input pins of both input channels are shorted to AGND. Then the CS5463 is commanded tocontinuous conversion acquisition mode, and digital output data is collected for the channel under test.The (zero-to-peak) value of the digital sinusoidal output signal is determined, and this value is convertedinto the (zero-to-peak) value of the sinusoidal voltage (measured in mV) that would need to be appliedat the channels inputs, in order to cause the same digital sinusoidal output. This voltage is then definedas Veq. PSRR is then (in dB):
6. When voltage level on PFMON is sagging, and LSD bit = 0, the voltage at which LSD is set to 1.
7. If the LSD bit has been set to 1 (because PFMON voltage fell below PMLO), this is the voltage level onPFMON at which the LSD bit can be permanently reset back to 0.
Parameter Symbol Min Typ Max Unit
Analog Inputs (Vol tage Channel)
Differential Input Range [(VIN+) - (VIN-)] VIN - 500 - mVP-P
Total Harmonic Distortion THD 65 75 - dBCrosstalk with Current Channel at Full Scale (50, 60 Hz) - -70 - dB
Input Capacitance All Gain Ranges IC - 0.2 - pF
Effective Input Impedance EII 2 - - MNoise (Referred to Input) NV - 140 - Vrms
Offset Drift (Without the High Pass Filter) OD - 16.0 - V/C
Gain Error (Note 3) GE - 3.0 %
Temperature Channel
Temperature Accuracy T - 5 - C
Power Supplies
Power Supply Currents (Active State) IA+
ID+ (VA+ = VD+ = 5 V)ID+(VA+ = 5 V, VD+ = 3.3 V)
PSCA
PSCDPSCD
-
--
1.1
2.91.7
-
--
mA
mAmA
Power Consumption Active State (VA+ = VD+ = 5 V)
(Note 4) Active State (VA+ = 5 V, VD+ = 3.3 V)
Stand-by State
Sleep State
PC -
-
-
-
21
11.6
8
10
29
17.5
-
-
mW
mW
mW
W
Power Supply Rejection Ratio (50, 60 Hz)
(Note 5) Voltage Channel
Current Channel
PSRR 45
70
-
65
75
-
-
-
dB
dB
PFMON Low-voltage Trigger Threshold (Note 6) PMLO 2.3 2.45 - V
PFMON High-voltage Power-on Trip Point (Note 7) PMHI - 2.55 2.7 V
PSRR 20150
Veq----------log=
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CS5463
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VOLTAGE REFERENCE
Notes: 8. The voltage at VREFOUT is measured across the temperature range. From these measurements thefollowing formula is used to calculate the VREFOUT Temperature Coefficient:.
9. Specified at maximum recommended output of 1 A, source or sink.
DIGITAL CHARACTERISTICS Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.
Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 C.
VA+ = VD+ = 5V 5%; AGND = DGND = 0 V. All voltages with respect to 0 V.
MCLK = 4.096 MHz.
Parameter Symbol Min Typ Max Unit
Reference Output
Output Voltage VREFOUT +2.4 +2.5 +2.6 V
Temperature Coefficient (Note 8) TCVREF - 25 60 ppm/C
Load Regulation (Note 9) VR - 6 10 mV
Reference Input
Input Voltage Range VREFIN +2.4 +2.5 +2.6 V
Input Capacitance - 4 - pF
Input CVF Current - 25 - nA
Parameter Symbol Min Typ Max Unit
Master Clock Characteristi cs
Master Clock Frequency Internal Gate Oscillator (Note 11) MCLK 2.5 4.096 20 MHz
Master Clock Duty Cycle 40 - 60 %
CPUCLK Duty Cycle (Note 12and 13) 40 - 60 %
Filter Characteristics
Phase Compensation Range (Voltage Channel, 60 Hz) -2.8 - +2.8
Input Sampling Rate DCLK = MCLK/K - DCLK/8 - Hz
Digital Filter Output Word Rate (Both Channels) OWR - DCLK/1024 - Hz
High-pass Filter Corner Frequency -3 dB - 0.5 - Hz
Full-scale DC Calibration Range (Referred to Input) (Note 14) FSCR 25 - 100 %F.S.
Channel-to-channel Time-shift Error (Note 15) 1.0 s
Input/Output Characteristics
High-level Input VoltageAll Pins Except XIN and SCLK and RESET
XIN
SCLK and RESET
VIH0.6 VD+
(VD+) - 0.5
0.8VD+
-
-
-
-
-
-
V
V
V
Low-level Input Voltage (VD = 5 V)
All Pins Except XIN and SCLK and RESET
XIN
SCLK and RESET
VIL-
-
-
-
-
-
0.8
1.5
0.2VD+
V
V
V
(VREFOUTMAX - VREFOUTMIN)
VREFOUTAVG(
( 1T
A
MAX - TA
MIN(
(1.0 x 10(
(6
TCVREF
=
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10 DS678F3
Notes: 10. All measurements performed under static conditions.
11. If a crystal is used, then XIN frequency must remain between 2.5 MHz - 5.0 MHz. If an externaloscillator is used, XIN frequency range is 2.5 MHz - 20 MHz, but K must be set so that MCLK is between2.5 MHz - 5.0 MHz.
12. If external MCLK is used, then the duty cycle must be between 45% and 55% to maintain thisspecification.
13. The frequency of CPUCLK is equal to MCLK.
14. The minimum FSCR is limited by the maximum allowed gain register value. The maximum FSCR islimited by the full-scale signal applied to the channel input.
15. Configuration Register bits PC[6:0] are set to 0000000.
16. The MODE pin is pulled low by an internal resistor.
Low-level Input Voltage (VD = 3.3 V)
All Pins Except XIN and SCLK and RESET
XIN
SCLK and RESET
VIL-
-
-
-
-
-
0.48
0.3
0.2VD+
V
V
VHigh-level Output Voltage Iout= +5 mA VOH (VD+) - 1.0 - - V
Low-level Output Voltage Iout= -5 mA VOL - - 0.4 V
Input Leakage Current (Note 16) Iin - 1 10 A
3-state Leakage Current IOZ - - 10 A
Digital Output Pin Capacitance Cout - 5 - pF
Parameter Symbol Min Typ Max Unit
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SWITCHING CHARACTERISTICS Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.
Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 C.
VA+ = 5 V 5% VD+ = 3.3 V 5% or 5 V 5%; AGND = DGND = 0 V. All voltages with respect to 0 V.
Logic Levels: Logic 0 = 0 V, Logic 1 = VD+.
Notes: 17. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.
18. Oscillator start-up time varies with crystal parameters. This specification does not apply when using anexternal clock source.
Parameter Symbol Min Typ Max Unit
Rise Times Any Digital Input Except SCLK
(Note 17) SCLK
Any Digital Output
trise -
-
-
-
-
50
1.0
100
-
s
s
ns
Fall Times Any Digital Input Except SCLK
(Note 17) SCLK
Any Digital Output
tfall -
-
-
-
-
50
1.0
100
-
s
s
ns
Start-up
Oscillator Start-up Time XTAL = 4.096 MHz (Note 18) tost - 60 - ms
Serial Port Timing
Serial Clock Frequency SCLK - - 2 MHz
Serial Clock Pulse Width High
Pulse Width Low
t1t2
200
200
-
-
-
-
ns
ns
SDI Timing
CS Falling to SCLK Rising t3 50 - - ns
Data Set-up Time Prior to SCLK Rising t4 50 - - ns
Data Hold Time After SCLK Rising t5 100 - - ns
SDO Timing
CS Falling to SDI Driving t6 - 20 50 ns
SCLK Falling to New Data Bit (hold time) t7 - 20 50 ns
CS Rising to SDO Hi-Z t8 - 20 50 ns
Auto-Boot Timing
Serial Clock Pulse Width Low
Pulse Width High
t9t10
8
8
MCLK
MCLK
MODE setup time to RESET Rising t11 50 ns
RESET rising to CS falling t12 48 MCLK
CS falling to SCLK rising t13 100 8 MCLK
SCLK falling to CS rising t14 16 MCLK
CS rising to driving MODE low (to end auto-boot sequence) t15
50 ns
SDO guaranteed setup time to SCLK rising t16 100 ns
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CS5463
12 DS678F3
t1
t2
t3
t4
t5
MSB
MSB-1
LSB
MSB
MSB-1
LSB
MSB
MSB-1
LSB
MSB
MSB-1
LSB
C om m and T im e 8 S C LK s H ig h B yte M id B yte Low B yte
C S
S C L K
S D I
t10
t9
R E S E T
S D O
S C L K
C S
L a s t 8B i t s
S D I
M O D E
STOPbit
D a t a fr o m E E P R O M
t16
t4 t
5
t14
t15
t7t
13
t12
t11
( I N P U T )
( I N P U T )
( O U T P U T )
( O U T P U T )
( O U T P U T )
( I N P U T )
SDI Write Timing (Not to Scale)
SDO Read Timing (Not to Scale)
Figure 1. CS5463 Read and Write Timing Diagrams
Auto-boot Sequence Timing (Not to Scale)
t1 t2
MSB
MSB-1
LSB
C o m m a n d T im e 8 S C L K s S Y N C 0 o r S Y N C 1
C o m m a n d
S Y N C 0 o r S Y N C 1
C o m m a n d
MSB
MSB-1
LSB
MSB
MSB-1
LSB
MSB
MSB-1
LSB
H ig h B y te M id B y te L o w B y te
C S
S D O
C L K
S D I
t6
t7
t8
S Y N C 0 o r S Y N C 1
C o m m a n d
U N K N O W N
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SWITCHING CHARACTERISTICS (Continued)
Notes: 19. Pulse output timing is specified at MCLK = 4.096 MHz, E2MODE = 0, and E3MODE[1:0] = 0. Refer toSection 5.5 Energy Pulse Outputon page 17for more information on pulse output pins.
20. Timing is proportional to the frequency of MCLK.
ABSOLUTE MAXIMUM RATINGS
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
Notes: 21. VA+ and AGND must satisfy [(VA+) - (AGND)] + 6.0 V.
22. VD+ and AGND must satisfy [(VD+) - (AGND)] + 6.0 V.
23. Applies to all pins including continuous over-voltage conditions at the analog input pins.
24. Transient current of up to 100 mA will not cause SCR latch-up.
25. Maximum DC input current for a power supply pin is 50 mA.
26. Total power dissipation, including all input currents and output currents.
Parameter Symbol Min Typ Max Unit
E1,E2, and E3 Timing (Note 19and 20)
Period tperiod 250 - - s
Pulse Width tpw 244 - - s
Rising Edge to Falling Edge t3 6 - - s
E2 Setup to E1 and/or E3 Falling Edge t4 1.5 - - s
E1 Falling Edge to E3 Falling Edge t5 248 - - s
Parameter Symbol Min Typ Max UnitDC Power Supplies (Notes 21and 22)
Positive Digital
Positive Analog
VD+
VA+
-0.3
-0.3
-
-
+6.0
+6.0
V
V
Input Current, Any Pin Except Supplies (Notes 23, 24, 25) IIN - - 10 mA
Output Current, Any Pin Except VREFOUT IOUT - - 100 mA
Power Dissipation (Note 26) PD - - 500 mW
Analog Input Voltage All Analog Pins VINA - 0.3 - (VA+) + 0.3 V
Digital Input Voltage All Digital Pins VIND -0.3 - (VD+) + 0.3 V
Ambient Operating Temperature TA -40 - 85 C
Storage Temperature Tstg -65 - 150 C
tperiod
E1
t3t4
t5 t3
t5t4
E2
E3
tpw
tperiodtpw
Figure 2. Timing Diagram for E1, E2, and E3
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4. THEORY OF OPERATION
The CS5463 is a dual-channel analog-to-digital convert-
er (ADC) followed by a computation engine that per-forms power calculations and energy-to-pulse
conversion. The data flow for the voltage and current
channel measurement and the power calculation algo-
rithms are depicted in Figure 3and 4, respectively.
The analog inputs are structured with two dedicated
channels, Voltageand Current, then optimized to simpli-
fy interfacing to various sensing elements.
The voltage-sensing element introduces a voltage
waveform on the voltage channel input VIN and is sub-
ject to a gain of 10x. A second-order delta-sigma modu-
lator samples the amplified signal for digitization.
Simultaneously, the current-sensing element introducesa voltage waveform on the current channel input IIN
and is subject to two selectable gains of the program-
mable gain amplifier (PGA). The amplified signal is
sampled by a fourth-order delta-sigma modulator for
digitization. Both converters sample at a rate of
MCLK/8, the over-sampling provides a wide dynamic
range and simplified anti-alias filter design.
4.1 Digital Filters
The decimating digital filters on both channels are Sinc3
filters followed by 4th-order IIR filters. The single-bit
data is passed to the low-pass decimation filter and out-
put at a fixed word rate. The output word is passed to an
optional IIR filter to compensate for the magnitude roll
off of the low-pass filtering operation.
An optional digital high-pass filter (HPFin Figure 3) re-
moves any DC component from the selected signal
path. By removing the DC component from the voltage
and/or the current channel, any DC content will also be
removed from the calculated active power as well. With
both HPFs enabled the DC component will be removed
from the calculated VRMSand IRMSas well as the appar-
ent power.
When the optional HPF in either channel is disabled, an
all-pass filter (APF) is implemented. The APF has an
amplitude response that is flat within the channel band-
width and is used for matching phase in systems where
only one HPF is engaged.
4.2 Voltage and Current Measurements
The digital filter output word is then subject to a DC off-
set adjustment and a gain calibration (See Section 7.
System Calibrationon page 37). The calibrated mea-
surement is available by reading the instantaneous volt-
age and current registers.The Root Mean Square (RMSin Figure 4) calculations
are performed on N instantaneous voltage and current
samples, Vnand In, respectively (where N is the cycle
count), using the formula:
and likewise for VRMS, using Vn. IRMSand VRMSare ac-
cessible by register reads, which are updated once ev-
ery cycle count (referred to as a computational cycle).
4.3 Power Measurements
The instantaneous voltage and current samples are
multiplied to obtain the instantaneous power (see Fig-
ure 3). The product is then averaged over N conver-
sions to compute active power and is used to drive
energy pulse output E1. Energy output E2 is selectable,
providing an energy sign or a pulse output that is pro-
portional to the apparent power. Energy output E3
VOLTAGE SINC3+
X
V *gn
CURRENT SINC3 +
X
I *gn
DELAY
REG
DELAY
REG
IDCoff
*
VDCoff
*
PGA
+
+
Configuration Register *
Digital Filter
Digital Filter
HPF
2nd Order
Modulator
4th Order
Modulator
x10 X
X
SYSGain
*PC6 PC5 PC4 PC3 PC2 PC1PC0
6
*DENOTES REGISTER NAME.
DELAY
REG
DELAY
REG
HPF VQ*
XVDEL XIDEL 01223228 7
...
Operational Modes Register *
+X
+
X
X Q*
2
MUX
X
V *
P*
I *MUX
VHPF IHPF6 5
*
APF
HPF
APF
MUX
IIR
MUXIIR
3IIR4
Figure 3. Data Measurement Flow Diagram.
IRMS
In
n 0=
N 1
N---------------------
=
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CS5463
DS678F3 15
provides a pulse output that is proportional to the reac-
tive power or apparent power. Output E3 can also be set
to display the sign of the voltage applied to the voltage
channel or the PFMON comparator output.
The apparent power (S) is the combination of the active
power and reactive power, without reference to an im-
pedance phase angle, and is calculated by the CS5463
using the following formula:
Power Factor (PF) is the active power (PActive) divided
by the apparent power (S)
The sign of the power factor is determined by the active
power.
The CS5463 calculates the reactive power, QTrigutiliz-
ing trigonometric identities, giving the formula
Average reactive power, QAvg, is generated by averag-ing the voltage multiplied by the current with a 90phase
shift difference between them. The 90 phase shift is re-
alized by applying an IIR digital filter in the voltage chan-
nel to obtain quadrature voltage (see Figure 3). This
filter will give exactly -90 phase shift across all frequen-
cies, and utilizes epsilon () to achieve unity gain at theline frequency.
The instantaneous quadrature voltage (VQ) and current
(I) samples are multiplied to obtain the instantaneous
quadrature power (Q). The product is then averaged
over N conversions, utilizing the formula
Fundamental active (PF) and reactive (QF) power is cal-culated by performing a discrete Fourier transform(DFT) at the relevant frequency on the instantaneousvoltage (V) and current (I). Epsilon is used to set the fre-quency of the internal sine (imaginary component) andcosine (real component) waveform generator. The har-monic active power (PH) is calculated by subtracting thefundamental active power (PF) from the active power
(PActive).The peak current (Ipeak) and peak voltage (Vpeak) arethe instantaneous current and voltage, respectively,with the greatest magnitude detected during the lastcomputation cycle. Active, apparent, reactive, and fun-damental power are updated every computation cycle.
4.4 Linearity Performance
The linearity of the VRMS, IRMS, active, reactive, andpower-factor power measurements (before calibration)will be within 0.1% of reading over the ranges speci-fied, with respect to the input voltage levels required tocause full-scale readings in the IRMSand VRMSregis-
ters. Refer toAccuracy Specificationson page 7.Until the CS5463 is calibrated, the accuracy of theCS5463 (with respect to a reference line-voltage andline-current level on the power mains) is not guaranteedto within 0.1%. (See Section 7. System Calibrationonpage 37.) The accuracy of the internal calculations canoften be improved by selecting a value for the CycleCount Register that will cause the time duration of onecomputation cycle to be equal to (or very close to) awhole number of power-line cycles (and N must begreater than or equal to 4000).
XV *
I *RMS
V *RMS
E1
I *
Energy-to-pulseXE3
+ +
X
+
IACoff
*
+
+
VACoff
*
+
E2
NN
NN
P *ACTIVE
NN
Poff*
P*
PulseRate*
*DENOTES REGISTER NAME.
X
S*
Q *AVG
-
+
X
Inverse X PF*
QTRIG*
Q* NN
X
Figure 4. Power Calculation Flow.
S VRMS IRMS=
PFPAc ti ve
S------------------=
QTrig S2 P
Ac ti ve2
=
QAv g
Qnn 1=
N
N
-------------------------
=
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5. FUNCTIONAL DESCRIPTION
5.1 Analog Inputs
The CS5463 is equipped with two fully differential input
channels. The inputs VINand IINare designated as
the voltage and current channel inputs, respectively.The full-scale differential input voltage for the current
and voltage channel is 250 mVP.
5.1.1 Voltage Channel
The output of the line voltage resistive divider or trans-
former is connected to the VIN+ and VIN- input pins of
the CS5463. The voltage channel is equipped with a
10x fixed-gain amplifier. The full-scale signal level that
can be applied to the voltage channel is 250 mV. If theinput signal is a sine wave the maximum RMS voltage
at a gain 10x is:
which is approximately 70.7% of maximum peak volt-
age. The voltage channel is also equipped with a Volt-
age Gain Register, allowing for an additional
programmable gain of up to 4x.
5.1.2 Current Channel
The output of the current-sense resistor or transformer
is connected to the IIN+ and IIN- input pins of the
CS5463. To accommodate different current sensing el-
ements the current channel incorporates a programma-
ble gain amplifier (PGA) with two programmable inputgains. Configuration Registerbit Igain (see Table 1) de-
fines the two gain selections and corresponding maxi-
mum input-signal level.
For example, if Igain=0, the current channels PGA gain
is set to 10x. If the input signals are pure sinusoids with
zero phase shift, the maximum peak differential signal
on the current or voltage channel is 250 mVP. The in-put signal levels are approximately 70.7% of maximum
peak voltage producing a full-scale energy pulse regis-
tration equal to 50% of absolute maximum energy pulse
registration. This will be discussed further in See Sec-
tion 5.5 Energy Pulse Outputon page 17.
The Current Gain Registeralso facilitates an additional
programmable gain of up to 4x. If an additional gain is
applied to the voltage and/or current channel, the maxi-
mum input range should be adjusted accordingly.
5.2 IIR Filters
The current and voltage channel are equipped with a
4th-order IIR filter, that is used to compensate for the
magnitude roll off of the low-pass decimation filter. Op-
erational Mode Registerbit IIR engages the IIR filters in
both the voltage and current channels.
5.3 High-pass Filters
By removing the offset from either channel, no error
component will be generated at DC when computing the
active power. By removing the offset from both chan-
nels, no error component will be generated at DC when
computing VRMS, IRMS, and apparent power. Operation-
al Mode Registerbits VHPF and IHPF activate the HPFin the voltage and current channel respectively. When a
high-pass filter is active in only one channel, an all-pass
filter (APF) is applied to the other channel. The APF has
an amplitude response that is flat within the channel
bandwidth and is used for matching phase in systems
where only one HPF is engaged.
5.4 Performing Measurements
The CS5463 performs measurements of instantaneous
voltage (Vn) and current (In), and calculates instanta-
neous power (Pn) at an output word rate (OWR) of
where K is the clock divider selected in the Configura-
tion Register.
The RMS voltage (VRMS), RMS current (IRMS), and ac-
tive power (Pactive) are computed using N instantaneous
samples of Vn, In, and Pnrespectively, where N is the
value in the Cycle Count Registerand is referred to as
a computation cycle. The apparent power (S) is the
product of VRMSand IRMS. A computation cycle is de-
rived from the master clock (MCLK), with frequency:
Under default conditions and with K = 1, N = 4000, and
MCLK = 4.096 MHz the OWR = 4000 Hz and the
Computation Cycle = 1 Hz.
All measurements are available as a percentage of full
scale. The format for signedregisters is a twos comple-
ment, normalized value between -1 and +1. The format
Igain Maximum Inpu t Range
0 250 mV 10x
1 50 mV 50x
Table 1. Current Channel PGA Setting
250mVP
2--------------------- 176.78mV
RM S
OW R MCLK K 1024
-----------------------------=
Computation Cycle
OWR
N---------------
=
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for unsignedregisters is a normalized value between 0
and 1. A register value of
represents the maximum possible value.
At each instantaneous measurement, the CRDY bit will
be set in the Status Register, and the INT pin will be-
come active if the CRDY bit is unmasked in the Mask
Register. At the end of each computation cycle, the
DRDY bit will be set in the Status Register, and the INT
pin will become active if the DRDY bit is unmasked in
the Mask Register. When these bits are asserted, they
must be cleared before they can be asserted again.
If the Cycle Count Register(N) is set to 1, all output cal-
culations are instantaneous, and DRDY, like CRDY, will
indicate when instantaneous measurements are fin-ished. Some calculations are inhibited when the cycle
count is less than 2.
Epsilon () is the ratio of the input line frequency (fi) tothe sample frequency (fs) of the ADC.
where fs = MCLK / (K*1024). With MCLK = 4.096 MHz
and clock divider K = 1, fs = 4000 Hz. For the two
most-common line frequencies, 50 Hz and 60 Hz
and
respectively. Epsilon is used to set the frequency of the
internal sine/cosine reference for the fundamental ac-
tive and reactive measurements, and the gain of the 90
phase shift (IIR) filter for the average reactive power.
5.5 Energy Pulse Output
The CS5463 provides three output pins for energy reg-
istration. By default, E1 registers active energy, E3 reg-
isters reactive energy, and E2 indicates the sign of both
active and reactive energy. (See Figure 2. Timing Dia-
gram for E1, E2, and E3on page13.) The E1 pulse out-
put is designed to register the Active Energy. The E2 pin
can be set to register Apparent Energy. Table 2defines
the pulse output mode, which is controlled by bit
E2MODE in the Operational Mode Register.
The E3 pin can be set to register Reactive Energy (de-
fault), PFMON, Voltage Channel Sign, or Apparent En-
ergy. Table 3defines the pulse output format, which is
controlled by bits E3MODE[1:0] in the Operational
Mode Register.
The pulse output frequency of E1, E2, and E3 is directly
proportional to the power calculated from the input sig-
nals. The value contained in the PulseRateE Registeris
the ratio of the frequency of energy-output pulses to the
number of samples, at full scale, which defines the av-
erage frequency for the output pulses. The pulse width,
tpw in Figure 2, is programmable through the Pulse-
Width register, and is approximately equal to:
If MCLK = 4.096 MHz, K = 1, and PulseWidth = 1, then
tpw 0.25 ms.
5.5.1 Active Energy
The E1 pin produces active-low pulses with an output
frequency proportional to the active power. The E2 pin
is the energy direction indicator. Positive energy is rep-
resented by E1 pin falling while the E2 is high. Negative
energy is represented by the E1 pin falling while the E2
is low. The E1 and E2 switching characteristics are
specified in Figure 2. Timing Diagram for E1, E2, and E3on page13.
Figure 5illustrates the pulse output format with positive
active energy and negative reactive energy.
223
1
223
------------------------ 0.99999988=
fi fs=
50 Hz 4000 Hz 0.0125= =
60 Hz 4000 Hz 0.015= =
E2MODE E2 Output Mode
0 Sign of Energy
1 Apparent Energy
Table 2. E2 Pin Configuration
E3MODE1 E3MODE0 E3 OutPut Mode
0 0 Reactive Energy
0 1 PFMON
1 0 Voltage Channel Sign
1 1 Apparent Energy
Table 3. E3 Pin Configuration
tpw
sec PulseWidth 1( MCLK/K ) / 1024------------------------------------------------
E3
E2
E1
Figure 5. Active and Reactive energy pulse outputs
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The pulse output frequency of E1 is directly proportional
to the active power calculated from the input signals. To
calculate the output frequency of E1, the following trans-
fer function can be utilized:
With MCLK = 4.096 MHz, PF = 1, and default settings,
the pulses will have an average frequency equal to the
frequency specified by PulseRatewhen the input sig-nals applied to the voltage and current channels cause
full-scale readings in the instantaneous voltage and cur-
rent registers. The maximum pulse frequency from the
E1 pin is (MCLK/K) /2048.
5.5.2 Apparent Energy Mode
Pin E2 outputs apparent energy pulses when the Oper-
ational Mode Registerbit E2MODE = 1. Pin E3 outputs
apparent energy pulses when the Operational Mode
Register bits E3MODE[1:0] = 3 (11b). Figure 6 illus-
trates the pulse output format with apparent energy on
E2 (E2MODE = 1 and E3MODE[1:0] = 0)
The pulse output frequency of E2 (and/or E3) is directly
proportional to the apparent power calculated from the
input signals. Since apparent power is without reference
to an impedance phase angle, the following transfer
function can be utilized to calculate the output frequency
on E2 (and/or E3).
With MCLK = 4.096 MHz and default settings, the puls-
es will have an average frequency equal to the frequen-
cy specified by PulseRate when the input signals
applied to the voltage and current channels cause
full-scale readings in the instantaneous voltage and cur-
rent registers. The maximum pulse frequency from theE2 (and/or E3) pin is (MCLK/K)/2048. The E2 (and/or
E3) pin outputs apparent energy, but has no energy di-
rection indicator.
5.5.3 Reactive Energy Mode
Reactive energy pulses are output on pin E3 by setting
bit E3MODE[1:0] = 0 (default) in the Operational Mode
Register. Positive reactive energy is registered by E3
falling when E2 is high. Negative reactive energy is reg-
istered by E3 falling when E2 is low. Figure 5 on
page 17illustrates the pulse output format with negative
reactive energy output on pin E3 and the sign of the en-
ergy on E2. The E3 and E2 pulse output switching char-acteristics are specified in Figure 2 on page 13.
The pulse output frequency of E3 is directly proportional
to the reactive power calculated from the input signals.
To calculate the output frequency on E3, the following
transfer function can be utilized:
With MCLK = 4.096 MHz, PF = 0 and default settings,
the pulses will have an average frequency equal to the
frequency specified by PulseRatewhen the input sig-
nals applied to the voltage and current channels cause
full-scale readings in the instantaneous voltage and cur-
rent registers. The maximum pulse frequency from the
E1 pin is (MCLK/ K)/2048.
5.5.4 Voltage Channel Sign Mode
Setting bits E3MODE[1:0] = 2 (10b) in the Operational
Mode Registeroutputs the sign of the voltage channel
on pin E3. Figure 7illustrates the output format with volt-
age channel sign on E3
FREQP= Average frequency of active energy E1 pulses [Hz]VIN = rms voltage across VIN+ and VIN- [V]VGAIN = Voltage channel gainIIN = rms voltage across IIN+ and IIN- [V]IGAIN = Current channel gainPF = Power FactorPulseRate = PulseRateE x (MCLK/K)/2048 [Hz]VREFIN = Voltage at VREFIN pin [V]
FREQP
VIN VGAIN II N IGAI N PF PulseRate
VREFIN2
---------------------------------------------------------------------------------------------------------------------------------=
E3
E2
E1
Figure 6. Apparent energy pulse outputs
FREQS= Average frequency of apparent energy E2 and/or E3 pulses [Hz]VIN = rms voltage across VIN+ and VIN- [V]VGAIN = Voltage channel gainIIN = rms voltage across IIN+ and IIN- [V]IGAIN = Current channel gainPulseRate = PulseRateE x (MCLK/K)/2048 [Hz]VREFIN = Voltage at VREFIN pin [V]
FREQS
VIN VGAIN II N I GA IN P ul se Ra te
VREFIN2
------------------------------------------------------------------------------------------------------------------=
FREQQ= Average frequency of reactive energy E3 pulses [Hz]VIN = rms voltage across VIN+ and VIN- [V]VGAIN = Voltage channel gainIIN = rms voltage across IIN+ and IIN- [V]
IGAIN = Current channel gainPQ =PulseRate = PulseRateE x (MCLK/K)/2048 [Hz]VREFIN = Voltage at VREFIN pin [V]
FREQQ
VIN VGAIN II N IGAIN PQ PulseRate
VREFIN2
----------------------------------------------------------------------------------------------------------------------------------=
1 PF2
E3
E2
E1
Figure 7. Voltage Channel Sign Pulse outputs
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Output pin E3 is high when the line voltage is positive
and pin E3 is low when the line voltage is negative.
5.5.5 PFMON Output Mode
Setting bit E3MODE[1:0] = 1 (01b) in the Operational
Mode Registeroutputs the state of the PFMON compar-ator on pin E3. Figure 8illustrates the output format with
PFMON on E3
When PFMON is greater then the threshold, pin E3 is
high and when PFMON is less than the threshold pin E3
is low.
5.5.6 Design ExampleEXAMPLE #1:
The maximum rated levels for a power line meter are
250 V rms and 20 A rms. The required number of puls-
es-per-second on E1 is 100 pulses per second
(100 Hz), when the levels on the power line are
220 V rms and 15 A rms.
With a 10x gain on the voltage and current channel the
maximum input signal is 250 mVP. (See Section 5.1An-
alog Inputs on page 16.) To prevent over-driving the
channel inputs, the maximum rated rms input levels will
register 0.6 in VRMSand IRMSby design. Therefore the
voltage level at the channel inputs will be 150 mV rmswhen the maximum rated levels on the power lines are
250 V rms and 20 A rms.
Solving for PulseRateusing the transfer function:
Therefore with PF = 1 and:
the pulse rate is:
and the PulseRateE Registeris set to:
with MCLK = 4.096 MHz and K = 1.
5.6 Sag and Fault Detect Feature
Status bit VSAG and IFAULT in the Status Register,in-
dicates a sag occurred in the power line voltage and
current, respectively. For a sag condition to be identi-
fied, the absolute value of the instantaneous voltage or
current must be less than the sag level for more thanhalf of the sag duration (see Figure 9).
To activate voltage sag detection, a voltage sag level
must be specified in the Voltage Sag Level Register
(VSAGLevel), and a voltage sag duration must be spec-
ified in the Voltage Sag Duration Register(VSAGDura-
tion). To activate current fault detection, a current sag
level must be specified in the Current Fault Level Reg-
ister (ISAGLevel), and a current sag duration must be
specified in the Current Fault Duration Register(ISAG-
Duration). The voltage and current sag levels are speci-
fied as the average of the absolute instantaneous
voltage and current, respectively. Voltage and currentsag duration is specified in terms of ADC cycles.
5.7 No Load Threshold
The No Load Threshold register (LoadMin) is used to
disable the active energy pulse output when the magni-
tude of the PActiveregister is less than the value in the
LoadMinregister.
5.8 On-chip Temperature Sensor
The on-chip temperature sensor is designed to assist in
characterizing the measurement element over a desiredtemperature range. Once a temperature characteriza-
tion is performed, the temperature sensor can then be
utilized to assist in compensating for temperature drift.
Temperature measurements are performed during con-
tinuous conversions and stored in the Temperature
Register. The Temperature Register(T) default is Cel-
sius scale (C). The Temperature Gain Register(Tgain)
and Temperature Offset Register(Toff) are constant val-
ues allowing for temperature scale conversions.
E3
E2
E1
Above PFMON Threshold Below PFMON Threshold
Figure 8. PFMON output to pin E3
PulseRateFREQ
PVREFIN
2
VIN VGAIN II N IGAIN PF---------------------------------------------------------------------------------------------=
VIN 220V 150mV 250V 132mV= =
I IN 15A 150mV 20A 112.5mV= =
PulseRate100 2.5
2
0.132 10 0.1125 10----------------------------------------------------------------- 420.8754Hz= =
PulseRateEPulseRate
MCLK K 2048---------------------------------------- 0.2104377= =
Level
Duration
Figure 9. Sag and Fault Detect
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The temperature update rate is a function of the number
of ADC samples. With MCLK = 4.096 MHz and K = 1
the update rate is:
The Cycle Count Register (N) must be set to a value
greater then one. Status bit TUP in the Status Register,
indicates when the Temperature Registeris updated.
The Temperature Offset Registersets the zero-degree
measurement. To improve temperature measurement
accuracy, the zero-degree offset may need to be adjust-
ed after the CS5463 is initialized. Temperature-offset
calibration is achieved by adjusting the Temperature
Offset Register (Toff) by the differential temperature
(T) measured from a calibrated digital thermometerand the CS5463 temperature sensor. A one-degree ad-
justment to the Temperature Register(T) is achieved by
adding 2.737649x10-4to the Temperature Offset Regis-
ter(Toff). Therefore,
if Toff= -0.0951126 and T = -2.0 (C), then
or 0xF3C168 (2s compliment notation) is stored in the
Temperature Offset Register(Toff).
To convert the Temperature Register(T) from a Celsius
scale (C) to a Fahrenheit scale (F) utilize the formula
Applying the above relationship to the CS5461A tem-
perature measurement algorithm
If Toff= -0.09566 and Tgain = 23.507 for a Celsius scale,
then the modified values are Toff
= -0.09079
(0xF460E1) and Tgain = 42.3132 (0x54A05E) for a
Fahrenheit scale.
5.9 Vol tage Reference
The CS5463 is specified for operation with a +2.5 V ref-
erence between the VREFIN and AGND pins. To utilize
the on-chip 2.5 V reference, connect the VREFOUT pin
to the VREFIN pin of the device. The VREFIN can be
used to connect external filtering and/or references.
5.10 System Initialization
Upon powering up, the digital circuitry is held in reset
until the analog voltage reaches 4.0 V. At that time, an
eight-XIN-clock-period delay is enabled to allow the os-
cillator to stabilize. The CS5463 will then initialize.
A hardware reset is initiated when the RESET pin is as-
serted with a minimum pulse width of 50 ns. The RE-
SET signal is asynchronous, with a Schmitt-trigger
input. Once the RESET pin is de-asserted, an
eight-XIN-clock-period delay is enabled.
A software reset is initiated by writing the command
0x80. After a hardware or software reset, the internal
registers (some of which drive output pins) will be reset
to their default values. Status bit DRDY in the Status
Register,indicates the CS5463 is in its active state and
ready to receive commands.
5.11 Power-down StatesThe CS5463 has two power-down states, Stand-byand
Sleep. In the stand-by state all circuitry except the volt-
age reference and crystal oscillator is turned off. To re-
turn the device to the active state, a power-up command
is sent to the device.
In Sleep state, all circuitry except the instruction decod-
er is turned off. When the power-up command is sent to
the device, a system initialization is performed (See
Section 5.10 System Initializationon page 20).
5.12 Oscillator Characteristics
XIN and XOUT are the input and output of an invertingamplifier configured as an on-chip oscillator, as shown
in Figure 10. The oscillator circuit is designed to work
with a quartz crystal. To reduce circuit cost, two load ca-
pacitors C1 and C2 are integrated in the device, from
XIN to DGND, and XOUT to DGND. PCB trace lengths
should be minimized to reduce stray capacitance. To
2240 samples
MCLK K 1024---------------------------------------- 0.56 sec=
Tof f
Tof f
T 2.737649 104
+=
Tof f
0.0951126 2.0 2.737649 104
+ 0.09566= =
Fo 9
5--- C
o17.7778+ =
T Fo
95--- T
gain
T Co
Tof f
17.7778 2.737649 104
+
+=
OscillatorCircuit
DGND
XIN
XOUT
C1
C1 = 22 pF
C2
C2 =
Figure 10. Oscillator Connection
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drive the device from an external clock source, XOUT
should be left unconnected while XIN is driven by the
external circuitry. There is an amplifier between XIN and
the digital section which provides CMOS level signals.
This amplifier works with sinusoidal inputs so there are
no problems with slow edge times.The CS5463 can be driven by an external oscillator
ranging from 2.5 to 20 MHz, but the K divider value must
be set such that the internal MCLK will run somewhere
between 2.5 MHz and 5 MHz. The K divider value is set
with the K[3:0] bits in the Configuration Register. As an
example, if XIN = MCLK = 15 MHz, and K is set to 5,
DCLK will equal 3 MHz, which is a valid value for DCLK.
5.13 Event Handler
The INT pin is used to indicate that an internal error or
event has taken place in the CS5463. Writing a logic 1
to any bit in the Mask Registerallows the corresponding
bit in the Status Registerto activate the INT pin. The in-
terrupt condition is cleared by writing a logic 1 to the bit
that has been set in the Status Register.
The behavior of the INT pin is controlled by the IMODE
and IINV bits of the Configuration Register.
If the interrupt output signal format is set for either falling
or rising edge, the duration of the INT pulse will be at
least one DCLK cycle (DCLK = MCLK/K).
5.13.1 Typical Interrupt Handler
The steps below show how interrupts can be handled.
INITIALIZATION:
1) All Status bits are cleared by writing 0xFFFFFF tothe Status Register.
2) The condition bits which will be used to generate
interrupts are then set to logic 1 in the Mask Reg-
ister.
3) Enable interrupts.
INTERRUPT HANDLER ROUTINE:
4) Read the Status Register.
5) Disable all interrupts.
6) Branch to the proper interrupt service routine.
7) Clear the Status Register by writing back the readvalue in step 4.
8) Re-enable interrupt
9) Return from interrupt service routine.
This handshaking procedure ensures that any new in-
terrupts activated between steps 4 and 7 are not lost
(cleared) by step 7.
5.14 Serial Port Overview
The CS5463 incorporates a serial port transmit and re-
ceive buffer with a command decoder that interprets
one-byte (8-bit) commands as they are received. There
are four types of commands: instructions, synchroniz-
ing, register writes, and register reads (See Section
5.16 Commandson page 23).
Instructions are one byte in length and will interrupt any
instruction currently executing. Instructions do not affect
register reads currently being transmitted.
Synchronizing commands are one byte in length and
only affect the serial interface. Synchronizing com-
mands do not affect operations currently in progress.
Register writes must be followed by three bytes of data.
Register reads can return up to four bytes of data.
Commands and data are transferred most-significant bit(MSB) first. Figure 1 on page 12, defines the serial port
timing and required sequence necessary for writing to
and reading from the serial port receive and transmit
buffer, respectively. While reading data from the serial
port, commands and data can be written simultaneous-
ly. Starting a new register read command while data is
being read will terminate the current read in progress.
This is acceptable if the remainder of the current read
data is not needed. During data reads, the serial port re-
quires input data. If a new command and data is not
sent, SYNC0 or SYNC1 must be sent.
5.14.1 Serial Port InterfaceThe serial port interface is a 4-wire synchronous serial
communications interface. The interface is enabled to
start excepting SCLKs when CS (Chip Select) is assert-
ed (logic 0). SCLK (Serial bit-clock) is a Schmitt-trigger
input that is used to strobe the data on SDI (Serial Data
In) into the receive buffer and out of the transmit buffer
onto SDO (Serial Data Out).
IMODE IINV INT Pin
0 0 Active-low Level
0 1 Active-high Level
1 0 Low Pulse
1 1 High Pulse
Table 4. Interrupt Configuration
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If the serial port interface becomes unsynchronized with
respect to the SCLK input, any attempt to clock valid
commands into the serial interface may result in unex-
pected operation. Therefor, the serial port interface
must then be re-initialized by one of the following ac-
tions:- Drive the CSpin high, then low.
- Hardware Reset (drive RESET pin low for at
least 10 s).
- Issue the Serial Port Initialization Sequence,
which is 3 (or more) SYNC1 command bytes
(0xFF) followed by one SYNC0 command byte
(0xFE).
If a re-synchronization is necessary, it is best to re-ini-
tialize the part either by hardware or software reset
(command 0x80), as the state of the part may be un-
known.
5.15 Register Paging
Read/write commands access one of the 32 registers
within a specified page. By default, Page = 0. To access
registers in another page, the Page Register(address
0x1F) must be written with the desired page number.
Example:
Reading register 6 in page 3.
1. Write 3 to page register with command and data:
0x7E 0x00 0x00 0x03
2. Read register 6 with command:
0x0C 0xFF 0xFF 0xFF
0xFFF
0x000
0x3FF
Hardware Registers*
32 Pages
Software Register*
32 Pages
ROM2048 Words
0x400
0x7FF0x800
Pages
0x40 - 0x7F
Pages
0x20 - 0x3F
Pages
0 - 0x1F
* Accessed using register read/write commands.
Figure 11. CS5463 Memory Map
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5.16 Commands
All commands are 8 bits in length. Any command byte value that is not listed in this section is invalid. Commands
that write to registers must be followed by 3 bytes of data. Commands that read data can be chained with other com-
mands (e.g., while reading data, a new command can be sent which can execute during the original read). All com-
mands except register reads, register writes, and SYNC0 & SYNC1 will abort any currently executing commands.
5.16.1 Start Conversions
Initiates acquiring measurements and calculating results. The device has two modes of acquisition.
C3 Modes of acquisition/measurement
0 = Perform a single computation cycle
1 = Perform continuous computation cycles
5.16.2 SYNC0 and SYNC1
The serial port can be initialized by asserting CS or by sending three or more consecutive SYNC1 commands fol-
lowed by a SYNC0 command. The SYNC0 or SYNC1 can also be sent while sending data out.
SYNC 0 = Last byte of a serial port re-initialization sequence.
1 = Used during reads and serial port initialization.
5.16.3 Power-up/Halt
If the device is powered-down, Power-Up/Halt will initiate a power on reset. If the part is already powered-on, all
computations will be halted.
5.16.4 Power-down and Software Reset
To conserve power the CS5463 has two power-down states. In stand-by state all circuitry, except the analog/digital
clock generators, is turned off. In the sleep state all circuitry, except the command decoder, is turned off. Bringing
the CS5463 out of sleep state requires more time than out of stand-by state, because of the extra time needed tore-start and re-stabilize the analog oscillator.
S[1:0] Power-down state
00 = Software Reset
01 = Halt and enter stand-by power saving state. This state allows quick power-on
10 = Halt and enter sleep power saving state.
11 = Reserved
B7 B6 B5 B4 B3 B2 B1 B0
1 1 1 0 C3 0 0 0
B7 B6 B5 B4 B3 B2 B1 B0
1 1 1 1 1 1 1 SYNC
B7 B6 B5 B4 B3 B2 B1 B0
1 0 1 0 0 0 0 0
B7 B6 B5 B4 B3 B2 B1 B0
1 0 0 S1 S0 0 0 0
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5.16.5 Register Read/Write
The Read/Write informs the command decoder that a register access is required. During a readoperation, the ad-dressed register is loaded into an output buffer and clocked out by SCLK. During a writeoperation, the data is
clocked into an input buffer and transferred to the addressed register upon completion of the 24thSCLK.
W/R Write/Read control
0 = Read
1 = Write
RA[4:0] Register address bits (bits 5 through 1) of the read/write command.
Register Page 0
Address RA[4:0] Name Description
0 00000 Config Configuration
1 00001 IDCoff Current DC Offset2 00010 Ign Current Gain
3 00011 VDCoff Voltage DC Offset
4 00100 Vgn Voltage Gain
5 00101 Cycle Count Number of A/D conversions used in one computation cycle (N)).
6 00110 PulseRateE Sets the E1, E2 and E3 energy-to-frequency output pulse rate.
7 00111 I Instantaneous Current
8 01000 V Instantaneous Voltage
9 01001 P Instantaneous Power
10 01010 PActive Active (Real) Power
11 01011 IRMS RMS Current
12 01100 VRMS RMS Voltage
13 01101 (Epsilon) Ratio of line frequency to output word rate (OWR)14 01110 Poff Power Offset15 01111 Status Status
16 10000 IACoff Current AC (RMS) Offset
17 10001 VACoff Voltage AC (RMS) Offset
18 10010 Mode Operation Mode
19 10011 T Temperature
20 10100 QAVG Average Reactive Power
21 10101 Q Instantaneous Reactive Power
22 10110 IPeak Peak Current
23 10111 VPeak Peak Voltage
24 11000 QTrig Reactive Power calculated from Power Triangle
25 11001 PF Power Factor
26 11010 Mask Interrupt Mask
27 11011 S Apparent Power 28 11100 Ctrl Control
29 11101 PH Harmonic Active Power
30 11110 PF Fundamental Active Power
31 11111 QF Fundamental Reactive Power / Page
Note: For proper operation, do notattempt to write to unspecified registers.
B7 B6 B5 B4 B3 B2 B1 B0
0 W/R RA4 RA3 RA2 RA1 RA0 0
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Register Page 1
Address RA[4:0] Name Description
0 00000 PulseWidth Energy Pulse Output Width
1 00001 LoadMin No Load Threshold
2 00010 TGain
Temperature Sensor Gain
3 00011 Toff Temperature Sensor Offset
Register Page 3
Address RA[4:0] Name Description
6 00110 VSAGDuration Voltage sag sample interval
7 00111 VSAGLevel Voltage sag level
10 01010 ISAGDuration Current fault sample interval
11 01011 ISAGLevel Current fault level
Note: For proper operation, do notattempt to write to unspecified registers.
5.16.6 Calibration
The CS5463 can perform system calibrations. Proper input signals must be applied to the current and voltage chan-
nel before performing a designated calibration.
CAL[4:0]* Designates calibration to be performed
01001 = Current channel DC offset
01010 = Current channel DC gain
01101 = Current channel AC offset
01110 = Current channel AC gain
10001 = Voltage channel DC offset
10010 = Voltage channel DC gain
10101 = Voltage channel AC offset
10110 = Voltage channel AC gain
11001 = Current and Voltage channel DC offset
11010 = Current and Voltage channel DC gain
11101 = Current and Voltage channel AC offset
11110 = Current and Voltage channel AC gain
*For proper operation, values for CAL[4:0] not specified should not be used.
B7 B6 B5 B4 B3 B2 B1 B0
1 1 0 CAL4 CAL3 CAL2 CAL1 CAL0
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6. REGISTER DESCRIPTION
1. Default = bit status after power-on or reset
2. Any bit not labeled is Reserved. A zero should always be used when writing to one of these bits.
6.1 Page 0 Registers
6.1.1 Configuration Register ( Config )Address: 0
Default = 0x000001
PC[6:0] Phase compensation. A 2s complement number which sets a delay in the voltage channel rel-
ative to the current channel. Default setting is 0000000 = 0.0215 degree phase delay at 60 Hz
(when MCLK = 4.096 MHz). See Section 7.2 Phase Compensationon page 39for more infor-
mation.
Igain Sets the gain of the current PGA.
0 = Gain is 10 (default)
1 = Gain is 50
EWA Allows the E1 and E2 pins to be configured as open-collector output pins.
0 = Normal outputs (default)
1 = Only the pull-down device of the E1 and E2 pins are active
IMODE, IINV Interrupt configuration bits. Select the desired pin behavior for indication of an interrupt.00 = Active-low level (default)
01 = Active-high level
10 = High-to-low pulse
11 = Low-to-high pulse
iCPU Inverts the CPUCLK clock. In order to reduce the level of noise present when analog signals
are sampled, the logic driven by CPUCLK should not be active during the sample edge.
0 = Normal operation (default)
1 = Minimize noise when CPUCLK is driving rising edge logic
K[3:0] Clock divider. A 4-bit binary number used to divide the value of MCLK to generate the internal
clock DCLK. The internal clock frequency is DCLK = MCLK/K. The value of K can range be-
tween 1 and 16. Note that a value of 0000 will set K to 16 (not zero). K = 1 at reset.
23 22 21 20 19 18 17 16
PC6 PC5 PC4 PC3 PC2 PC1 PC0 Igain
15 14 13 12 11 10 9 8
EWA - - IMODE IINV - - -
7 6 5 4 3 2 1 0
- - - iCPU K3 K2 K1 K0
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6.1.2 Current and Voltage DC Offset Regis ter ( IDCoff , VDCoff )Address: 1 (Current DC Offset); 3 (Voltage DC Offset)
Default = 0x000000
The DC Offset registers (IDCoff,VDCoff) are initialized to 0.0 on reset. When DC Offset calibration is performed, the
register is updated with the DC offset measured over a computation cycle. DRDY will be set at the end of the
calibration. This register may be read and stored for future system offset compensation. The value is represent-
ed in two's complement notation and in the range of -1.0 IDCoff, VDCoff 1.0, with the binary point to the right ofthe MSB. See Section 7.1.2.1 DC Offset Calibration Sequenceon page 37for more information.
6.1.3 Current and Voltage Gain Register ( Ign , Vgn )Address: 2 (Current Gain); 4 (Voltage Gain)
Default = 0x400000 = 1.000
The gain registers (Ign,Vgn)are initialized to 1.0 on reset. When either a AC or DC Gain calibration is performed,
the register is updated with the gain measured over a computation cycle. DRDY will be set at the end of the
calibration. This register may be read and stored for future system gain compensation. The value is in the range
0.0 Ign,Vgn < 3.9999, with the binary point to the right of the second MSB.
6.1.4 Cycle Count Register ( Cycle Count )Address: 5
Default = 0x000FA0 = 4000
Cycle Count, denoted as N, determines the length of one computation cycle. During continuous conversions,
the computation cycle frequency is (MCLK/K)/(1024N). A one second computational cycle period occurs whenMCLK = 4.096 MHz, K = 1, and N = 4000.
6.1.5 PulseRateE Register ( PulseRateE )Address: 6
Default = 0x800000 = 1.00 (2 kHz @ 4.096 MHz MCLK)
PulseRateE sets the frequency of E1, E2, & E3pulses. E1, E2, E3 frequency = (MCLK x PulseRateE) / 2048 at
full scale. For a 4 khz sample rate, the maximum pulse rate is 2 khz. The value is represented in two's comple-
ment notation and in the range is -1.0 PulseRateE 1.0, with the binary point to the right of the MSB. Negativevalues have the same effect as positive. See Section 5.5 Energy Pulse Outputon page 17for more information.
MSB LSB
-(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23
MSB LSB
21
20
2-1
2-2
2-3
2-4
2-5
2-6
..... 2-16
2-17
2-18
2-19
2-20
2-21
2-22
MSB LSB
223 222 221 220 219 218 217 216 ..... 26 25 24 23 22 21 20
MSB LSB
-(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23
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6.1.6 Instantaneous Current , Vol tage, and Power Registers ( I , V , P )Address: 7 (Instantaneous Current); 8 (Instantaneous Voltage); 9 (Instantaneous Power)
I and V contain the instantaneous measured values for current and voltage, respectively. The instantaneous
voltage and current samples are multiplied to obtain Instantaneous Power (P). The value is represented in two's
complement notation and in the range of -1.0 I, V, P 1.0, with the binary point to the right of the MSB.
6.1.7 Active (Real) Power Register ( PActive )Address: 10 (Active Power)
The instantaneous power is averaged over each computation cycle (N conversions) to compute Active Power
(PActive). The value will be within in the range of -1.0 PActive 1.0. The value is represented in two's complementnotation, with the binary point to the right of the MSB.
6.1.8 RMS Current & Voltage Regis ters ( IRMS, VRMS )Address: 11 (IRMS); 12 (VRMS)
IRMSand VRMScontain the Root Mean Square (RMS) values of I and V, calculated each computation cycle. The
value is represented in unsigned binary notation and in the range of 0.0 IRMS, VRMS 1.0, with the binary pointto the left of the MSB.
6.1.9 Epsi lon Regis ter ( )Address: 13
Default = 0x01999A = 0.0125 sec
Epsilon () is the ratio of the input line frequency to the sample frequency of the ADC (See Section 5.4 Perform-ing Measurementson page 16). Epsilon is either written to the register, or measured during conversions. The
value is represented in two's complement notation and in the range of -1.0 1.0, with the binary point to theright of the MSB. Negative values have no significance.
MSB LSB
-(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23
MSB LSB
-(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23
MSB LSB
2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 ..... 2-18 2-19 2-20 2-21 2-22 2-23 2-24
MSB LSB
-(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23
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6.1.10 Power Offset Register ( Poff )Address: 14
Default = 0x000000
Power Offset (Poff) is added to the instantaneous power being accumulated in the Pactive register, and can be
used to offset contributions to the energy result that are caused by undesirable sources of energy that are in-
herent in the system. The value is represented in two's complement notation and in the range of -1.0 Poff 1.0,with the binary point to the right of the MSB.
6.1.11 Status Register and Mask Register ( Status , Mask )Address:15(Status Register); 26 (Mask Register)
Default = 0x800001 (Status Register), 0x000000 (Mask Register)
The Status Register indicates status within the chip. In normal operation, writing a '1' to a bit will cause the bit
to reset. Writing a '0' to a bit will not change its current state.
The Mask Register is used to control the activation of the INT pin. Placing a logic '1' in a Mask bit will allow the
corresponding bit in the Status Register to activate the INT pin when the status bit is asserted.
DRDY Data Ready. During conversions, this bit will indicate the end of computation cycles. For cali-brations, this bit indicates the end of a calibration sequence.
CRDY Conversion Ready. Indicates a new conversion is ready. This will occur at the output word rate.
IOR Current Out of Range. Set when the Instantaneous Current Registeroverflows.
VOR Voltage Out of Range. Set when the Instantaneous Voltage Register overflows.
IROR IRMSOut of Range. Set when the IRMSRegisteroverflows.
VROR VRMSOut of Range. Set when the VRMSRegisteroverflows.
EOR Energy Out of Range. Set when PACTIVE overflows.
IFAULT Indicates a current fault has occurred. See Section 5.6 Sag and Fault Detect Featureon page
19.
VSAG Indicates a voltage sag has occurred. See Section 5.6 Sag and Fault Detect Featureon page
19.
TUP Temperature Updated. Indicates the Temperature Registerhas updated.
TOD Modulator oscillation detected on the temperature channel. Set when the modulator oscillates
due to an input above full scale.
VOD (IOD) Modulator oscillation detected on the voltage (current) channel. Set when the modulator oscil-
MSB LSB
-(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23
23 22 21 20 19 18 17 16
DRDY CRDY IOR VOR
15 14 13 12 11 10 9 8
IROR VROR EOR IFAULT VSAG
7 6 5