enhanced-jfet low-power low-offset operational … tl03xa enhanced-jfet low-power low-offset...

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TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C - FEBRUARY 1997 - REVISED DECEMBER 2001 1 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 D Direct Upgrades for the TL06x Low-Power BiFETs D Low Power Consumption . . . 6.5 mW/Channel Typ D On-Chip Offset-Voltage Trimming for Improved DC Performance (1.5 mV, TL031A) D Higher Slew Rate and Bandwidth Without Increased Power Consumption D Available in TSSOP for Small Form-Factor Designs description The TL03x series of JFET-input operational amplifiers offer improved dc and ac characteristics over the TL06x family of low-power BiFET operational amplifiers. On-chip zener trimming of offset voltage yields precision grades as low as 1.5 mV (TL031A) for greater accuracy in dc-coupled applications. The Texas Instruments improved BiFET process and optimized designs also yield improved bandwidths and slew rates without increased power consumption. The TL03x devices are pin-compatible with the TL06x and can be used to upgrade existing circuits or for optimal performance in new designs. BiFET operational amplifiers offer the inherently higher input impedance of the JFET-input transistors without sacrificing the output drive associated with bipolar amplifiers. This higher input impedance makes the TL3x amplifiers better suited for interfacing with high-impedance sensors or very low-level ac signals. These devices also feature inherently better ac response than bipolar or CMOS devices having comparable power consumption. The TL03x family has been optimized for micropower operation, while improving on the performance of the TL06x series. Designers requiring significantly faster ac response should consider the ExcaliburTLE206x family of low-power BiFET operational amplifiers. Because BiFET operational amplifiers are designed for use with dual power supplies, care must be taken to observe common-mode input-voltage limits and output swing when operating from a single supply. DC biasing of the input signal is required, and loads should be terminated to a virtual-ground node at midsupply. The TI TLE2426 integrated virtual-ground generator is useful when operating BiFET amplifiers from single supplies. The TL03x devices are fully specified at ±15 V and ±5 V. For operation in low-voltage and/or single-supply systems, the TI LinCMOS families of operational amplifiers (TLC prefix) are recommended. When moving from BiFET to CMOS amplifiers, particular attention should be paid to slew rate, bandwidth requirements, and output loading. The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized for operation from -40°C to 85°C. The M-suffix devices are characterized for operation over the full military temperature range of -55°C to 125°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Excalibur is a trademark of Texas Instruments.

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Page 1: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSET

OPERATIONAL AMPLIFIERSSLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

� Direct Upgrades for the TL06x Low-PowerBiFETs

� Low Power Consumption . . .6.5 mW/Channel Typ

� On-Chip Offset-Voltage Trimming forImproved DC Performance(1.5 mV, TL031A)

� Higher Slew Rate and Bandwidth WithoutIncreased Power Consumption

� Available in TSSOP for Small Form-FactorDesigns

description

The TL03x series of JFET-input operational amplifiers offer improved dc and ac characteristics over the TL06xfamily of low-power BiFET operational amplifiers. On-chip zener trimming of offset voltage yields precisiongrades as low as 1.5 mV (TL031A) for greater accuracy in dc-coupled applications. The Texas Instrumentsimproved BiFET process and optimized designs also yield improved bandwidths and slew rates withoutincreased power consumption. The TL03x devices are pin-compatible with the TL06x and can be used toupgrade existing circuits or for optimal performance in new designs.

BiFET operational amplifiers offer the inherently higher input impedance of the JFET-input transistors withoutsacrificing the output drive associated with bipolar amplifiers. This higher input impedance makes the TL3xamplifiers better suited for interfacing with high-impedance sensors or very low-level ac signals. These devicesalso feature inherently better ac response than bipolar or CMOS devices having comparable powerconsumption.

The TL03x family has been optimized for micropower operation, while improving on the performance of theTL06x series. Designers requiring significantly faster ac response should consider the Excalibur™ TLE206xfamily of low-power BiFET operational amplifiers.

Because BiFET operational amplifiers are designed for use with dual power supplies, care must be taken toobserve common-mode input-voltage limits and output swing when operating from a single supply. DC biasingof the input signal is required, and loads should be terminated to a virtual-ground node at midsupply. The TITLE2426 integrated virtual-ground generator is useful when operating BiFET amplifiers from single supplies.

The TL03x devices are fully specified at ±15 V and ±5 V. For operation in low-voltage and/or single-supplysystems, the TI LinCMOS families of operational amplifiers (TLC prefix) are recommended. When moving fromBiFET to CMOS amplifiers, particular attention should be paid to slew rate, bandwidth requirements, and outputloading.

The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterizedfor operation from −40°C to 85°C. The M-suffix devices are characterized for operation over the full militarytemperature range of −55°C to 125°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright © 2001, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.

Excalibur is a trademark of Texas Instruments.

Page 2: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSETOPERATIONAL AMPLIFIERSSLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

2

3

4

8

7

6

5

OFFSET N1IN−IN+

VCC−

NCVCC+OUTOFFSET N2

3 2 1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

NCVCC+

NCOUTNC

NCIN−NCIN+NC

NC

OF

FS

ET

N1

NC

NC

NC

NC

OF

FS

ET

N2

NC

NC

VC

C−

TL031x, TL031AxD, JG, OR P PACKAGE

(TOP VIEW)

1

2

3

4

8

7

6

5

1OUT1IN−1IN+

VCC −

VCC+2OUT2IN−2IN+

3 2 1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

NC2OUTNC2IN−NC

NC1IN−

NC1IN+

NC

NC

1OU

TN

C

NC

NC

NC

2IN

+N

C

CC

−V

CC

+V

TL031M, TL031AMFK PACKAGE(TOP VIEW) TL032M, TL032AM

FK PACKAGE(TOP VIEW)

TL032x, TL032AxD, JG, OR P PACKAGE

(TOP VIEW)

3 2 1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

4IN+NCVCC−

NC3IN+

1IN+NC

VCC+

NC2IN+

1IN

−1O

UT

NC

3IN

2IN

NC

3OU

T4O

UT

4IN

2OU

T

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1OUT1IN−1IN+VCC+

2IN+2IN−

2OUT

4OUT4IN−4IN+VCC−

3IN+3IN−3OUT

TL034x, TL034AxD, J, N, OR PW PACKAGE

(TOP VIEW)

TL034M, TL034AMFK PACKAGE(TOP VIEW)

NC − No internal connection

Page 3: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSET

OPERATIONAL AMPLIFIERSSLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AVAILABLE OPTIONS

PACKAGED DEVICES

TAVIOMAXAT 25°C

SMALLOUTLINE

(D)

CHIPCARRIER

(FK)

CERAMICDIP(J)

CERAMICDIP(JG)

PLASTICDIP(N)

PLASTICDIP(P)

TSSOP(PW)

0.8 mVTL031ACDTL032ACD

— — — —TL031ACPTL032ACP

0°C to 70°C 1.5 mVTL031CDTL032CDTL034ACD

— — — TL034ACNTL031CPTL032CP

4 mV TL034CD — — — TL034CN — TL034CPW

0.8 mVTL031AIDTL032AID

— — — —TL031AIPTL032AIP

−40°C to 85°C 1.5 mVTL031IDTL032IDTL034AID

— — — TL034AINTL031IPTL032IP

4 mV TL034ID — — — TL034IN — —

0.8 mVTL031AMDTL032AMD

TL031AMFKTL032AMFK

—TL031AMJGTL032AMJG

—TL031AMPTL032AMP

−55°C to 125°C1.5 mV

TL031MDTL032MDTL034AMD

TL031MFKTL032MFKTL034AMFK

TL034AMJTL031MJGTL032MJG

TL034AMNTL031MPTL032MP

4 mV TL034MD TL034MFK TL034MJ — TL034MN — —

The D and PW packages are available taped and reeled and are indicated by adding an R suffix to device type (e.g., TL034CDR or TL034CPWR).

Page 4: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSETOPERATIONAL AMPLIFIERSSLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

symbol (each amplifier)

+OUT

IN−

IN+

equivalent schematic (each amplifier)

R2

OFFSET N2OFFSET N1

IN−

IN+

Q2

Q3

Q5

VCC+

Q14

Q6R4

Q8 Q10 R7

Q11

R6

Q12

R3

C1

Q9

Q7

Q4

R5R1

Q1

JF1 JF2

Q13

Q16R8

JF3 JF4

Q15Q17

OUT

D1

VCC−

NOTE A: OFFSET N1 and OFFSET N2 are available only on the TL031, TL031A.

See Note A

Page 5: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSET

OPERATIONAL AMPLIFIERSSLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†

Supply voltage (see Note 1): VCC+ 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC− −18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Differential input voltage, VID (see Note 2) ±30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage, VI (any input) (see Notes 1 and 3) ±15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input current, II (each input) ±1 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output current, IO (each output) ±40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Total current into VCC+ 160 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Total current out of VCC− 160 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Duration of short-circuit current at (or below) 25°C (see Note 4) Unlimited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package thermal impedance, θJA (see Note 5): D package (8 pin) 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . .

D package (14 pin) 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P package 85°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1 /16 inch) from case for 10 seconds: D, N, P, or PW package 260°C. . . . . . . . . Lead temperature 1,6 mm (1 /16 inch) from case for 60 seconds: J or JG package 300°C. . . . . . . . . . . . . . . Case temperature for 60 seconds: FK package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC−.2. Differential voltages are at IN+ with respect to IN−.3. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less.4. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum

dissipation rating is not exceeded.5. The package thermal impedance is calculated in accordance with JESD 51-7.

DISSIPATION RATING TABLE

PACKAGETA ≤ 25°C

POWER RATINGDERATING FACTOR

ABOVE TA = 25°CTA = 70°C

POWER RATINGTA = 85°C

POWER RATINGTA = 125°C

POWER RATING

FK 1375 mW 11.0 mW/°C 880 mW 715 mW 275 mW

J 1375 mW 11.0 mW/°C 880 mW 715 mW 275 mW

JG 1050 mW 8.4 mW/°C 672 mW 546 mW 210 mW

recommended operating conditions

C SUFFIX I SUFFIX M SUFFIXUNIT

MIN MAX MIN MAX MIN MAXUNIT

VCC± Supply voltage ±5 ±15 ±5 ±15 ±5 ±15 V

V Common mode input voltageVCC± = ±5 V −1.5 4 −1.5 4 −1.5 4

VVIC Common-mode input voltageVCC± = ±15 V −11.5 14 −11.5 14 −11.5 14

V

TA Operating free-air temperature 0 70 −40 85 −55 125 °C

Page 6: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSETOPERATIONAL AMPLIFIERSSLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL031C and TL031AC electrical characteristics at specified free-air temperature

TL031C, TL031AC

PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA

MIN TYP MAX MIN TYP MAX

UNIT

TL031C25°C 0.54 3.5 0.5 1.5

V Input offset voltageVO = 0,V 0

TL031CFull range† 4.5 2.5

mVVIO Input offset voltage VIC = 0,RS = 50 Ω TL031AC

25°C 0.41 2.8 0.34 0.8mV

RS = 50 Ω TL031ACFull range† 3.8 1.8

TL031C25°C to

7 1 5 9�

Temperature coefficient ofVO = 0,V 0

TL031C25 C to 70°C 7.1 5.9

V/°C�VIOTemperature coefficient ofinput offset voltage

VIC =0, RS = 50 Ω TL031AC

25°C to7 1 5 9 25

μV/°Cinput offset voltage RS = 50 Ω TL031AC

25 C to 70°C 7.1 5.9 25

Input offset voltagelong-term drift‡

VO = 0, VIC =0, RS = 50 Ω

25°C 0.04 0.04 μV/mo

I Input offset currentVO = 0, VIC = 0 25°C 1 100 1 100

pAIIO Input offset currentVO = 0, VIC = 0See Figure 5 70°C 9 200 12 200

pA

I Input bias currentVO = 0, VIC = 0 25°C 2 200 2 200

pAIIB Input bias currentVO = 0, VIC = 0See Figure 5 70°C 50 400 80 400

pA

VCommon-mode input

25°C−1.5to 4

−3.4to 5.4

−11.5to 14

−13.4to 15.4

VVICRCommon mode inputvoltage range

Full range† −1.5to 4

−11.5to 14

V

M i iti k25°C 3 4.3 13 14

VOM+Maximum positive peakoutput voltage swing RL = 10 kΩ 0°C 3 4.2 13 14 VVOM+ output voltage swing RL 10 kΩ

70°C 3 4.3 13 14

V

M i ti k25°C −3 −4.2 −12.5 −13.9

VOM−Maximum negative peakoutput voltage swing RL = 10 kΩ 0°C −3 −4.1 −12.5 −13.9 VVOM− output voltage swing RL 10 kΩ

70°C −3 −4.2 −12.5 −14

V

25°C 4 12 5 14.3

AVDLarge-signal differentialvoltage amplification§ RL = 10 kΩ 0°C 3 11.1 4 13.5 V/mVAVD voltage amplification§ RL 10 kΩ

70°C 4 13.3 5 15.2

V/mV

ri Input resistance 25°C 1012 1012 Ω

ci Input capacitance 25°C 5 4 pF

C d V V i25°C 70 87 75 94

CMRRCommon-moderejection ratio

VIC = VICRmin,VO = 0 RS = 50 Ω 0°C 70 87 75 94 dBCMRR rejection ratio VO = 0, RS = 50 Ω

70°C 70 87 75 94

dB

Supply-voltage 25°C 75 96 75 96

kSVR

Supply-voltage rejection ratio VO = 0, RS = 50 Ω 0°C 75 96 75 96 dBSVR rejection ratio(ΔVCC±/ΔVIO)

O , S

70°C 75 96 75 96

† Full range is 0°C to 70°C.‡ Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated to

TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.§ At VCC± = ±5 V, VO = ±2.3 V; at VCC± = ±15 V, VO = ±10 V

Page 7: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSET

OPERATIONAL AMPLIFIERSSLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL031C and TL031AC electrical characteristics at specified free-air temperature (continued)

TL031C, TL031AC

PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA

MIN TYP MAX MIN TYP MAX

UNIT

25°C 1.9 2.5 6.5 8.4

PD Total power dissipation VO = 0, No load 0°C 1.8 2.5 6.3 8.4 mWPD Total power dissipation VO 0, No load

70°C 1.9 2.5 6.3 8.4

mW

25°C 192 250 217 280

ICC Supply current VO = 0, No load 0°C 184 250 211 280 μACC pp y O ,

70°C 189 250 210 280

μ

TL031C and TL031AC operating characteristics at specified free-air temperature

TL031C, TL031AC

PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA

MIN TYP MAX MIN TYP MAX

UNIT

R 10 kΩ C 100 F25°C 2 1.5 2.9

SR+ Positive slew rate atunity gain†

RL = 10 kΩ, CL = 100 pFSee Figure 1

0°C 1.8 1 2.6 V/μsSR+unity gain† See Figure 1

70°C 2.2 1.5 3.2

V/μs

R 10 kΩ C 100 F25°C 3.9 1.5 5.1

SR− Negative slew rate atunity gain†

RL = 10 kΩ, CL = 100 pFSee Figure 1

0°C 3.7 1.5 5 V/μsSRunity gain† See Figure 1

70°C 4 1.5 5

V/μs

VI(PP) = ±10 mV, 25°C 138 132

tr Rise timeVI(PP) = ±10 mV,RL = 10 kΩ, CL = 100 pF 0°C 134 127 nstr Rise time RL 10 kΩ, CL 100 pFSee Figures 1 and 2 70°C 150 142

ns

VI(PP) = ±10 mV, 25°C 138 132

tf Fall timeVI(PP) = ±10 mV,RL = 10 kΩ, CL = 100 pF 0°C 134 127 nstf Fall time RL 10 kΩ, CL 100 pFSee Figure 1 70°C 150 142

ns

VI(PP) = ±10 mV, 25°C 11% 5%

Overshoot factorVI(PP) = ±10 mV,RL = 10 kΩ, CL = 100 pF 0°C 10% 4%Overshoot factor RL 10 kΩ, CL 100 pFSee Figures 1 and 2 70°C 12% 6%

TL031Cf = 10 Hz

25°C61 61

V Equivalent inputTL031C

RS = 20 Ω f = 1 kHz25°C

41 41nV/√HVn

Equivalent inputnoise voltage

TL031AC

RS = 20 ΩSee Figure 3 f = 10 Hz

25°C61 61

nV/√Hzg

TL031ACf = 1 kHz

25°C41 41 60

InEquivalent input noisecurrent

f = 1 kHz 25°C 0.003 0.003 pA/√Hz

VI = 10 mV 25°C 1 1.1

B1 Unity-gain bandwidthVI = 10 mVRL = 10 kΩ, CL = 25 pF 0°C 1 1.1 MHzB1 Unity gain bandwidth RL 10 kΩ, CL 25 pFSee Figure 4 70°C 1 1

MHz

VI = 10 mV 25°C 61° 65°

φm Phase margin at unity gainVI = 10 mVRL = 10 kΩ, CL = 25 pF 0°C 61° 65°φm g y g RL 10 kΩ, CL 25 pFSee Figure 4 70°C 60° 64°

† For VCC± = ±5 V, VI(PP) = ±1 V; for VCC± = ±15 V, VI(PP) = ±5 V

Page 8: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSETOPERATIONAL AMPLIFIERSSLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL031I and TL031AI electrical characteristics at specified free-air temperatureTL031I, TL031AI

PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA

MIN TYP MAX MIN TYP MAXUNIT

TL031I25°C 0.54 3.5 0.5 1.5

V Input offset voltageVO = 0,V 0

TL031IFull range† 5.3 3.3

mVVIO Input offset voltage VIC = 0,RS = 50 Ω TL031AI

25°C 0.41 2.8 0.34 0.8mV

RS = 50 Ω TL031AIFull range† 4.6 2.6

TL031I25°C to

6 5 6 2�

Temperature coefficientf

VO = 0,V 0

TL031I25 C to

85°C 6.5 6.2

V/°C�VIO ofinput offset voltage

VIC = 0,RS = 50 Ω TL031AI

25°C to6 5 6 2 25

μV/°Cinput offset voltage RS = 50 Ω TL031AI

25 C to85°C 6.5 6.2 25

Input offset voltageVO = 0, V 0 25°C 0 04 0 04 V/moInput offset voltage

long-term drift‡VIC = 0,RS = 50 Ω

25°C 0.04 0.04 μV/mo

I Input offset currentVO = 0, VIC = 0 25°C 1 100 1 100 pA

IIO Input offset currentVO = 0, VIC = 0See Figure 5 85°C 0.02 0.45 0.02 0.45 nA

I Input bias currentVO = 0, VIC = 0 25°C 2 200 2 200 pA

IIB Input bias currentVO = 0, VIC = 0See Figure 5 85°C 0.2 0.9 0.2 0.9 nA

VCommon-mode input

25°C−1.5to 4

−3.4to 5.4

−11.5to 14

−13.4to 15.4

VVICRCommon mode inputvoltage range

Full range† −1.5to 4

−11.5to 14

V

M i iti k25°C 3 4.3 13 14

VOM+Maximum positive peakoutput voltage swing RL = 10 kΩ −40°C 3 4.1 13 14 VVOM+ output voltage swing RL 10 kΩ

85°C 3 4.4 13 14

V

M i ti k25°C −3 −4.2 −12.5 −13.9

VOM−Maximum negative peakoutput voltage swing RL = 10 kΩ −40°C −3 −4.1 −12.5 −13.8 VVOM− output voltage swing RL 10 kΩ

85°C −3 −4.2 −12.5 −14

V

25°C 4 12 5 14.3

AVDLarge-signal differentialvoltage amplification§ RL = 10 kΩ −40°C 3 8.4 4 11.6 V/mVAVD voltage amplification§ RL 10 kΩ

85°C 4 13.5 5 15.3

V/mV

ri Input resistance 25°C 1012 1012 Ω

ci Input capacitance 25°C 5 4 pF

C d V V i25°C 70 87 75 94

CMRRCommon-moderejection ratio

VIC = VICRmin,VO = 0 RS = 50 Ω −40°C 70 87 75 94 dBCMRR rejection ratio VO = 0, RS = 50 Ω

85°C 70 87 75 94

dB

Supply-voltage 25°C 75 96 75 96

kSVR

Supply-voltagerejection ratio VO = 0, RS = 50 Ω −40°C 75 96 75 96 dBSVR rejection ratio(ΔVCC±/ΔVIO)

O , S

85°C 75 96 75 96

† Full range is −40°C to 85°C.‡ Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated to

TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.§ At VCC± = ±5 V, VO = ±2.3 V; at VCC± = ±15 V, VO = ±10 V

Page 9: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSET

OPERATIONAL AMPLIFIERSSLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL031I and TL031AI electrical characteristics at specified free-air temperature (continued)TL031I, TL031AI

PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA

MIN TYP MAX MIN TYP MAXUNIT

25°C 1.9 2.5 6.5 8.4

PD Total power dissipation VO = 0, No load −40°C 1.4 2.5 5.4 8.4 mWPD Total power dissipation VO 0, No load

85°C 1.9 2.5 6.2 8.4

mW

25°C 192 250 217 280

ICC Supply current VO = 0, No load −40°C 144 250 181 280 μACC pp y O ,

85°C 189 250 207 280

μ

TL031I and TL031AI operating characteristics at specified free-air temperature

TL031I, TL031AI

PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA

MIN TYP MAX MIN TYP MAX

UNIT

R 10 kΩ C 100 F25°C 2 1.5 2.9

SR+ Positive slew rate atunity gain†

RL = 10 kΩ, CL = 100 pFSee Figure 1

−40°C 1.6 1 2.1 V/μsSR+unity gain† See Figure 1

85°C 2.3 1.5 3.3

V/μs

N ti l t t it R 10 kΩ C 100 F25°C 3.9 1.5 5.1

SR−Negative slew rate at unitygain†

RL = 10 kΩ, CL = 100 pFSee Figure 1

−40°C 3.3 1.5 4.8 V/μsSR gain† See Figure 185°C 4.1 1.5 4.9

V/μs

VI(PP) = ±10 mV, 25°C 138 132

tr Rise timeVI(PP) = ±10 mV,RL = 10 kΩ, CL = 100 pF −40°C 132 123 nstr Rise time RL 10 kΩ, CL 100 pFSee Figures 1 and 2 85°C 154 146

ns

VI(PP) = ±10 mV, 25°C 138 132

tf Fall timeVI(PP) = ±10 mV,RL = 10 kΩ, CL = 100 pF −40°C 132 123 nstf Fall time RL 10 kΩ, CL 100 pFSee Figure 1 85°C 154 146

ns

VI(PP) = ±10 mV, 25°C 11% 5%

Overshoot factorVI(PP) = ±10 mV,RL = 10 kΩ, CL = 100 pF −40°C 12% 5%Overshoot factor RL 10 kΩ, CL 100 pFSee Figures 1 and 2 85°C 13% 7%

TL031If = 10 Hz

25°C61 61

VEquivalent i t

TL031IRS = 20 Ω f = 1 kHz

25°C41 41

nV/√HVn inputnoise voltage TL031AI

RS = 20 ΩSee Figure 3 f = 10 Hz

25°C61 61

nV/√Hznoise voltage TL031AI

f = 1 kHz25°C

41 41 60

IEquivalent input noise

f 1 kHz 25°C 0 003 0 003 pA/√HInEquivalent input noisecurrent f = 1 kHz 25°C 0.003 0.003 pA/√Hz

VI = 10 mV 25°C 1 1.1

B1 Unity-gain bandwidthVI = 10 mVRL = 10 kΩ, CL = 25 pF −40°C 1 1.1 MHzB1 Unity gain bandwidth RL 10 kΩ, CL 25 pFSee Figure 4 85°C 0.9 1

MHz

VI = 10 mV, 25°C 61° 65°

φm Phase margin at unity gainVI = 10 mV,RL = 10 kΩ, CL = 25 pF −40°C 60° 65°φm g y g RL 10 kΩ, CL 25 pFSee Figure 4 85°C 60° 64°

† For VCC± = ±5 V, VI(PP) = ±1 V; for VCC± = ±15 V, VI(PP) = ±5 V

Page 10: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSETOPERATIONAL AMPLIFIERSSLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL031M and TL031AM electrical characteristics at specified free-air temperature

TL031M, TL031AM

PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA

MIN TYP MAX MIN TYP MAX

UNIT

TL031M25°C 0.54 3.5 0.5 1.5

V Input offset voltageVO = 0,V 0

TL031MFull range† 6.5 4.5

mVVIO Input offset voltage VIC = 0,RS = 50 Ω TL031AM

25°C 0.41 2.8 0.34 0.8mV

RS = 50 Ω TL031AMFull range† 5.8 3.8

Temperature coefficient of VO = 0,V 0

TL031M25°C to125°C 5.1 4.3

V/°C�VIO

Temperature coefficient of

input offset voltageVIC = 0,RS = 50 Ω TL031AM

25°C to125°C 5.1 4.3

μV/°C

Input offset voltagelong-term drift‡

VO = 0, VIC = 0,RS = 50 Ω

25°C 0.04 0.04 μV/mo

I Input offset currentVO = 0, VIC = 0 25°C 1 100 1 100 pA

IIO Input offset currentVO = 0, VIC = 0See Figure 5 125°C 0.2 10 0.2 10 nA

I Input bias currentVO = 0, VIC = 0 25°C 2 200 2 200 pA

IIB Input bias currentVO = 0, VIC = 0See Figure 5 125°C 7 20 8 20 nA

VCommon-mode input

25°C−1.5to 4

−3.4to 5.4

−11.5to 14

−13.4to 15.4

VVICRCommon mode inputvoltage range

Full range† −1.5to 4

−11.5to 14

V

M i iti k25°C 3 4.3 13 14

VOM+Maximum positive peakoutput voltage swing RL = 10 kΩ −55°C 3 4.1 13 14 VVOM+ output voltage swing RL 10 kΩ

125°C 3 4.4 13 14

V

M i ti k25°C −3 −4.2 −12.5 −13.9

VOM−Maximum negative peakoutput voltage swing RL = 10 kΩ −55°C −3 −4 −12.5 −13.8 VVOM− output voltage swing RL 10 kΩ

125°C −3 −4.3 −12.5 −14

V

25°C 4 12 5 14.3

AVDLarge-signal differentialvoltage amplification§ RL = 10 kΩ −55°C 3 7.1 4 10.4 V/mVAVD voltage amplification§ RL 10 kΩ

125°C 3 12.9 4 15

V/mV

ri Input resistance 25°C 1012 1012 Ω

ci Input capacitance 25°C 5 4 pF

C d V V i25°C 70 87 75 94

CMRRCommon-moderejection ratio

VIC = VICRmin,VO = 0 RS = 50 Ω −55°C 70 87 70 94 dBCMRR rejection ratio VO = 0, RS = 50 Ω

125°C 70 87 70 94

dB

Supply-voltage 25°C 75 96 75 96

kSVR

Supply-voltage rejection ratio VO = 0, RS = 50 Ω −55°C 75 96 75 95 dBkSVR rejection ratio(ΔVCC±/ΔVIO)

VO 0, RS 50 Ω125°C 75 96 75 96

dB

25°C 1.9 2.5 6.5 8.4

PD Total power dissipation VO = 0, No load −55°C 1.1 2.5 4.7 8.4 mWD p p O ,

125°C 1.8 2.5 5.8 8.4

† Full range is −55°C to 125°C.‡ Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated to

TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.§ At VCC± = ±5 V, VO = ±2.3 V; at VCC± = ±15 V, VO = ±10 V

Page 11: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSET

OPERATIONAL AMPLIFIERSSLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL031M and TL031AM electrical characteristics at specified free-air temperature (continued)

TL031M, TL031AM

PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA

MIN TYP MAX MIN TYP MAX

UNIT

25°C 192 250 217 280

ICC Supply current VO = 0, No load −55°C 114 250 156 280 μACC pp y O ,

125°C 178 250 197 280

μ

TL031M and TL031AM operating characteristics at specified free-air temperature

TL031M, TL031AM

PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA

MIN TYP MAX MIN TYP MAX

UNIT

R 10 kΩ C 100 F25°C 2 1.5 2.9

SR+ Positive slew rate atunity gain†

RL = 10 kΩ, CL = 100 pFSee Figure 1

−55°C 1.4 1 1.9 V/μsSR+unity gain† See Figure 1

125°C 2.4 1 3.5

V/μs

R 10 kΩ C 100 F25°C 3.9 1.5 5.1

SR− Negative slew rate atunity gain†

RL = 10 kΩ, CL = 100 pFSee Figure 1

−55°C 3.2 1 4.6 V/μsSRunity gain† See Figure 1

125°C 4.1 1 4.7

V/μs

VI(PP) = ±10 mV, 25°C 138 132

tr Rise timeVI(PP) = ±10 mV,RL = 10 kΩ, CL = 100 pF −55°C 142 123 nstr Rise time RL 10 kΩ, CL 100 pFSee Figures 1 and 2 125°C 166 158

ns

VI(PP) = ±10 mV, 25°C 138 132

tf Fall timeVI(PP) = ±10 mV,RL = 10 kΩ, CL = 100 pF −55°C 142 123 nstf Fall time RL 10 kΩ, CL 100 pFSee Figure 1 125°C 166 158

ns

VI(PP) = ±10 mV, 25°C 11% 5%

Overshoot factorVI(PP) = ±10 mV,RL = 10 kΩ, CL = 100 pF −55°C 16% 6%Overshoot factor RL 10 kΩ, CL 100 pFSee Figures 1 and 2 125°C 14% 8%

TL031Mf = 10 Hz

25°C61 61

VEquivalent input

TL031MRS = 20 Ω f = 1 kHz

25°C41 41

nV/√HVnEquivalent inputnoise voltage

TL031AM

RS = 20 ΩSee Figure 3 f = 10 Hz

25°C61 61

nV/√Hz

TL031AMf = 1 kHz

25°C41 41

IEquivalent input noise

f 1 kHz 25°C 0 003 0 003 pA/√HInEquivalent input noisecurrent f = 1 kHz 25°C 0.003 0.003 pA/√Hz

VI = 10 mV, 25°C 1 1.1

B1 Unity-gain bandwidthVI = 10 mV,RL = 10 kΩ, CL = 25 pF −55°C 1 1.1 MHzB1 Unity gain bandwidth RL 10 kΩ, CL 25 pFSee Figure 4 125°C 0.9 0.9

MHz

VI = 10 mV, 25°C 61° 65°

φm Phase margin at unity gainVI = 10 mV,RL = 10 kΩ, CL = 25 pF −55°C 57° 64°φm g y g RL 10 kΩ, CL 25 pFSee Figure 4 125°C 59° 62°

† For VCC± = ±5 V, VI(PP) = ±1 V; for VCC± = ±15 V, VI(PP) = ±5 V

Page 12: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSETOPERATIONAL AMPLIFIERSSLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL032C and TL032AC electrical characteristics at specified free-air temperature

TL032C, TL032AC

PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA

MIN TYP MAX MIN TYP MAX

UNIT

TL032C25°C 0.69 3.5 0.57 1.5

V Input offset voltageVO = 0,V 0

TL032CFull range† 4.5 2.5

mVVIO Input offset voltage VIC = 0,RS = 50 Ω TL032AC

25°C 0.53 2.8 0.39 0.8mV

RS = 50 Ω TL032ACFull range† 3.8 1.8

�VTemperature

ffi i t f i tVO = 0,V 0

TL032C 25°C to70°C

11.5 10.8

V/°C�VIO coefficient of inputoffset voltage

VIC = 0,RS = 50 Ω TL032AC 25°C to

70°C11.5 10.8 25

μV/°C

Input offset voltagelong-term drift‡

VO = 0, VIC = 0,RS = 50 Ω

25°C 0.04 0.04 μV/mo

I Input offset currentVO = 0, VIC = 0 25°C 1 100 1 100

pAIIO Input offset currentVO = 0,See Figure 5

VIC = 0

70°C 9 200 12 200pA

I Input bias currentVO = 0, VIC = 0 25°C 2 200 2 200

pAIIB Input bias currentVO = 0, See Figure 5

VIC = 0

70°C 50 400 80 400pA

VCommon-mode input

25°C−1.5to 4

−3.4to 5.4

−11.5to 14

−13.4to 15.4

VVICRCommon mode inputvoltage range

Full range† −1.5to 4

−11.5to 14

V

Maximum positive 25°C 3 4.3 13 14

VOM+

Maximum positivepeak output voltage RL = 10 kΩ 0°C 3 4.2 13 14 VVOM+ peak output voltageswing

RL 10 kΩ70°C 3 4.3 13 14

V

Maximum negative 25°C −3 −4.2 −12.5 −13.9

VOM−

Maximum negativepeak output voltage RL = 10 kΩ 0°C −3 −4.1 −12.5 −13.9 VVOM− peak output voltageswing

RL 10 kΩ70°C −3 −4.2 −12.5 −14

V

Large-signal25°C 4 12 5 14.3

AVD

Large-signaldifferential voltage RL = 10 kΩ 0°C 3 11.1 4 13.5 V/mVAVD differential voltageamplification§

RL 10 kΩ70°C 4 13.3 5 15.2

V/mV

ri Input resistance 25°C 1012 1012 Ω

ci Input capacitance 25°C 5 14 pF

C d V V i25°C 70 87 75 94

CMRRCommon-moderejection ratio

VIC = VICRmin,VO = 0 RS = 50 Ω 0°C 70 87 75 94 dBCMRR rejection ratio VO = 0, RS = 50 Ω

70°C 70 87 75 94

dB

Supply-voltageV ±5 V t ±15 V

25°C 75 96 75 96

kSVR

Supply-voltagerejection ratio

VCC± = ±5 V to ±15 V,VO = 0 RS = 50 Ω 0°C 75 96 75 96 dBSVR rejection ratio

(ΔVCC±/ΔVIO)VO = 0, RS = 50 Ω

70°C 75 96 75 96† Full range is 0°C to 70°C.‡ Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated to

TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.§ At VCC± = ±5 V, VO = 2.3 V; at VCC± = ±15 V, VO = ±10 V

Page 13: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSET

OPERATIONAL AMPLIFIERSSLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL032C and TL032AC electrical characteristics at specified free-air temperature (continued)TL032C, TL032AC

PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TAMIN TYP MAX MIN TYP MAX

UNIT

T t l di i ti25°C 3.8 5 13 17

PDTotal power dissipation(two amplifiers) VO = 0, No load 0°C 3.7 5 12.7 17 mWPD (two amplifiers) VO 0, No load

70°C 3.8 5 12.6 17

mW

ISupply current

V 0 No load0°C 368 500 422 560

AICCSupply current(two amplifiers) VO = 0, No load

70°C 378 500 420 560μA

VO1/VO2 Crosstalk attenuation AVD = 100 dB 25°C 120 120 dB

TL032C and TL032AC operating characteristics at specified free-air temperature

TL032C, TL032AC

PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITA

MIN TYP MAX MIN TYP MAX

R 10 kΩ C 100 F25°C 1.2 1.5 2.9

SR+ Positive slew rate at unitygain†

RL = 10 kΩ, CL = 100 pFSee Figure 1

0°C 1.8 1 2.6 V/μsSR+gain† See Figure 1

70°C 2.2 1.5 3.2

V/μs

R 10 kΩ C 100 F25°C 3.9 1.5 5.1

SR− Negative slew rate at unitygain†

RL = 10 kΩ, CL = 100 pFSee Figure 1

0°C 3.7 1.5 5 V/μsSRgain† See Figure 1

70°C 4 1.5 5

V/μs

VI(PP) = ±10 V, 25°C 138 132

tr Rise timeVI(PP) = ±10 V,RL = 10 kΩ, CL = 100 pF 0°C 134 127 nstr Rise time RL 10 kΩ, CL 100 pFSee Figures 1 and 2 70°C 150 142

ns

VI(PP) = ±10 V, 25°C 138 132

tf Fall timeVI(PP) = ±10 V,RL = 10 kΩ, CL = 100 pF 0°C 134 127 nstf Fall time RL 10 kΩ, CL 100 pFSee Figures 1 and 2 70°C 150 142

ns

VI(PP) = ±10 V, 25°C 11% 5%

Overshoot factorVI(PP) = ±10 V,RL = 10 kΩ, CL = 100 pF 0°C 10% 4%Overshoot factor RL 10 kΩ, CL 100 pFSee Figures 1 and 2 70°C 12% 6%

TL032Cf = 10 Hz

25°C49 49

V Equivalent inputTL032C

RS = 20 Ω f = 1 kHz25°C

41 41nV/√HzVn

Equivalent inputnoise voltage

TL032AC

RS = 20 ΩSee Figure 3 f = 10 Hz

25°C49 49

nV/√Hzg

TL032ACf = 1 kHz

25°C41 41 60

In Equivalent input noise current f = 1 kHz 25°C 0.003 0.003 pA/√Hz

VI = 10 mV, 25°C 1 1.1

B1 Unity-gain bandwidthVI = 10 mV,RL = 10 kΩ, CL = 25 pF 0°C 1 1.1 MHzB1 Unity gain bandwidth RL 10 kΩ, CL 25 pFSee Figure 4 70°C 1 1

MHz

VI = 10 mV, 25°C 61° 65°

φm Phase margin at unity gainVI = 10 mV,RL = 10 kΩ, CL = 25 pF 0°C 61° 65°φm g y g RL 10 kΩ, CL 25 pFSee Figure 4 70°C 60° 64°

† For VCC± = ±5 V, VI(PP) = ±1 V; for VCC± = ±15 V, VI(PP) = ±5 V

Page 14: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSETOPERATIONAL AMPLIFIERSSLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL032I and TL032AI electrical characteristics at specified free-air temperatureTL032I, TL032AI

PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA

MIN TYP MAX MIN TYP MAXUNIT

TL032I25°C 0.69 3.5 0.57 1.5

V Input offset voltageVO = 0,V 0

TL032IFull range† 5.3 3.3

mVVIO Input offset voltage VIC = 0,RS = 50 Ω TL032AI

25°C 0.53 2.8 0.39 0.8mV

RS = 50 Ω TL032AIFull range† 4.6 2.6

�VTemperature

ffi i t f i tVO = 0,V 0

TL032I25°C to

85°C 11.4 10.8

V/°C�VIO coefficient of inputoffset voltage

VIC = 0,RS = 50 Ω TL032AI

25°C to85°C 11.4 10.8 25

μV/°C

Input offset voltagelong-term drift‡

VO = 0,VIC = 0,RS = 50 Ω

25°C 0.04 0.04 μV/mo

I Input offset currentVO = 0, VIC = 0 25°C 1 100 1 100 pA

IIO Input offset currentVO = 0,See Figure 5

VIC = 0

85°C 0.02 0.45 0.02 0.45 nA

I Input bias currentVO = 0, VIC = 0 25°C 2 200 2 200 pA

IIB Input bias currentVO = 0,See Figure 5

VIC = 0

85°C 0.2 0.9 0.3 0.9 nA

VCommon-mode input

25°C−1.5to 4

−3.4to 5.4

−11.5to 14

−13.4to 15.4

VVICRCommon mode inputvoltage range

Full range† −1.5to 4

−11.5to 14

V

Maximum positive 25°C 3 4.3 13 14

VOM+

Maximum positivepeak output voltage RL = 10 kΩ −40°C 3 4.2 13 14 VVOM+ peak output voltageswing

RL 10 kΩ85°C 3 4.4 13 14

V

Maximum negative 25°C −3 −4.2 −12.5 −13.9

VOM−

Maximum negativepeak output voltage RL = 10 kΩ −40°C −3 −4.1 −12.5 −13.8 VVOM− peak output voltageswing

RL 10 kΩ85°C −3 −4.2 −12.5 −14

V

A Large-signal differential R 10 kΩ−40°C 3 8.4 4 11.6

V/mVAVDLarge-signal differentialvoltage amplification§ RL = 10 kΩ

85°C 4 13.5 5 15.3V/mV

ri Input resistance 25°C 1012 1012 Ω

ci Input capacitance 25°C 5 4 pF

C d V V i25°C 70 87 75 94

CMRRCommon-moderejection ratio

VIC = VICRmin,VO = 0 RS = 50 Ω −40°C 70 87 75 94 dBCMRR rejection ratio VO = 0, RS = 50 Ω

85°C 70 87 75 94

dB

Supply-voltageV ±5 V t ±15 V

25°C 75 96 75 96

kSVR

Supply-voltage rejection ratio

VCC± = ±5 V to ±15 V,VO = 0 RS = 50 Ω −40°C 75 96 75 96 dBSVR rejection ratio

(ΔVCC±/ΔVIO)VO = 0, RS = 50 Ω

85°C 75 96 75 96† Full range is −40°C to 85°C.‡ Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated to

TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.§ At VCC± = ±5 V, VO = 2.3 V; at VCC± = ±15 V, VO = ±10 V

Page 15: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSET

OPERATIONAL AMPLIFIERSSLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL032I and TL032AI electrical characteristics at specified free-air temperature (continued)TL032I, TL032AI

PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA

MIN TYP MAX MIN TYP MAXUNIT

Total power 25°C 3.8 5 13 17

PD

Total powerdissipation VO = 0, No load −40°C 2.9 5 10.9 17 mWPD dissipation (two amplifiers)

VO 0, No load

85°C 3.7 5 12.4 17

mW

S l t25°C 384 500 434 560

ICCSupply current (two amplifiers) VO = 0, No load −40°C 288 500 362 560 μAICC (two amplifiers) VO 0, No load

85°C 372 500 414 560

μA

VO1/VO2Crosstalkattenuation

AVD = 100 dB 25°C 120 120 dB

TL032I and TL032AI operating characteristics at specified free-air temperatureTL032I, TL032AI

PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA

MIN TYP MAX MIN TYP MAXUNIT

25°C 2 1.5 2.9

SR+ Positive slew rate at unitygain† RL = 10 kΩ, CL = 100 pF −40°C 1.6 1 2.1 V/μsSR+gain† RL 10 kΩ, CL 100 pF

85°C 2.3 1.5 3.3

V/μs

25°C 3.9 1.5 5.1

SR− Negative slew rate at unitygain† RL = 10 kΩ, CL = 100 pF −40°C 3.3 1.5 4.8 V/μsSRgain† RL 10 kΩ, CL 100 pF

85°C 4.1 1.5 4.9

V/μs

VI(PP) = ±10 V, 25°C 138 132

tr Rise timeVI(PP) = ±10 V,RL = 10 kΩ, CL = 100 pF −40°C 132 123 nstr Rise time RL 10 kΩ, CL 100 pFSee Figures 1 and 2 85°C 154 146

ns

VI(PP) = ±10 V, 25°C 138 132

tf Fall timeVI(PP) = ±10 V,RL = 10 kΩ, CL = 100 pF −40°C 132 123 nstf Fall time RL 10 kΩ, CL 100 pFSee Figure 1 85°C 154 146

ns

VI(PP) = ±10 V, 25°C 11% 5%

Overshoot factorVI(PP) = ±10 V,RL = 10 kΩ, CL = 100 pF −40°C 12% 5%Overshoot factor RL 10 kΩ, CL 100 pFSee Figures 1 and 2 85°C 13% 7%

TL032If = 10 Hz

25°C49 49

V Equivalent inputTL032I

RS = 20 Ω f = 1 kHz25°C

41 41nV/√HzVn

Equivalent inputnoise voltage

TL032AI

RS = 20 ΩSee Figure 3 f = 10 Hz

25°C49 49

nV/√Hzg

TL032AIf = 1 kHz

25°C41 41 60

InEquivalent input noise current

f = 1 kHz 25°C 0.003 0.003 pA/√Hz

VI = 10 mV, 25°C 1 1.1

B1 Unity-gain bandwidthVI = 10 mV,RL = 10 kΩ, CL = 25 pF −40°C 1 1.1 MHzB1 Unity gain bandwidth RL 10 kΩ, CL 25 pFSee Figure 4 85°C 0.9 1

MHz

VI = 10 mV, 25°C 61° 65°

φm Phase margin at unity gainVI = 10 mV,RL = 10 kΩ, CL = 25 pF −40°C 61° 65°φm g y g RL 10 kΩ, CL 25 pFSee Figure 4 85°C 60° 64°

† For VCC± = ±5 V, VI(PP) = ±1 V; for VCC± = ±15 V, VI(PP) = ±5 V

Page 16: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSETOPERATIONAL AMPLIFIERSSLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL032M and TL032AM electrical characteristics at specified free-air temperatureTL032M, TL032AM

PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TAMIN TYP MAX MIN TYP MAX

UNIT

TL032M25°C 0.69 3.5 0.57 1.5

V Input offset voltageVO = 0,V 0

TL032MFull range† 6.5 4.5

mVVIO Input offset voltage VIC = 0,RS = 50 Ω TL032AM

25°C 0.53 2.8 0.39 0.8mV

RS = 50 Ω TL032AMFull range† 5.8 3.8

Temperature coefficientVO = 0,V 0

TL032M25°C to125°C 9.7 9.7

V/°C�VIO

Temperature coefficientof input offset voltage

VIC = 0,RS = 50 Ω TL032AM

25°C to125°C 9.7 9.7

μV/°C

Input offset voltage long-term drift‡

VO = 0,VIC = 0,RS = 50 Ω

25°C 0.04 0.04 μV/mo

I Input offset currentVO = 0, VIC = 0 25°C 1 100 1 100 pA

IIO Input offset currentVO = 0,See Figure 5

VIC = 0

125°C 0.2 10 0.2 10 nA

I Input bias currentVO = 0, VIC = 0 25°C 2 200 2 200 pA

IIB Input bias currentVO = 0,See Figure 5

VIC = 0

125°C 7 20 8 20 nA

VCommon-mode input

25°C−1.5to 4

−3.4to 5.4

−11.5to 14

−13.4to 15.4

VVICRCommon mode inputvoltage range

Full range† −1.5to 4

−11.5to 14

V

M i iti k 25°C 3 4.3 13 14

VOM+Maximum positive peakoutput voltage swing RL = 10 kΩ −55°C 3 4.1 13 14 VVOM+ output voltage swing RL 10 kΩ

125°C 3 4.4 13 14

V

M i ti k 25°C −3 −4.2 −12.5 −13.9

VOM−Maximum negative peakoutput voltage swing RL = 10 kΩ −55°C −3 −4 −12.5 −13.8 VVOM− output voltage swing RL 10 kΩ

125°C −3 −4.3 −12.5 −14

V

25°C 4 12 5 14.3

AVDLarge-signal differentialvoltage amplification§ RL = 10 kΩ −55°C 3 7.1 4 10.4 V/mVAVD voltage amplification§ RL 10 kΩ

125°C 3 12.9 4 15

V/mV

ri Input resistance 25°C 1012 1012 Ω

ci Input capacitance 25°C 5 4 pF

C d j ti V V i 25°C 70 87 75 94

CMRRCommon-mode rejectionratio

VIC = VICRmin,VO = 0 RS = 50 Ω −55°C 70 87 70 94 dBCMRR ratio VO = 0, RS = 50 Ω

125°C 70 87 70 94

dB

Supply-voltageV ±5 V t ±15 V

25°C 75 96 75 96

kSVR

Supply-voltage rejection ratio

VCC± = ±5 V to ±15 V,VO = 0 RS = 50 Ω −55°C 75 95 75 95 dBSVR rejection ratio

(ΔVCC±/ΔVIO)VO = 0, RS = 50 Ω

125°C 75 96 75 96† Full range is −55°C to 125°C.‡ Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated to

TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.§ At VCC± = ±5 V, VO = 2.3 V; at VCC± = ±15 V, VO = ±10 V

Page 17: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSET

OPERATIONAL AMPLIFIERSSLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

17POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL032M and TL032AM electrical characteristics at specified free-air temperature (continued)TL032M, TL032AM

PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TAMIN TYP MAX MIN TYP MAX

UNIT

Total power dissipation 25°C 3.8 5 13 17

PD

Total power dissipation(two amplifiers) VO = 0, No load −55°C 2.3 5 9.4 17 mWPD (two amplifiers)VO = 0,

VO 0, No load

125°C 3.6 5 11.8 17

mW

S l t25°C 384 500 434 560

ICCSupply current (two amplifiers) VO = 0, No load −55°C 228 500 312 560 μAICC (two amplifiers) VO 0, No load

125°C 356 500 394 560

μA

VO1/VO2 Crosstalk attenuation AVD = 100 dB 25°C 120 120 dB

TL032M and TL032AM operating characteristics at specified free-air temperatureTL032M, TL032AM

PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA

MIN TYP MAX MIN TYP MAXUNIT

R 10 kΩ C 100 F25°C 2 1.5 2.9

SR+ Positive slew rate at unitygain†

RL = 10 kΩ, CL = 100 pFSee and Figure 1

−55°C 1.4 1 1.9 V/μsSR+gain† See and Figure 1

125°C 2.4 1 3.5

V/μs

R 10 kΩ C 100 F25°C 3.9 1.5 5.1

SR− Negative slew rate at unitygain†

RL = 10 kΩ, CL = 100 pFSee and Figure 1

−55°C 3.2 1 4.6 V/μsSRgain† See and Figure 1

125°C 4.1 1 4.7

V/μs

VI(PP) = ±10 V, 25°C 138 132

tr Rise timeVI(PP) = ±10 V,RL = 10 kΩ, CL = 100 pF −55°C 142 123 nstr Rise time RL 10 kΩ, CL 100 pFSee Figures 1 and 2 125°C 166 58

ns

VI(PP) = ±10 V, 25°C 138 132

tf Fall timeVI(PP) = ±10 V,RL = 10 kΩ, CL = 100 pF −55°C 142 123 nstf Fall time RL 10 kΩ, CL 100 pFSee Figure 1 125°C 166 158

ns

VI(PP) = ±10 V, 25°C 11% 5%

Overshoot factorVI(PP) = ±10 V,RL = 10 kΩ, CL = 100 pF −55°C 16% 6%Overshoot factor RL 10 kΩ, CL 100 pFSee Figures 1 and 2 125°C 14% 8%

TL032Mf = 10 Hz

25°C49 49

VEquivalent input noise

TL032MRS = 20 Ω f = 1 kHz

25°C41 41

nV/√HzVn input noise voltage TL032AM

RS = 20 ΩSee Figure 3 f = 10 Hz

25°C49 49

nV/√Hzvoltage TL032AM

f = 1 kHz25°C

41 41

InEquivalent input noise current

f = 1 kHz 25°C 0.003 0.003 pA/√Hz

VI = 10 mV, 25°C 1 1.1

B1 Unity-gain bandwidthVI = 10 mV,RL = 10 kΩ, CL = 25 pF −55°C 1 1.1 MHzB1 Unity gain bandwidth RL 10 kΩ, CL 25 pFSee Figure 4 125°C 0.9 0.9

MHz

VI = 10 mV, 25°C 61° 65°

φm Phase margin at unity gainVI = 10 mV,RL = 10 kΩ, CL = 25 pF −55°C 57° 64°φm g y g RL 10 kΩ, CL 25 pFSee Figure 4 125°C 59° 62°

† For VCC± = ±5 V, VI(PP) = ±1 V; for VCC± = ±15 V, VI(PP) = ±5 V

Page 18: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSETOPERATIONAL AMPLIFIERSSLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL034C and TL034AC electrical characteristics at specified free-air temperatureTL034C, TL034AC

PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA

MIN TYP MAX MIN TYP MAXUNIT

TL034C25°C 0.91 6 0.79 4

V Input offset voltageVO = 0,V 0

TL034CFull range† 8.2 6.2

mVVIO Input offset voltage VIC = 0,RS = 50 Ω TL034AC

25°C 0.7 3.5 0.58 1.5mV

RS = 50 Ω TL034ACFull range† 5.7 3.7

�Temperature coefficient

VO = 0,V 0

TL034C 25°C to70°C

11.6 12

V/°C�VIO

Temperature coefficientof input offset voltage

VIC = 0,RS = 50 Ω TL034AC 25°C to

70°C11.6 12 25

μV/°C

Input offset voltage long-term drift‡

VO = 0,VIC = 0,RS = 50 Ω

25°C 0.04 0.04 μV/mo

I Input offset currentVO = 0, VIC = 0 25°C 1 100 1 100

pAIIO Input offset currentVO = 0, VIC = 0See Figure 5 70°C 9 200 12 200

pA

I Input bias currentVO = 0, VIC = 0 25°C 2 200 2 200

pAIIB Input bias currentVO = 0, VIC = 0See Figure 5 70°C 50 400 80 400

pA

VCommon-mode input

25°C−1.5to 4

−3.4to 5.4

−11.5to 14

−13.4to 15.4

VVICRCommon mode inputvoltage range

Full range† −1.5to 4

−11.5to 14

V

M i iti k25°C 3 4.3 13 14

VOM+Maximum positive peakoutput voltage swing RL = 10 kΩ 0°C 3 4.2 13 14 VVOM+ output voltage swing RL 10 kΩ

70°C 3 4.3 13 14

V

M i ti k25°C −3 −4.2 −12.5 −13.9

VOM−Maximum negative peakoutput voltage swing RL = 10 kΩ 0°C −3 −4.1 −12.5 −13.9 VVOM− output voltage swing RL 10 kΩ

70°C −3 −4.2 −12.5 −14

V

25°C 4 12 5 14.3

AVDLarge-signal differentialvoltage amplification§ RL = 10 kΩ 0°C 3 11.1 4 13.5 V/mVAVD voltage amplification§ RL 10 kΩ

70°C 4 13.3 5 15.2

V/mV

ri Input resistance 25°C 1012 1012 Ω

ci Input capacitance 25°C 5 14 pF

C dVIC = VICRmin, 25°C 70 87 75 94

CMRRCommon-moderejection ratio

VIC = VICRmin,VO = 0, 0°C 70 87 75 94 dBCMRR rejection ratioVO 0,RS = 50 Ω 70°C 70 87 75 94

dB

Supply-voltage 25°C 75 96 75 96

kSVR

Supply-voltage rejection ratio VO = 0, RS = 50 Ω 0°C 75 96 75 96 dBSVR rejection ratio(ΔVCC±/ΔVIO)

O , S

70°C 75 96 75 96† Full range is 0°C to 70°C.‡ Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated to

TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.§ At VCC± = ±5 V, VO = ±2.3 V; at VCC± = ±15 V, VO = ±10 V

Page 19: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSET

OPERATIONAL AMPLIFIERSSLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

19POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL034C and TL034AC electrical characteristics at specified free-air temperature (continued)TL034C, TL034AC

PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA

MIN TYP MAX MIN TYP MAXUNIT

T t l di i ti25°C 7.7 10 26 34

PDTotal power dissipation(two amplifiers) VO = 0, No load 0°C 7.4 10 25.3 34 mWPD (two amplifiers) VO 0, No load

70°C 7.6 10 25.2 34

mW

S l t (f25°C 0.77 1 0.87 1.12

ICCSupply current (fouramplifiers) VO = 0, No load 0°C 0.74 1 0.85 1.12 mAICC amplifiers) VO 0, No load

70°C 0.76 1 0.84 1.12

mA

VO1/VO2 Crosstalk attenuation AVD = 100 25°C 120 120 dB

TL034C and TL034AC operating characteristics at specified free-air temperatureTL034C, TL034AC

PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA

MIN TYP MAX MIN TYP MAXUNIT

R 10 kΩ C 100 F25°C 2 1.5 2.9

SR+ Positive slew rate at unitygain†

RL = 10 kΩ, CL = 100 pFSee Figure 1

0°C 1.8 1 2.6 V/μsSR+gain† See Figure 1

70°C 2.2 1.5 3.2

V/μs

R 10 kΩ C 100 F25°C 3.9 1.5 5.1

SR− Negative slew rate at unitygain†

RL = 10 kΩ, CL = 100 pFSee Figure 1

0°C 3.7 1.5 5 V/μsSRgain† See Figure 1

70°C 4 1.5 5

V/μs

VI(PP) = ±10 V, 25°C 138 132

tr Rise timeVI(PP) = ±10 V,RL = 10 kΩ, CL = 100 pF 0°C 134 127 nstr Rise time RL 10 kΩ, CL 100 pFSee Figures 1 and 2 70°C 150 142

ns

VI(PP) = ±10 V, 25°C 138 132

tf Fall timeVI(PP) = ±10 V,RL = 10 kΩ, CL = 100 pF 0°C 134 127 nstf Fall time RL 10 kΩ, CL 100 pFSee Figure 1 70°C 150 142

ns

VI(PP) = ±10 V, 25°C 11% 5%

Overshoot factorVI(PP) = ±10 V,RL = 10 kΩ, CL = 100 pF 0°C 10% 4%Overshoot factor RL 10 kΩ, CL 100 pFSee Figures 1 and 2 70°C 12% 6%

TL034Cf = 10 Hz

25°C83 83

V Equivalent inputTL034C

RS = 20 Ω f = 1 kHz25°C

43 43nV/√HzVn

Equivalent inputnoise voltage

TL034AC

RS = 20 ΩSee Figure 3 f = 10 Hz

25°C83 83

nV/√Hzg

TL034ACf = 1 kHz

25°C43 43 60

In Equivalent input noise current f = 1 kHz 25°C 0.003 0.003 pA/√Hz

VI = 10 mV 25°C 1 1.1

B1 Unity-gain bandwidthVI = 10 mVRL = 10 kΩ, CL = 25 pF 0°C 1 1.1 MHzB1 Unity gain bandwidth RL 10 kΩ, CL 25 pF See Figure 4 70°C 1 1

MHz

VI = 10 mV, 25°C 61° 65°

φm Phase margin at unity gainVI = 10 mV,RL = 10 kΩ, CL = 25 pF 0°C 61° 65°φm g y g RL 10 kΩ, CL 25 pF See Figure 4 70°C 60° 64°

† For VCC± = ±5 V, VI(PP) = ±1 V; for VCC± = ±15 V, VI(PP) = ±5 V

Page 20: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSETOPERATIONAL AMPLIFIERSSLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL034I and TL034AI electrical characteristics at specified free-air temperatureTL034I, TL034AI

PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA

MIN TYP MAX MIN TYP MAXUNIT

TL034I25°C 0.91 3.6 0.79 4

V Input offset voltageVO = 0,V 0

TL034IFull range† 9.3 7.3

mVVIO Input offset voltage VIC = 0,RS = 50 Ω TL034AI

25°C 0.7 3.5 0.58 1.5mV

RS = 50 Ω TL034AIFull range† 6.8 4.8

�Temperature coefficient

VO = 0, VIC0

TL034I25°C to

85°C 11.5 11.6

V/°C�VIO

Temperature coefficientof input offset voltage

= 0,RS = 50 Ω TL034AI

25°C to85°C 11.5 11.6 25

μV/°C

Input offset voltagelong-term drift‡

VO = 0, VIC = 0,RS = 50 Ω

25°C 0.04 0.04 μV/mo

I Input offset currentVO = 0, VIC = 0 25°C 1 100 1 100 pA

IIO Input offset currentVO = 0, VIC = 0See Figure 5 85°C 0.02 0.45 0.02 0.45 nA

I Input bias currentVO = 0, VIC = 0 25°C 2 200 2 200 pA

IIB Input bias currentVO = 0, VIC = 0See Figure 5 85°C 0.2 0.9 0.3 0.9 nA

VCommon-mode input

25°C−1.5to 4

−3.4to 5.4

−11.5to 14

−13.4to 15.4

VVICRCommon mode inputvoltage range

Full range† −1.5to 4

−11.5to 14

V

M i iti k25°C 3 4.3 13 14

VOM+Maximum positive peakoutput voltage swing RL = 10 kΩ −40°C 3 4.1 13 14 VVOM+ output voltage swing RL 10 kΩ

85°C 3 4.4 13 14

V

Maximum negative 25°C −3 −4.2 −12.5 −13.9

VOM−

Maximum negativepeak RL = 10 kΩ −40°C −3 −4.1 −12.5 −13.8 VVOM− peakoutput voltage swing

RL 10 kΩ85°C −3 −4.2 −12.5 −14

V

A Large-signal differential R 10 kΩ−40°C 4 12 5 14.3

V/mVAVDLarge-signal differentialvoltage amplification§ RL = 10 kΩ

85°C 3 8.4 4 11.6V/mV

ri Input resistance 25°C 1012 1012 Ω

ci Input capacitance 25°C 5 4 pF

C dVIC = VICRmin, 25°C 70 87 75 94

CMRRCommon-moderejection ratio

VIC = VICRmin,VO = 0, −40°C 70 87 75 94 dBCMRR rejection ratioVO 0,RS = 50 Ω 85°C 70 87 75 94

dB

Supply-voltage 25°C 75 96 75 96

kSVR

Supply-voltage rejection ratio VO = 0, RS = 50 Ω −40°C 75 96 75 96 dBSVR rejection ratio(ΔVCC±/ ΔVIO)

O , S

85°C 75 96 75 96† Full range is −40°C to 85°C.‡ Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated to

TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.§ At VCC± = ±5 V, VO = ±2.3 V; at VCC± = ±15 V, VO = ±10 V

Page 21: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSET

OPERATIONAL AMPLIFIERSSLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

21POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL034I and TL034AI electrical characteristics at specified free-air temperature (continued)TL034I, TL034AI

PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA

MIN TYP MAX MIN TYP MAXUNIT

T t l di i ti25°C 7.7 10 26 34

PDTotal power dissipation(four amplifiers) VO = 0, No load −40°C 5.8 10 21.7 34 mWPD (four amplifiers) VO 0, No load

85°C 7.4 10 24.8 34

mW

S l t25°C 0.77 1 0.87 1.12

ICCSupply current (four amplifiers) VO = 0, No load −40°C 0.58 1 0.72 1.12 mAICC (four amplifiers) VO 0, No load

85°C 0.74 1 0.83 1.12

mA

VO1/VO2 Crosstalk attenuation AVD = 100 25°C 120 120 dB

TL034I and TL034AI operating characteristicsTL034I, TL034AI

PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA

MIN TYP MAX MIN TYP MAXUNIT

R 10 kΩ C 100 F25°C 2 1.5 2.9

SR+ Positive slew rate at unitygain†

RL = 10 kΩ, CL = 100 pFSee Figure 1

−40°C 1.6 1 2.1 V/μsSR+gain† See Figure 1

85°C 2.3 1.5 3.3

V/μs

R 10 kΩ C 100 F25°C 3.9 1.5 5.1

SR− Negative slew rate at unitygain†

RL = 10 kΩ, CL = 100 pFSee Figure 1

−40°C 3.3 1.5 4.8 V/μsSRgain† See Figure 1

85°C 4.1 1.5 4.9

V/μs

VI(PP) = ±10 V, 25°C 138 132

tr Rise timeVI(PP) = ±10 V,RL = 10 kΩ, CL = 100 pF −40°C 132 123 nstr Rise time RL 10 kΩ, CL 100 pFSee Figures 1 and 2 85°C 154 146

ns

VI(PP) = ±10 V, 25°C 138 132

tf Fall timeVI(PP) = ±10 V,RL = 10 kΩ, CL = 100 pF −40°C 132 123 nstf Fall time RL 10 kΩ, CL 100 pFSee Figures 1 and 2 85°C 154 146

ns

VI(PP) = ±10 V, 25°C 11% 5%

Overshoot factorVI(PP) = ±10 V,RL = 10 kΩ, CL = 100 pF −40°C 12% 5%Overshoot factor RL 10 kΩ, CL 100 pFSee Figures 1 and 2 85°C 13% 7%

TL034If = 10 Hz

25°C83 83

V Equivalent inputTL034I

RS = 20 Ω f = 1 kHz25°C

43 43nV/√HzVn

Equivalent inputnoise voltage

TL034AI

RS = 20 ΩSee Figure 3 f = 10 Hz

25°C83 83

nV/√Hzg

TL034AIf = 1 kHz

25°C43 43 60

InEquivalent input noisecurrent

f = 1 kHz 25°C 0.003 0.003 pA/√Hz

VI = 10 mV, 25°C 1 1.1

B1 Unity-gain bandwidthVI = 10 mV,RL = 10 kΩ, CL = 25 pF −40°C 1 1.1 MHzB1 Unity gain bandwidth RL 10 kΩ, CL 25 pFSee Figure 4 85°C 0.9 1

MHz

VI = 10 mV, 25°C 61° 65°

φm Phase margin at unity gainVI = 10 mV,RL = 10 kΩ, CL = 25 pF −40°C 61° 65°φm g y g RL 10 kΩ, CL 25 pFSee Figure 4 85°C 60° 64°

† For VCC± = ±5 V, VI(PP) = ±1 V; for VCC± = ±15 V, VI(PP) = ±5 V

Page 22: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSETOPERATIONAL AMPLIFIERSSLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL034M and TL034AM electrical characteristics at specified free-air temperatureTL034M, TL034AM

PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA

MIN TYP MAX MIN TYP MAXUNIT

TL034M25°C 0.91 3.6 0.78 4

V Input offset voltageVO = 0,V 0

TL034MFull range† 11 9

mVVIO Input offset voltage VIC = 0,RS = 50 Ω TL034AM

25°C 0.7 3.5 0.58 1.5mV

RS = 50 Ω TL034AMFull range† 8.5 6.5

Temperature coefficient ofVO = 0,V 0

TL034M25°C to125°C 10.6 10.9

V/°C�VIO

Temperature coefficient ofinput offset voltage

VIC = 0,RS = 50 Ω TL034AM

25°C to125°C 10.6 10.9

μV/°C

Input offset voltage long-term drift‡

VO = 0, VIC = 0,RS = 50 Ω

25°C 0.04 0.04 μV/mo

I Input offset currentVO = 0, VIC = 0 25°C 1 100 1 100 pA

IIO Input offset currentVO = 0, VIC = 0See Figure 5 125°C 0.2 10 0.2 10 nA

I Input bias currentVO = 0, VIC = 0 25°C 2 200 2 200 pA

IIB Input bias currentVO = 0, VIC = 0See Figure 5 125°C 7 20 8 20 nA

VCommon-mode input

25°C−1.5to 4

−3.4to 5.4

−11.5to 14

−13.4to 15.4

VVICRCommon mode inputvoltage range

Full range† −1.5to 4

−11.5to 14

V

M i iti k 25°C 3 4.3 13 14

VOM+Maximum positive peakoutput voltage swing RL = 10 kΩ −55°C 3 4.1 13 14 VVOM+ output voltage swing RL 10 kΩ

125°C 3 4.4 13 14

V

M i ti k 25°C −3 −4.2 −12.5 −13.9

VOM−Maximum negative peakoutput voltage swing RL = 10 kΩ −55°C −3 −4 −12.5 −13.8 VVOM− output voltage swing RL 10 kΩ

125°C −3 −4.3 −12.5 −14

V

25°C 4 12 5 14.3

AVDLarge-signal differentialvoltage amplification§ RL = 10 kΩ −55°C 3 7.1 4 10.4 V/mVAVD voltage amplification§ RL 10 kΩ

125°C 3 12.9 4 15

V/mV

ri Input resistance 25°C 1012 1012 Ω

ci Input capacitance 25°C 5 4 pF

C d V V i 25°C 70 87 75 94

CMRRCommon-moderejection ratio

VIC = VICRmin,VO = 0 RS = 50 Ω −55°C 70 87 70 94 dBCMRR rejection ratio VO = 0, RS = 50 Ω

125°C 70 87 70 94

dB

Supply-voltage 25°C 75 96 75 96

kSVR

Supply-voltage rejection ratio VO = 0, RS = 50 Ω −55°C 75 95 75 95 dBSVR rejection ratio(ΔVCC±/ΔVIO)

O , S

125°C 75 96 75 96† Full range is −55°C to 125°C.‡ Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated to

TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.§ At VCC± = ±5 V, VO = ±2.3 V; at VCC± = ±15 V, VO = ±10 V

Page 23: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSET

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23POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL034M and TL034AM electrical characteristics at specified free-air temperature (continued)TL034M, TL034AM

PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA

MIN TYP MAX MIN TYP MAXUNIT

T t l di i ti 25°C 7.7 10 26 34

PDTotal power dissipation(two amplifiers) VO = 0, No load −55°C 4.6 12 18.7 45 mWPD (two amplifiers) VO 0, No load

125°C 7.1 12 23.6 45

mW

S l t 25°C 0.77 1 0.87 1.12

ICCSupply current (two amplifiers) VO = 0, No load −55°C 0.46 1.2 0.62 1.5 mAICC (two amplifiers) VO 0, No load

125°C 0.71 1.2 0.79 1.5

mA

VO1/VO2 Crosstalk attenuation AVD = 100 25°C 120 120 dB

TL034M and TL034AM operating characteristics at specified free-air temperatureTL034M, TL034AM

PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA

MIN TYP MAX MIN TYP MAXUNIT

R 10 kΩ C 100 F25°C 2 1.5 2.9

SR+ Positive slew rate at unitygain†

RL = 10 kΩ, CL = 100 pFSee Figure 1

−55°C 1.4 1 1.9 V/μsSR+gain† See Figure 1

125°C 2.4 1 3.5

V/μs

R 10 kΩ C 100 F25°C 3.9 1.5 5.1

SR− Negative slew rate at unitygain†

RL = 10 kΩ, CL = 100 pFSee Figure 1

−55°C 3.2 1 4.6 V/μsSRgain† See Figure 1

125°C 4.1 1 4.7

V/μs

VI(PP) = ±10 V, 25°C 138 132

tr Rise timeVI(PP) = ±10 V,RL = 10 kΩ, CL = 100 pF −55°C 142 123 nstr Rise time RL 10 kΩ, CL 100 pFSee Figures 1 and 2 125°C 166 58

ns

VI(PP) = ±10 V, 25°C 138 132

tf Fall timeVI(PP) = ±10 V,RL = 10 kΩ, CL = 100 pF −55°C 142 123 nstf Fall time RL 10 kΩ, CL 100 pFSee Figure 1 125°C 166 158

ns

VI(PP) = ±10 V, 25°C 11% 5%

Overshoot factorVI(PP) = ±10 V,RL = 10 kΩ, CL = 100 pF −55°C 16% 6%Overshoot factor RL 10 kΩ, CL 100 pFSee Figures 1 and 2 125°C 14% 8%

TL034Mf = 10 Hz

25°C83 83

VEquivalent input

TL034MRS = 20 Ω f = 1 kHz

25°C43 43

nV/√HzVnEquivalent inputnoise voltage

TL034AM

RS = 20 ΩSee Figure 3 f = 10 Hz

25°C83 83

nV/√Hz

TL034AMf = 1 kHz

25°C43 43

InEquivalent input noisecurrent

f = 1 kHz 25°C 0.003 0.003 pA/√Hz

VI = 10 mV, 25°C 1 1.1

B1 Unity-gain bandwidthVI = 10 mV,RL = 10 kΩ, CL = 25 pF −55°C 1 1.1 MHzB1 Unity gain bandwidth RL 10 kΩ, CL 25 pFSee Figure 4 125°C 0.9 0.9

MHz

VI = 10 mV, 25°C 61° 65°

φm Phase margin at unity gainVI = 10 mV,RL = 10 kΩ, CL = 25 pF −55°C 57° 64°φm g y g RL 10 kΩ, CL 25 pFSee Figure 4 125°C 59° 62°

† For VCC± = ±5 V, VI(PP) = ±1 V; for VCC± = ±15 V, VI(PP) = ±5 V

Page 24: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

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24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

Figure 1. Slew-Rate and Overshoot Test Circuit

VI

+

VCC+

VCC−

VO

CL(see Note A)

RL

NOTE A: CL includes fixture capacitance.

Figure 2. Rise Time and Overshoot Waveform

Overshoot

10%

90%

tr

Figure 3. Noise-Voltage Test Circuit

VCC−

VCC+

VO

RS RS

10 kΩ

Figure 4. Unity-Gain Bandwidth andPhase-Margin Test Circuit

(see Note A)CL

VO

VCC−

VCC+

RL

VI

10 kΩ

100 Ω

NOTE A: CL includes fixture capacitance.

+

+

VCC+

VCC−

Picoammeters

Ground Shield

Figure 5. Input-Bias and Offset-Current Test Circuit

Page 25: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSET

OPERATIONAL AMPLIFIERSSLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

25POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

typical values

Typical values presented in this data sheet represent the median (50% point) of device parametric performance.

input bias and offset current

At the picoampere bias current level typical of the TL03x and TL03xA, accurate measurement of the bias currentbecomes difficult. Not only does this measurement require a picoammeter, but test-socket leakages easily canexceed the actual device bias currents. To accurately measure these small currents, Texas Instruments usesa two-step process. The socket leakage is measured using picoammeters with bias voltages applied but withno device in the socket. The device is then inserted into the socket and a second test that measures both thesocket leakage and the device input bias current is performed. The two measurements are then subtractedalgebraically to determine the bias current of the device.

noise

With the increasing emphasis on low noise levels in many of today’s applications, the input noise voltage densityis performed at f = 1 kHz, unless otherwise noted.

Page 26: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSETOPERATIONAL AMPLIFIERSSLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Table of GraphsFIGURE

Distribution of TL03x input offset voltage 6−11

Distribution of TL03x input offset-voltage temperature coefficient 12−14

Input bias current vs Common-mode input voltage 15

Input bias current and input offset current vs Free-air temperature 16

Common-mode input voltage vs Supply voltage 17

Common-mode input voltage vs Free-air temperature 18

Output voltage vs Differential input voltage 19, 20

Maximum peak output voltage vs Supply voltage 21

Maximum peak-to-peak output voltage vs Frequency 22

Maximum peak output voltage vs Output current 23, 24

Maximum peak output voltage vs Free-air temperature 25, 26

Large-signal differential voltage amplification vs Load resistance 27

Large-signal differential voltage amplification and Phase shift vs Frequency 28

Large-signal differential voltage amplification vs Free-air temperature 29

Output impedance vs Frequency 30

Common-mode rejection ratio vs Frequency 31, 32

Common-mode rejection ratio vs Free-air temperature 33

Supply-voltage rejection ratio vs Free-air temperature 34

Short-circuit output current vs Supply voltage 35

Short-circuit output current vs Time 36

Short-circuit output current vs Free-air temperature 37

Equivalent input noise voltage vs Frequency (TL031 and TL031A) 38

Equivalent input noise voltage vs Frequency (TL032 and TL032A) 39

Equivalent input noise voltage vs Frequency (TL034 and TL034A) 40

Supply current vs Supply voltage (TL031 and TL031A) 41

Supply current vs Supply voltage (TL032 and TL032A) 42

Supply current vs Supply voltage (TL034 and TL034A) 43

Supply current vs Free-air temperature (TL031 and TL031A) 44

Supply current vs Free-air temperature (TL032 and TL032A) 45

Supply current vs Free-air temperature (TL034 and TL034A) 46

Slew rate vs Load resistance 47, 48

Slew rate vs Free-air temperature 49, 50

Overshoot factor vs Load capacitance 51

Total harmonic distortion vs Frequency 52

Unity-gain bandwidth vs Supply voltage 53

Unity-gain bandwidth vs Free-air temperature 54

Phase margin vs Supply voltage 55

Phase margin vs Load capacitance 56

Phase margin vs Free-air temperature 57

Voltage-follower small-signal pulse response 58

Voltage-follower large-signal pulse response 59, 60

Page 27: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSET

OPERATIONAL AMPLIFIERSSLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

27POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 6

0

Per

cen

tag

e o

f U

nit

s −

%

VIO − Input Offset Voltage − mV

2

4

6

8

10

12

14

−1.2 −0.6 0 0.6 1.2

DISTRIBUTION OF TL031INPUT OFFSET VOLTAGE

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

1681 Units Tested From 1 Wafer LotÎÎÎÎÎÎÎÎÎÎ

VCC± = ±15 V

ÎÎÎÎÎÎÎÎ

TA = 25°CP Package

Figure 7

0−900

Per

cen

tag

e o

f U

nit

s −

%

VIO − Input Offset Voltage − μV

2

4

6

8

10

12

14

16

−600 0 300 600 900

1433 Units Tested From 1 Wafer LotVCC± = ±15 V

ÎÎÎÎÎÎÎÎÎÎ

P Package

DISTRIBUTION OF TL031AINPUT OFFSET VOLTAGE

TA = 25°C

−300

Figure 8

−1.20

Per

cen

tag

e o

f Am

plif

icat

ion

− %

VIO − Input Offset Voltage − mV

12

−0.6 0 0.6 1.2

3

6

9

DISTRIBUTION OF TL032INPUT OFFSET VOLTAGE

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

1681 Amplifiers Tested From 1 Wafer Lot

ÎÎÎÎÎÎÎÎ

TA = 25°CP Package

VCC± = ±15 V

Figure 9

−9000

Per

cen

tag

e o

f Am

plif

iers

− %

VIO − Input Offset Voltage − μV

900

15

−600 −300 0 300 600

3

6

9

12

DISTRIBUTION OF TL032AINPUT OFFSET VOLTAGE

1321 Amplifiers Tested From 1 Wafer LotVCC± = ±15 VTA = 25°C P Package

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TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSETOPERATIONAL AMPLIFIERSSLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 10

−1.20

VIO − Input Offset Voltage − mV

12

−0.6 0 0.6 1.2

3

6

9

DISTRIBUTION OF TL034INPUT OFFSET VOLTAGE

TA = 25°C

ÎÎÎÎD Package

ÎÎÎÎÎÎÎÎÎÎ

VCC± = ±15 VÎÎÎÎÎÎÎÎÎÎÎÎ1681 Amplifiers Tested From 1 Wafer Lot

Per

cen

tag

e o

f Am

plif

iers

− %

Figure 11

−1.80

Per

cen

tag

e o

f Am

plif

iers

− %

VIO − Input Offset Voltage − mV

1.8−1.2 0.6 0 0.6 1.2

3

6

9

12

DISTRIBUTION OF TL034AINPUT OFFSET VOLTAGE

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

1716 Amplifiers Tested From 3 Wafer Lots

ÎÎÎÎÎN Package

ÎÎÎÎÎÎÎÎÎÎÎÎ

VCC± = ±15 VTA = 25°C

15

Figure 12

0−30

Per

cen

tag

e o

f U

nit

s −

%

− Input Offset-Voltage Temperature Coefficient − μV/°C

6

12

18

24

−20 −10 0 10 20 30

DISTRIBUTION OF TL031INPUT OFFSET-VOLTAGE

TEMPERATURE COEFFICIENT

76 Units Tested From 1 Wafer LotVCC± = ±15 VTA = 25°C to 125°CP Package

�VIO

Figure 13

−400

Per

cen

tag

e o

f Am

plif

iers

− %

− Temperature Coefficient − μV/°C

40

30

5

10

15

20

25

−30 −20 −10 0 10 20 30

DISTRIBUTION OF TL032INPUT OFFSET-VOLTAGE

TEMPERATURE COEFFICIENT

P Package

VCC± = ±15 VÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

160 Amplifiers Tested From 2 Wafer Lots

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

TA = 25°C to 125°C

�VIO

Page 29: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSET

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29POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 14

−400

Per

cen

tag

e o

f Am

plif

iers

− %

− Temperature Coefficient − μV/°C

40

30

5

10

15

20

25

−30 −20 −10 0 10 20 30

DISTRIBUTION OF TL034INPUT OFFSET-VOLTAGE

TEMPERATURE COEFFICIENT

D Package

VCC± = ±15 V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

160 Amplifiers Tested From 2 Wafer Lots

ÎÎÎÎÎÎTA = 25°C to 125°C

�VIO

Figure 15

−10−15

IIB −

Inp

ut

Bia

s C

urr

ent

− n

A

VIC − Common-Mode Input Voltage − V

−5

0

5

10

−10 −5 0 5 10 15

TA = 25°CVCC± = ±15 V

INPUT BIAS CURRENTvs

COMMON-MODE INPUT VOLTAGE

IBI

Figure 16

0.00125

TA − Free-Air Temperature − °C

0.01

0.1

1

10

45 65 85 105 125

INPUT BIAS CURRENT ANDINPUT OFFSET CURRENT†

vsFREE-AIR TEMPERATURE

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

VCC± = ±15 VVO = 0VIC = 0

ÎÎÎÎ

IIO

ÎÎÎÎÎÎ

IIB

IIB a

nd

IIO

− In

pu

t B

ias

and

Inp

ut

Off

set

Cu

rren

t −

nA

IBII I

O

Figure 17

−160

VIC

− C

om

mo

n-M

od

e In

pu

t Vo

ltag

e −

V

|VCC±| − Supply Voltage − V

−12

−8

−4

0

4

8

12

16

2 4 6 8 10 12 14 16

TA = 25°C

ÎÎÎÎÎÎÎÎÎÎ

Positive Limit

ÎÎÎÎÎÎÎÎÎÎ

Negative Limit

COMMON-MODE INPUT VOLTAGEvs

SUPPLY VOLTAGE

ÁÁÁÁÁÁ

VIC

† Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.

Page 30: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSETOPERATIONAL AMPLIFIERSSLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 18

1251007550250−25−50

20

15

10

5

0

−5

−10

−15

TA − Free-Air Temperature −°C−75

−20

VCC± = ±15 V

ÎÎÎÎÎPositive Limit

ÎÎÎÎÎÎÎÎÎÎ

Negative Limit

COMMON-MODE INPUT VOLTAGE†

vsFREE-AIR TEMPERATURE

VIC

− C

om

mo

n-M

od

e In

pu

t Vo

ltag

e −

V

ÁÁÁÁÁÁ

VIC

Figure 19

−1.5−5

−1

0

0.5

1

1.5

−4 −3 −2 −1 0 1 2 3 4 5

OUTPUT VOLTAGEvs

DIFFERENTIAL INPUT VOLTAGE

−0.5

ÎÎÎÎÎÎÎÎÎÎ

RL = 1 kΩÎÎÎÎRL = 2 kΩ

ÎÎÎÎRL = 5 kΩÎÎÎÎÎÎÎÎÎÎ

RL = 10 kΩÎÎÎÎÎÎÎÎÎÎ

RL = 20 kΩ

VCC± = ±5 VTA = 25°C

ÎÎÎRL = 1 kΩÎÎÎÎÎÎ

RL = 2 kΩ

ÎÎÎÎÎÎÎÎ

RL = 5 kΩ

ÎÎÎÎÎÎÎÎ

RL = 20 kΩ

ÎÎÎÎRL = 10 kΩ

− O

utp

ut

Volt

age

− V

VO

VID − Differential Input Voltage − V

Figure 20

−1.5−15

−1

−0.5

0

0.5

1

−10 −5 0 5 10

1.5

OUTPUT VOLTAGEvs

DIFFERENTIAL INPUT VOLTAGE

15

ÈÈÈÈÈÈÈÈ

RL = 5 kΩ

ÈÈÈÈÈÈÈÈ

RL = 10 kΩÈÈÈÈRL = 20 kΩÈÈÈÈÈÈÈÈ

RL = 50 kΩ

TA = 25°CVCC± = ±15 V

VID − Differential Input Voltage − V

− O

utp

ut

Volt

age

− V

VO

RL = 5 kΩRL = 10 kΩRL = 20 kΩRL = 50 kΩ

Figure 21

−160

VO

M −

Max

imu

m P

eak

Ou

tpu

t Vo

ltag

e −

V

|VCC±| − Supply Voltage − V

−12

−8

−4

0

4

8

12

16

2 4 6 8 10 12 14 16

TA = 25°CRL = 10 kΩ

ÎÎÎÎÎÎ

VOM−

VOM+

MAXIMUM PEAK OUTPUT VOLTAGEvs

SUPPLY VOLTAGE

ÁÁÁÁ

V OM

† Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.

Page 31: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

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31POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 22

01 k

VO

PP

− M

axim

um

Pea

k-to

-Pea

k O

utp

ut

Volt

age

− V

f − Frequency − Hz

5

10

15

20

25

30

10 k 100 k 1 M

TA = 125°C

VCC± = ±15 V

TA = −55°C

VCC± = ±5 V

MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE†

vsFREQUENCY

ÁÁÁÁÁÁ

VO

(PP

)

ÎÎÎÎÎÎÎÎÎÎ

RL = 10 kΩ

Figure 23

− M

axim

um

Pea

k O

utp

ut

Volt

age

− V

00

|IO| − Output Current − mA

1

2

3

4

5

5 10 15 20

VOM+

VOM−

VCC± = ±5 VTA = 25°C

MAXIMUM PEAK OUTPUT VOLTAGEvs

OUTPUT CURRENT

|V|

OM

Figure 24

00

|IO| − Output Current − mA5 10 15 20 25 30

2

4

6

8

10

12

14

16

ÎÎÎÎÎÎVOM−

ÎÎÎÎÎÎÎÎ

VOM+

VCC± = ±15 VTA = 25°C

MAXIMUM PEAK OUTPUT VOLTAGEvs

OUTPUT CURRENT

− M

axim

um

Pea

k O

utp

ut

Volt

age

− V

|V|

OM

Figure 25

−5−75

VO

M −

Max

imu

m P

eak

Ou

tpu

t Vo

ltag

e −

V

TA − Free-Air Temperature − °C

−4

−3

−2

−1

0

1

2

3

4

5

−50 −25 0 25 50 75 100 125

ÎÎÎÎVOM+

ÎÎÎÎÎÎ

VOM−

ÎÎÎÎÎÎÎÎÎÎ

VCC± = ±5 VRL = 10 kΩ

MAXIMUM PEAK OUTPUT VOLTAGE†

vsFREE-AIR TEMPERATURE

ÁÁÁÁÁÁ

V OM

† Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.

Page 32: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSETOPERATIONAL AMPLIFIERSSLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 26

−16

TA − Free-Air Temperature −°C

−75 −50 −25 0 25 50 75 100 125

−12

−8

−4

0

4

8

12

16

VOM+

MAXIMUM PEAK OUTPUT VOLTAGE†

vsFREE-AIR TEMPERATURE

ÎÎÎÎÎÎÎÎÎÎ

VCC± = ±15 VRL = 10 kΩ

VO

M −

Max

imu

m P

eak

Ou

tpu

t Vo

ltag

e −

V

ÁÁÁÁÁÁ

V OM

ÎÎÎÎÎÎ

VOM−

Figure 27

0

RL − Load Resistance − Ω

5

10

15

20

25

30

35

40

10 k 100 k 1 M

VCC± = ±15 V

VCC± = ±5 V

TA = 25°CVO = ±1 V

LARGE-SIGNAL DIFFERENTIALVOLTAGE AMPLIFICATION

vsLOAD RESISTANCE

− L

arg

e-S

ign

al D

iffe

ren

tial

AV

DV

olt

age

Am

plif

icat

ion

− V

/mV

0.110

f − Frequency − Hz

100 k

10 k

1 k

100

10

1

100 1 k 10 k 100 k 1 M 10 M

30°

60°

90°

120°

150°

180°

Ph

ase

Sh

ift

ÎÎÎÎÎÎ

AVD

VCC± = ±15 VRL = 10 kΩCL = 25 pFTA = 25°C

LARGE-SIGNAL DIFFERENTIAL VOLTAGEAMPLIFICATION AND PHASE SHIFT

vsFREQUENCY

ÎÎÎÎÎÎÎÎ

Phase Shift

− L

arg

e-S

ign

al D

iffe

ren

tial

AV

DV

olt

age

Am

plif

icat

ion

Figure 28

† Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.

Page 33: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSET

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33POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 29

−751

TA − Free-Air Temperature − °C125

50

−50 −25 0 25 50 75 100

10

VCC± = ±15 V

ÎÎÎÎÎÎÎÎ

RL = 10 kΩ

VCC± = ±5 V

LARGE-SIGNAL DIFFERENTIALVOLTAGE AMPLIFICATION†

vsFREE-AIR TEMPERATURE

− L

arg

e-S

ign

al D

iffe

ren

tial

AV

DV

olt

age

Am

plif

icat

ion

− V

/mV

Figure 30

1 k10

zo −

Ou

tpu

t Im

ped

ence

f − Frequency − Hz100 k

200

10 k

20

40

60

80

100

AVD = 100

AVD = 10

AVD = 1

VCC± = ±15 Vro (open loop) ≈ 250 Ω

OUTPUT IMPEDANCEvs

FREQUENCY

ÁÁΩÎÎÎÎÎTA = 25°C

ÁÁÁÁ

z o

Figure 31

100

CM

RR

− C

om

mo

n-M

od

e R

ejec

tio

n R

atio

− d

B

f − Frequency − Hz10 M

100

100 1 k 10 k 100 k 1 M

10

20

30

40

50

60

70

80

90VCC± = ±5 V

ÎÎÎÎÎÎÎÎ

TA = 25°C

COMMON-MODE REJECTION RATIOvs

FREQUENCY

Figure 32

100

f − Frequency − Hz10 M

100

100 1 k 10 k 100 k 1 M

10

20

30

40

50

60

70

80

90 ÎÎÎÎÎÎÎÎ

TA = 25°CVCC± = ±15 V

COMMON-MODE REJECTION RATIOvs

FREQUENCY

CM

RR

− C

om

mo

n-M

od

e R

ejec

tio

n R

atio

− d

B

† Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.

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34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 33

−7575

CM

RR

− C

om

mo

n-M

od

e R

ejec

tio

n R

atio

− d

B

TA − Free-Air Temperature − °C125

95

−50 −25 0 25 50 75 100

80

85

90

VCC± = ±15 V

VCC± = ±5 V

COMMON-MODE REJECTION RATIO†

vsFREE-AIR TEMPERATURE

ÎÎÎÎÎÎÎÎÎÎ

VIC = VICRmin

Figure 34

−7590

− S

up

ply

Vo

ltag

e R

ejec

tio

n R

atio

− d

B

TA − Free-Air Temperature − °C125

100

−50 −25 0 25 50 75 100

92

94

96

98

VCC± = ±5 V to ±15 V

SUPPLY-VOLTAGE REJECTION RATIO†

vsFREE-AIR TEMPERATURE

SV

Rk

Figure 35

0−30

IOS

− S

ho

rt-C

ircu

it O

utp

ut

Cu

rren

t −

mA

|VCC±| − Supply Voltage − V16

30

2 4 6 8 10 12 14

−20

−10

0

10

20

VO = 0TA = 25°C

VID = 100 mV

VID = −100 mV

SHORT-CIRCUIT OUTPUT CURRENTvs

SUPPLY VOLTAGE

ÁÁÁÁ

OS

I

Figure 36

0−20

t − Time − s30

30

5 10 15 20 25

−10

0

10

20

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

VCC± = ±15 VTA = 25°C

VID = −100 mV

VID = 100 mV

SHORT-CIRCUIT OUTPUT CURRENTvs

TIME

IOS

− S

ho

rt-C

ircu

it O

utp

ut

Cu

rren

t −

mA

ÁÁÁÁ

OS

I

† Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.

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TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSET

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TYPICAL CHARACTERISTICS

Figure 37

−75−25

− S

ho

rt-C

ircu

it O

utp

ut

Cu

rren

t −

mA

TA − Free-Air Temperature − °C125

25

−50 −25 0 25 50 75 100

−20

−15

−10

−5

0

5

10

15

20

SHORT-CIRCUIT OUTPUT CURRENT†

vsFREE-AIR TEMPERATURE

OS

I

ÎÎÎÎÎÎÎÎÎÎ

VID = 100 mV

ÎÎÎÎÎÎ

VO = 0

ÎÎÎÎÎÎVID = −100 mV ÎÎÎÎÎÎÎÎÎÎ

VCC± = ±5 V

ÎÎÎÎÎÎÎÎÎÎ

VCC± = ±15 V

ÎÎÎÎÎÎÎÎÎÎ

VCC± = ±15 V

ÎÎÎÎÎÎÎÎÎÎ

VCC± = ±5 V

Figure 38

1040

Vn

− E

qu

ival

ent

Inp

ut

No

ise

Volt

age

− n

VH

z

f − Frequency − Hz

100 k

70

60

50

100 1 k 10 k

ÁÁÁÁÁÁÁÁ

nV

/H

zV

n

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

VCC± = ±15 VRS = 20 ΩTA = 25°CSee Figure 3

TL031 and TL031AEQUIVALENT INPUT NOISE VOLTAGE

vsFREQUENCY

Figure 39

1030

Vn

− E

qu

ival

ent

Inp

ut

No

ise

Volt

age

− n

VH

z

f − Frequency − Hz100 k

60

50

40

100 1 k 10 k

Vn

ÁÁÁÁÁÁ

nV

/H

z ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

VCC± = ±15 VRS = 20 ΩTA = 25°CSee Figure 3

TL032 and TL032AEQUIVALENT INPUT NOISE VOLTAGE

vsFREQUENCY

Figure 40

1040

Vn

− E

qu

ival

ent

Inp

ut

No

ise

Volt

age

− n

VH

z

f − Frequency − Hz11 k

90

70

50

100 1 k 10 k

Vn

ÁÁÁÁÁÁ

nV

/H

z ÁÁÁÁÁÁÁÁÁÁÁÁ

VCC± = ±15 VRS = 20 ΩTA = 25°CSee Figure 3

80

60

TL034 and TL034AEQUIVALENT INPUT NOISE VOLTAGE

vsFREQUENCY

† Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.

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TYPICAL CHARACTERISTICS

Figure 41

00

|VCC±| − Supply Voltage − V16

250

2 4 6 8 10 12 14

50

100

150

200

TA = 25°C

TA = 125°C

TA = −55°C

ÁÁÁÁÁÁÁÁÁÁÁÁ

VO = 0No Load

ICC

− S

up

ply

Cu

rren

t −

A

ÁÁÁÁ

CC

IA

μ

TL031 and TL031ASUPPLY CURRENT†

vsSUPPLY VOLTAGE

Figure 42

00

ICC

− S

up

ply

Cu

rren

t −A

|VCC±| − Supply Voltage − V16

500

2 4 6 8 10 12 14

100

200

300

400

TA = 25°C

TA = 125°C

TA = −55°CÁÁÁÁÁÁ

CC

IA

μ

ÁÁÁÁÁÁ

VO = 0No Load

TL032 and TL032ASUPPLY CURRENT†

vsSUPPLY VOLTAGE

Figure 43

00

ICC

− S

up

ply

Cu

rren

t −A

|VCC±| − Supply Voltage − V16

1000

2 4 6 8 10 12 14

200

400

600

800

TA = 25°C

TA = 125°C

TA = −55°CÁÁÁÁÁÁ

CC

IA

μ

ÎÎÎÎÎÎÎÎÎ

VO = 0No Load

TL034 and TL034ASUPPLY CURRENT†

vsSUPPLY VOLTAGE

Figure 44

−750

TA − Free-Air Temperature − °C125

250

−50 −25 0 25 50 75 100

50

100

150

200

VCC± = ±15 V

VCC± = ±5 V

ÁÁÁÁÁÁÁÁÁ

VO = 0No Load

ICC

− S

up

ply

Cu

rren

t −

A

ÁÁÁÁ

CC

IA

μ

TL031 and TL031ASUPPLY CURRENT†

vsFREE-AIR TEMPERATURE

† Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.

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TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSET

OPERATIONAL AMPLIFIERSSLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

37POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 45

−750

TA − Free-Air Temperature − °C125

500

−50 −25 0 25 50 75 100

100

200

300

400

VCC± = ±15 V

VCC± = ±5 V

ICC

− S

up

ply

Cu

rren

t −A

ÁÁÁÁ

CC

IA

μ

ÁÁÁÁÁÁÁÁÁÁÁÁ

VO = 0No Load

TL032 and TL032ASUPPLY CURRENT†

vsFREE-AIR TEMPERATURE

Figure 46

−750

TA − Free-Air Temperature − °C125

1000

−50 −25 0 25 50 75 100

200

400

600

800

ÎÎÎÎÎÎÎÎÎÎ

VCC± = ±15 V

ÎÎÎÎÎÎÎÎÎÎ

VCC± = ±5 V

ICC

− S

up

ply

Cu

rren

t −A

ÁÁÁÁ

CC

IA

μ

ÎÎÎÎÎÎÎÎ

VO = 0No Load

TL034 and TL034ASUPPLY CURRENT†

vsFREE-AIR TEMPERATURE

Figure 47

10

RL − Load Resistance − kΩ100

6

1

2

3

4

5

10

SR−

SR+

SLEW RATEvs

LOAD RESISTANCE

SR

− S

lew

Rat

e −

V/s

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

VCC± = ±5 VCL = 100 pFTA = 25°CSee Figure 1

Figure 48

10

5

4

3

2

1

6

100RL − Load Resistance − kΩ

01

ÎÎSR+

ÎÎÎSR−

SLEW RATEvs

LOAD RESISTANCE

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

VCC± = ±15 VCL = 100 pFTA = 25°CSee Figure 1

SR

− S

lew

Rat

e −

V/s

† Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.

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38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 49

−750

TA − Free-Air Temperature − °C125

6

−50 −25 0 25 50 75 100

1

2

3

4

5

SR−

SR+

SLEW RATE†

vsFREE-AIR TEMPERATURE

SR

− S

lew

Rat

e −

V/s

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

VCC± = ±5 VRL = 10 kΩCL = 100 pFSee Figure 1

Figure 50

−750

TA − Free-Air Temperature − °C125

6

−50 −25 0 25 50 75 100

1

2

3

4

5SR−

SR+

SLEW RATE†

vsFREE-AIR TEMPERATURE

SR

− S

lew

Rat

e −

V/s

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

VCC± = ±15 VRL = 10 kΩCL = 100 pFSee Figure 1

Figure 51

00

Ove

rsh

oo

t F

acto

r −

%

CL − Load Capacitance − pF250

60

50 100 150 200

10

20

30

40

50

VI(PP) = ±10 mVRL = 10 kΩTA = 25°CSee Figure 1

ÎÎÎÎÎÎÎÎÎÎ

VCC± = ±5 V

OVERSHOOT FACTORvs

LOAD CAPACITANCE

ÎÎÎÎÎÎVCC± = ±15 V

Figure 52

1000.1

TH

D −

To

tal H

arm

on

ic D

isto

rtio

n −

%

f − Frequency − Hz100 k

0.5

0.2

0.3

0.4

1 k 10 k

VCC± = ±15 VAVD = 1VO(rms) = 6 VTA = 25°C

TOTAL HARMONIC DISTORTIONvs

FREQUENCY

† Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.

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TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSET

OPERATIONAL AMPLIFIERSSLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

39POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 53

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

00.9

|VCC±|− Supply Voltage − V16

1.1

2 4 6 8 10 12 14

0.95

1.0

1.05

UNITY-GAIN BANDWIDTHvs

SUPPLY VOLTAGE

VI = 10 mVRL = 10 kΩCL = 25 pFTA = 25°CSee Figure 4

B1

− U

nit

y-G

ain

Ban

dw

idth

− M

Hz

B1

Figure 54

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

−750.8

TA − Free-Air Temperature − °C125

1.3

−50 −25 0 25 50 75 100

0.9

1.0

1.1

1.2

VCC+ = ±15 V

VCC± = ±5 V

VI = 10 mVRL = 10 kΩCL = 25 pFSee Figure 4

UNITY-GAIN BANDWIDTH†

vsFREE-AIR TEMPERATURE

B1

− U

nit

y-G

ain

Ban

dw

idth

− M

Hz

B1

Figure 55

057°

m −

Ph

ase

Mar

gin

|VCC±| − Supply Voltage − V

16

65°

2 4 6 8 10 12 14

59°

61°

63°

PHASE MARGINvs

SUPPLY VOLTAGE

ÁÁÁÁÁÁ

φ m

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

VI = 10 mVRL = 10 kΩCL = 25 pF

See Figure 4

m −

Ph

ase

Mar

gin

ÁÁÁÁÁÁ

φ m

TA = 25°C

Figure 56

050°

CL − Load Capacitance − pF

100

70°

10 20 30 40 50 60 70 80 90

52°

54°

56°

58°

60°

62°

64°

66°

68°

PHASE MARGINvs

LOAD CAPACITANCE

m −

Ph

ase

Mar

gin

ÁÁÁÁ

φ m

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

VI = 10 mVRL = 10 kΩTA = 25°CSee Figure 4

ÎÎÎÎÎÎÎÎ

VCC± = ±5 V

NOTE A: Values of phase margin below a load capacitance of 25 pFwere estimated.

ÎÎÎÎÎÎÎÎ

See Note A

ÎÎÎÎÎVCC± = ±15 V

† Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.

Page 40: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

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40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 57

−7555°

TA − Free-Air Temperature −°C125

67°

−50 −25 0 25 50 75 100

57°

59°

61°

63°

65°

VCC± = ±5 V

PHASE MARGIN†

vsFREE-AIR TEMPERATURE

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

VI = 10 mVRL = 10 kΩCL = 25 pFSee Figure 4

− P

has

e M

arg

inmφ

ÎÎÎÎÎÎÎÎÎÎ

VCC± = ±15 V

Figure 58

−16

VO

− O

utp

ut

Volt

age

− m

V

t − Time − μs1.4

16

0 0.2 0.4 0.6 0.8 1.0 1.2

−12

−8

−4

0

4

8

12

VOLTAGE-FOLLOWERSMALL-SIGNAL

PULSE RESPONSE

ÁÁÁÁV

O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

VCC± = ±15 V

RL = 10 kΩCL = 100 pF

See Figure 1TA = 25°C

Figure 59

−2

VO

− O

utp

ut

Volt

age

− V

t − Time − μs8

2

0 1 2 3 4 5 6 7

0

1

VOLTAGE-FOLLOWERLARGE-SIGNAL

PULSE RESPONSE

ÁÁÁÁ

VO

VCC± = ±5 VRL = 10 kΩCL = 100 pFTA = 25°CSee Figure 1

−1

Figure 60t − Time − μs

0

−6

−2

2

4

6

0

−4

8

−8161412108642 18

VOLTAGE-FOLLOWERLARGE-SIGNAL

PULSE RESPONSE

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

See Figure 1TA = 25°CCL = 100 pFRL = 10 kΩVCC± = ±15 V

VO

− O

utp

ut

Volt

age

− V

ÁÁÁÁ

VO

† Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.

Page 41: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSET

OPERATIONAL AMPLIFIERSSLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

41POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

input characteristics

The TL03x and TL03xA are specified with a minimum and a maximum input voltage that, if exceeded at eitherinput, could cause the device to malfunction.

Due to of the extremely high input impedance and resulting low bias-current requirements, the TL03x andTL03xA are well suited for low-level signal processing; however, leakage currents on printed circuit boards andsockets easily can exceed bias-current requirements and cause degradation in system performance. It is a goodpractice to include guard rings around inputs (see Figure 61). These guard rings should be driven from alow-impedance source at the same voltage level as the common-mode input.

Unused amplifiers should be connected as grounded unity-gain followers to avoid oscillation.

(c) UNITY-GAIN AMPLIFIER(b) INVERTING AMPLIFIER(a) NONINVERTING AMPLIFIER

VOVI

+

VIVO

VO

VI

+

+

Figure 61. Use of Guard Rings

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APPLICATION INFORMATION

output characteristics

All operating characteristics (except bandwidth and phase margin) are specified with 100-pF load capacitance.The TL03x and TL03xA drive higher capacitive loads; however, as the load capacitance increases, the resultingresponse pole occurs at lower frequencies, thereby causing ringing, peaking, or even oscillation. The value ofthe load capacitance at which oscillation occurs varies with production lots. If an application appears to besensitive to oscillation due to load capacitance, adding a small resistance in series with the load should alleviatethe problem (see Figure 63). Capacitive loads of 1000 pF and larger can be driven if enough resistance is addedin series with the output (see Figure 62).

(a) CL = 100 pF, R = 0 (b) CL = 300 pF, R = 0 (c) CL = 350 pF, R = 0

(d) CL = 1000 pF, R = 0 (e) CL = 1000 pF, R = 50 Ω (f) CL = 1000 pF, R = 2 kΩ

Figure 62. Effect of Capacitive Loads

RVO

10 kΩ(see Note A)

CL− 15 V

15 V

−5 V

5 V

+

NOTE A: CL includes fixture capacitance.

Figure 63. Test Circuit for Output Characteristics

Page 43: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSET

OPERATIONAL AMPLIFIERSSLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

43POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

high-Q notch filter

In general, Texas Instruments enhanced-JFET operational amplifiers serve as excellent filters. The circuit inFigure 64 provides a narrow notch at a specific frequency. Notch filters are designed to eliminate frequenciesthat are interfering with the operation of an application. For this filter, the center frequency can be calculated as:

fO � 12�� R1 � C1

With the resistors and capacitors shown in Figure 64, the center frequency is 1 kHz. C1 = C3 = C2 + 2 andR1 = R3 = 2 × R2. The center frequency can be modified by varying these values. When adjusting the centerfrequency, ensure that the operational amplifier has sufficient gain at the frequency required.

+

0.2−8

Gai

n −

dB

f − Frequency − kHz2

2

0.4 0.6 0.8 1 0.2 0.4 0.6 0.8

−7

−6

−5

−4

−3

−2

0

1

R1 R3

1.5 MΩ

C2220 pF

R3 750 kΩ

C1 C3

110 pF 110 pF

1.5 MΩ

15 V

−15 V

TL03x

VOVI

−1

Figure 64. High-Q Notch Filter

Page 44: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

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APPLICATION INFORMATION

transimpedance amplifier

The low-power precision TL03x allows accurate measurement of low currents. The high input impedance andlow offset voltage of the TL03xA greatly simplify the design of a transimpedance amplifier. At room temperature,this design achieves 10-bit accuracy with an error of less than 1/2 LSB.

Assuming that R2 is much less than R1 and ignoring error terms, the output voltage can be expressed as:

VO � –IIN � RF�R1 � R2

R2�

Using the resistor values shown in the schematic for a 1-nA input current, the output voltage equals −0.1 V. Ifthe VO limit for the TL03xA is measured at ±12 V, the maximum input current for these resistor values is ±120 nA.Similarly, one LSB on a 10-bit scale corresponds to 12 mV of output voltage, or 120 pA of input current.

The following equation shows the effect of input offset voltage and input bias current on the output voltage:

VO � – �VIO � RF�IIO � IIB

���R1 � R2R2

If the application requires input protection for the transimpedance amplifier, do not use standard PN diodes.Instead, use low-leakage Siliconix SN4117 JFETs (or equivalent) connected as diodes across the TL03xAinputs (see Figure 65).

As with all precision applications, special care must be taken to eliminate external sources of leakage andinterference. Other precautions include using high-quality insulation, cleaning insulating surfaces to removefluxes and other residue, and enclosing the application within a protective box.

+

15 V

−15 V

TL03xA

RF

10 MΩ

90 kΩ

VO

10 kΩR2

SN4117

R1

Input Current

Figure 65. Transimpedance Amplifier

Page 45: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSET

OPERATIONAL AMPLIFIERSSLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

45POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

4-mA to 20-mA current loops

Often, information from an analog sensor must be sent over a distance to the receiving circuitry. For manyapplications, the most feasible method involves converting voltage information to a current before transmission.The following circuits give two variations of low-power current loops. The circuit in Figure 66 requires three wiresfrom the transmitting to receiving circuitry, while the second variation in Figure 67 requires only two wires, butincludes an extra integrated circuit. Both circuits benefit from the high input impedance of the TL03xA becausemany inexpensive sensors do not have low output impedance.

Assuming that the voltage at the noninverting input of the TL03xA is zero, the following equation determinesthe output current:

IO � VI� R3R1 � RS

�� 5V� R3R2 � RS

� � 0.16 � VI � 4mA

The circuits presently provide 4-mA to 20-mA output current for an input voltage of 0 to 100 mV. By modifyingR1, R2, and R3, the input voltage range or the output current range can be adjusted.

Including the offset voltage of the operational amplifier in the above equation clearly illustrates why the low offsetTL03xA was chosen:

IO � VI� R3R1 � RS

�� 5V� R3R2 � RS

� VI� R3R1 � RS

� R3R2 � RS

� R1RS�

� 0.16 � VI � 4mA – 0.17 � VI

For example, an offset voltage of 1 mV decreases the output current by 0.17 mA.

Due to the low power consumption of the TL03xA, both circuits have at least 2 mA available to drive the actualsensor from the 5-V reference node.

Page 46: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSETOPERATIONAL AMPLIFIERSSLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

46 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

+

R5

3.3 kΩ2N3904

TL03xA

1 MΩR2

R1

5 kΩ

R3 80 kΩ

R4 5 kΩ

VI

Signal Common

1N4148

RS

100 ΩRL 50 Ω

IO

5 V Ref

VCC+ = 10 V

VEE = −5 V

100 kΩ

R7

R6

TL431

100 kΩ

Figure 66. Three-Wire 4-mA to 20-mA Current Loop

100 Ω

+

32

4

8

5

LTC1044

10 μF

10 μF

R5

3.3 kΩ2N3904

TL03xA

1 MΩR2

R1

5 kΩ

R3 80 kΩ

R4 5 kΩ

VI

Signal Common

1N4148

RS

RL 50 Ω

IO

LT1019-5

GND

OUT

IN

5 V Ref

VCC+ = 10 V

Figure 67. Two-Wire 4-mA to 20-mA Current Loop

Page 47: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSET

OPERATIONAL AMPLIFIERSSLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

47POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

low-level light-detector preamplifier

Applications that need to detect small currents require high input-impedance operational amplifiers; otherwise,the bias currents of the operational amplifier camouflage the current being monitored. Phototransistors providea current that is proportional to the light reaching the transistor. The TL03x allows even the small currentsresulting from low-level light to be detected.

In Figure 68, if there is no light, the phototransistor is off and the output is high. As light is detected, theoperational amplifier output begins pulling low. Adjusting R4 both compensates for offset voltage of the amplifierand adjusts the point of light detection by the amplifier.

TL03x

+

R6

10 kΩ

C1100 pF

R7

R3

R1

TIL601

R2 5 kΩ

R5

R4

10 kΩ

10 kΩ

10 kΩ10 kΩ

10 kΩ

15 V

VO

−15 V

Figure 68. Low-Level Light-Detector Preamplifier

Page 48: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSETOPERATIONAL AMPLIFIERSSLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

48 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

audio-distribution amplifier

This audio-distribution amplifier (see Figure 69) feeds the input signal to three separate output channels. U1Aamplifies the input signal with a gain of 10, while U1B, U1C, and U1D serve as buffers to the output channels.The gain response of this circuit is very flat from 20 Hz to 20 kHz. The TL03x allows quick response to the inputsignal while maintaining low power consumption.

+

VCC+

R41 MΩ

C11 μF

U1B

R510 kΩ

R3100 kΩ

C2100 μF

+

−U1C

+

−U1D

+

U1A

R2100 kΩ

R1100 kΩ

VI

VCC+ VOA

VOB

VOC

NOTE A: U1A through U1D = TL03x; VCC+ = 5 V

Figure 69. Audio-Distribution Amplifier Circuit

Page 49: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

TL03x, TL03xAENHANCED-JFET LOW-POWER LOW-OFFSET

OPERATIONAL AMPLIFIERSSLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

49POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

instrumentation amplifier with linear gain adjust

The low offset voltage and low power consumption of the TL03x provide an accurate but inexpensiveinstrumentation amplifier (see Figure 70). This particular configuration offers the advantage that the gain canbe linearly set by one resistor:

VO = R6R5

× (VB − VA)

Adjusting R6 varies the gain. The value of R6 always should be greater than, or equal to, the value of R5 toensure stability. The disadvantage of this instrumentation amplifier topology is the high degree of CMRRdegradation resulting from mismatches between R1, R2, R3, and R4. For this reason, these four resistorsshould be 0.1%-tolerance resistors.

+

−U1C

+

U1A

R61 MΩ

VA

VCC+

VO

+

+

VB

U1B

R210 kΩ0.1%

R410 kΩ0.1%

R7100 kΩ

R5100 kΩ

R110 kΩ0.1%

R310 kΩ0.1%

U1D

VCC−

NOTE A: U1A through U1D = TL03x; VCC± = ±15 V

Figure 70. Instrumentation Amplifier With Linear Gain-Adjust Circuit

Page 50: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

PACKAGE OPTION ADDENDUM

www.ti.com 17-Mar-2017

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

TL031CD ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL031C

TL031CDG4 ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL031C

TL031CDR ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL031C

TL031CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL031C

TL031CP ACTIVE PDIP P 8 50 Pb-Free(RoHS)

CU NIPDAU N / A for Pkg Type 0 to 70 TL031CP

TL031CPE4 ACTIVE PDIP P 8 50 Pb-Free(RoHS)

CU NIPDAU N / A for Pkg Type 0 to 70 TL031CP

TL031ID ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL031I

TL031IDG4 ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL031I

TL031IP ACTIVE PDIP P 8 50 Pb-Free(RoHS)

CU NIPDAU N / A for Pkg Type -40 to 85 TL031IP

TL032ACD ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 0 to 70 032AC

TL032ACDG4 ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 0 to 70 032AC

TL032ACDR ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 0 to 70 032AC

TL032ACP ACTIVE PDIP P 8 50 Pb-Free(RoHS)

CU NIPDAU N / A for Pkg Type 0 to 70 TL032ACP

TL032AID ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 032AI

TL032AIDG4 ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 032AI

TL032AIDR ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 032AI

TL032AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 032AI

Page 51: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

PACKAGE OPTION ADDENDUM

www.ti.com 17-Mar-2017

Addendum-Page 2

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

TL032AIP ACTIVE PDIP P 8 50 Pb-Free(RoHS)

CU NIPDAU N / A for Pkg Type -40 to 85 TL032AIP

TL032CD ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL032C

TL032CDE4 ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL032C

TL032CDR ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL032C

TL032CDRE4 ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL032C

TL032CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL032C

TL032CP ACTIVE PDIP P 8 50 Pb-Free(RoHS)

CU NIPDAU N / A for Pkg Type 0 to 70 TL032CP

TL032CPE4 ACTIVE PDIP P 8 50 Pb-Free(RoHS)

CU NIPDAU N / A for Pkg Type 0 to 70 TL032CP

TL032CPSR ACTIVE SO PS 8 2000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 0 to 70 T032

TL032ID ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL032I

TL032IDE4 ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL032I

TL032IDG4 ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL032I

TL032IDR ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL032I

TL032IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL032I

TL032IP ACTIVE PDIP P 8 50 Pb-Free(RoHS)

CU NIPDAU N / A for Pkg Type -40 to 85 TL032IP

TL032IPE4 ACTIVE PDIP P 8 50 Pb-Free(RoHS)

CU NIPDAU N / A for Pkg Type -40 to 85 TL032IP

TL034ACD ACTIVE SOIC D 14 50 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL034AC

TL034ACDR ACTIVE SOIC D 14 2500 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL034AC

Page 52: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

PACKAGE OPTION ADDENDUM

www.ti.com 17-Mar-2017

Addendum-Page 3

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

TL034ACDRE4 ACTIVE SOIC D 14 2500 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL034AC

TL034ACN ACTIVE PDIP N 14 25 Pb-Free(RoHS)

CU NIPDAU N / A for Pkg Type 0 to 70 TL034ACN

TL034AID ACTIVE SOIC D 14 50 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL034AI

TL034AIDG4 ACTIVE SOIC D 14 50 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL034AI

TL034AIDR ACTIVE SOIC D 14 2500 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL034AI

TL034AIN ACTIVE PDIP N 14 25 Pb-Free(RoHS)

CU NIPDAU N / A for Pkg Type -40 to 85 TL034AIN

TL034CD ACTIVE SOIC D 14 50 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL034C

TL034CDR ACTIVE SOIC D 14 2500 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL034C

TL034CN ACTIVE PDIP N 14 25 Pb-Free(RoHS)

CU NIPDAU N / A for Pkg Type 0 to 70 TL034CN

TL034CNE4 ACTIVE PDIP N 14 25 Pb-Free(RoHS)

CU NIPDAU N / A for Pkg Type 0 to 70 TL034CN

TL034CNSR ACTIVE SO NS 14 2000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL034

TL034CPW ACTIVE TSSOP PW 14 90 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 0 to 70 T034

TL034CPWR ACTIVE TSSOP PW 14 2000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 0 to 70 T034

TL034ID ACTIVE SOIC D 14 50 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL034I

TL034IDG4 ACTIVE SOIC D 14 50 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL034I

TL034IDR ACTIVE SOIC D 14 2500 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL034I

TL034IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL034I

TL034IN ACTIVE PDIP N 14 25 Pb-Free(RoHS)

CU NIPDAU N / A for Pkg Type -40 to 85 TL034IN

Page 53: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

PACKAGE OPTION ADDENDUM

www.ti.com 17-Mar-2017

Addendum-Page 4

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

TL034INE4 ACTIVE PDIP N 14 25 Pb-Free(RoHS)

CU NIPDAU N / A for Pkg Type -40 to 85 TL034IN

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Page 54: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

TL031CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TL032ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TL032AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TL032CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TL032CPSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1

TL032IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TL034AIDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

TL034CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

TL034CNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1

TL034CPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 10-May-2018

Pack Materials-Page 1

Page 55: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TL031CDR SOIC D 8 2500 340.5 338.1 20.6

TL032ACDR SOIC D 8 2500 340.5 338.1 20.6

TL032AIDR SOIC D 8 2500 340.5 338.1 20.6

TL032CDR SOIC D 8 2500 340.5 338.1 20.6

TL032CPSR SO PS 8 2000 367.0 367.0 38.0

TL032IDR SOIC D 8 2500 340.5 338.1 20.6

TL034AIDR SOIC D 14 2500 367.0 367.0 38.0

TL034CDR SOIC D 14 2500 367.0 367.0 38.0

TL034CNSR SO NS 14 2000 367.0 367.0 38.0

TL034CPWR TSSOP PW 14 2000 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 10-May-2018

Pack Materials-Page 2

Page 56: Enhanced-JFET Low-Power Low-Offset Operational … TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 POST OFFICE
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IMPORTANT NOTICE

Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to itssemiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyersshould obtain the latest relevant information before placing orders and should verify that such information is current and complete.TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integratedcircuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products andservices.Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and isaccompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduceddocumentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statementsdifferent from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for theassociated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designersremain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers havefull and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI productsused in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. 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Designers mustensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products inlife-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., lifesupport, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). 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