The Effect of Delayed Zero Crossings Following a Short Circuit on System

Stability

James Gallagher*, Neil McDonagh and William Phang

ESB International

Ireland

SUMMARY

Fundamental to a circuit breaker is that it can only

break a fault current when the alternating current

crosses the zero. A fault current is made up of a DC

and AC component. If the DC component is

sufficiently large, there will be a large delay before

the current crosses the zero and therefore a large

delay before the circuit breaker can break the fault

current. This delay can be of the order of hundreds of

milliseconds.

The issue of delayed zero crossings following a short

circuit has been well documented in various literature

[1-3], however is still not adequately legislated for in

IEEE or IEC standards. This paper adds to the

existing body of knowledge by assessing the effects

of delayed zero crossings on system stability. This

paper uses a generic generator model to test for the

possibility of delayed current zeros following a short

circuit. This delay will then be used to assess the

effect on system stability using a generic bus system.

Keywords: Circuit Breaker – Zero Crossing– Stability

1. INTRODUCTION

Upon the occurrence of a fault, current of large

magnitude will flow. Initially, this current is a

combination of alternating and direct currents (AC

and DC). The DC component decays with time and

the time constant of this decay is determined by the

X/R ratio at the fault site. In the case of a high X/R

ratio, this decay time can be extremely large.

In cases where the DC component of the fault current

is larger than the AC component and the time

constant is quite large, the fault current wave form

may not cross zero for a long period of time. A

simplified LR circuit is shown in Figure 1.1.

Figure 1.1 – Switching of LR circuit

For a short circuit calculation in a simplified single

phase system the fault current may be defined as

shown in Equation 1 [4]. The waveform of a fault on

this system is shown in Figure 1.2. As can be seen,

the fault current is a combination of the AC

symmetrical component and the DC offset.

Figure 1.2 – Fault Current

*ESB International, Stephen Court, 18-21 St Stephen’s Green, Dublin 2, Ireland

( )

−+

+

−+

−

+

−= −−−

R

Lt

LR

E

R

L

LR

Eeti

tLR ωϕω

ω

ωϕ

ω

1

222

max1

222

max/ tansintansin)(Equation 1

Asymmetrical Current

AC Component DC Component

I

t

If the simple system from Figure 1.1 is connected to a

load as illustrated in Figure 1.3, an initial pre-fault

current component is considered in the DC offset.

Figure 1.3 – LR Circuit Feeding Load

This additional term in the DC offset will be of the

form:

( )0

/Ie

tLR−

Where I0 = pre-fault current flowing in the load

This I0 term is dependant on the current flowing in

the load and if it is in phase with the DC component,

from Equation 1 it will result in the DC component

being greater than the AC component which will

result in a delayed zero crossing. The longest delayed

zero crossings are associated with capacitive loads.

That is when generators are operating in the under-

excited condition.

A waveform plot displaying a delayed zero crossing

is shown in Figure 1.4.

Figure 1.4 – Delayed Zero Crossing

1.1 Worst Case Delayed Zero Crossings

In reference to delayed zero crossings the worst case

scenario is a two phase fault that develops into a

three-phase fault, while generators are operating in an

under excited condition. This fault starts as a line to

line fault which initiates at the zero crossing of the

line to line voltage, which then develops into a three-

phase fault 5ms later. The worst case scenario occurs

when there is negligible resistance in the fault path,

so ideally this fault is a bolted fault. The occurrence

of this scenario is highly improbable but it is still

possible. One of the only instances in which this may

happen is if a section of network within the station is

outaged with earths applied, and the circuit breaker is

closed. Two poles of the circuit breaker must close in

unison at the zero point of the phase to phase voltage

between those two phases with the remaining pole

closing 5ms later. This sequence of events will result

in the largest DC offset and the longest zero crossing

delay times.

Significant delay times can also occur for other types

of faults such as simultaneous three-phase faults.

1.2 Circuit Breaker Operation

When a circuit breaker attempts to open, the current

flowing through the breaker must cross zero or close

to zero depending upon current chopping

characteristics. If there is no zero crossing, an arc will

form in the arc channel of the circuit breaker. This

arc will have a variable resistance, at medium voltage

levels the per unit resistance of this arc is sufficient to

change the X/R ratio in the fault path and bring about

a zero crossing. For high voltage circuit breakers the

arc resistance is much less effective in bringing about

a zero crossing, meaning that it may be difficult to

interrupt faults on the HV system near to generators.

If a circuit breaker attempts to break a current that

does not cross zero, it risks forming an arc that will

not be broken. This will destroy the circuit breaker,

endanger the lives of people in the vicinity of the

station, items of plant connected to the system, and

threaten the stability of the whole system. There is no

straightforward solution to this issue. The clearest

way to ensure that the ability of the circuit breaker to

break the fault current is not compromised is to

decrease the X/R ratio in the path feeding the fault,

delay the opening time of the breaker or, limit the

operation of generators.

1.3 Effects on Stability

It is possible that the fault on the system cannot be

cleared or it may be purposely not cleared until a zero

crossing has occurred. This zero crossing may not

occur for several hundred milliseconds. A fault on the

system for this long could have detrimental effects on

the stability of the system. The system can be studied

in terms of both voltage stability and transient angle

stability. Voltage instability is the result of a

progressive decline in voltage due to a disturbance.

Voltage stability issues are associated with the

transfer of active and reactive power over a highly

inductive network. It is also influenced by generator

and load characteristics, tap changer action and

reactive power compensation devices. Transient

stability analyses the ability of a power system to

maintain synchronous operation when subjected to a

transient disturbance. Transient stability is influenced

by fault clearance time, post-fault transmission

system reactance, generator loading, output,

reactance and inertia [5].

2. ANALYSIS

In order to assess the effects of delayed zero

crossings, a number of software models were

constructed. These models were used to both

calculate the delayed zero crossings and examine the

effect of those delayed zero crossings on stability. An

EMTP – ATP (Alternative Transients program)

model was used to calculate the delayed zero

Delayed zero crossing

Load

Equation 2

I

t

crossings time delay. A PSSTM

E (Power System

Simulator for Engineers) model was used in order to

carry out dynamic simulations and analyse the effect

on system stability. For the purpose of this analysis, a

generic bus system was used to provide an example

of the effect of delayed zero crossings.

2.1 Voltage Stability Test System This paper presents a relatively small system for the

analysis of voltage collapse issues. It is based on the

1979 IEEE Reliability Test System [6]. Modifications

were made to this system to make it more suitable for

voltage stability analysis[6].

This test system contains the following elements:

Network

Element

Amount on

Test System

230kV bus 14

138kV bus 10

18kV bus 34

13.8kV bus 17

230kV Feeder 21

138kV Feeder 13

Generators 32

SVC 2

Table 2.1 – Test System Elements

The total load of the system is 3,200MW.

2.2 Delayed Zero Crossing Test System

A model of a single generator and step-up

transformer was built using software package EMTP

– ATP. Generic gas turbine generator and transformer

models were used. This test system was used to

calculate the duration of the fault the be applied on

the voltage stability test system.

2.3 Fault Scenario As discussed in Section 1.1, the worst case fault

scenario is a two phase fault that develops into a

three-phase fault. Delays for simultaneous three-

phase fault are also of a similar order, although

generally shorter. In this paper only simultaneous

three-phase faults are analysed.

3. DELAYED ZERO CROSSING RESULTS Zero crossing times for various machine operating

points were calculated in ATP for the generic

generator. It was found that a delay time of 326ms

from fault inception until fault zero crossing was

calculated for the machine operating point of

168.5MW, 120.3 MVAr under-excited. For this

calculation, neither circuit breaker operation nor arc

resistance were modelled. Figure 3.1 shows the

waveform for one of the faulted phases.

0.0 0.1 0.2 0.3 0.4 0.5[s]-1000

100

1200

2300

3400

4500

[A]

Simultaneous Fault, No Circuit Breaker, ST1, 168.5MW 120.3MVAr Under-Excited

Figure 3.1 – Delayed Zero Crossing Waveform

Figure 3.2 shows zero crossing delay times for a

variety of machine operating points. The operating

points are grouped into regions according to the delay

time for zero crossing to occur.

Region 1: time <= 100ms

Region 2: 100 < time <= 200ms

Region 3: time > 200ms

Delayed Zero Crossing

0

50

100

150

200

250

300

350

400

-150 -100 -50 0 50 100 150

MVAr

MW

Limits

t<=100ms

100ms<t<=200ms

t>200ms

Figure 3.2 – Operating Points and Delays

4. VOLTAGE STABILITY RESULTS Simultaneous three-phase faults sustained for various

time lengths were applied at ASTOR 230kV bus (bus

number 118). It is assumed that the fault is sustained

at the 230kV bus for an extended period of time as

the circuit breakers cannot clear the fault until a zero

crossing occurs.

4.1 Effect of 100ms Delay

A 100ms delay corresponds to a machine operating

point of 51.3 MW, 23.9 MVAr under-excited, see

Region 1 in Figure 3.2.

Figure 4.1 shows the bus voltage for fault at bus 118.

A three-phase fault is applied at 1s and sustained for

0.1s before being cleared. When the fault is cleared,

the system voltages are restored to the pre-fault

values and the oscillations die out.

326ms

Region 1

Region 2 Region 3

Figure 4.1 – Faulted Bus Voltage

Figures 4.2 and 4.3 show the output of the SVCs at

bus 10114 (-50/+200 MVAr) and 10116 (-50/+100

MVAr).

Both increase to their maximum reactive power

output value on occurrence of the fault and stay at

this value for approx 0.5s after the fault is cleared.

They both then decrease to a steady state value.

Figure 4.2 – SVC at Bus 10114

Figure 4.3 - SVC at Bus 10116

Figures 4.4 and 4.5 show the active and reactive

power outputs of the machine feeding the faulted bus

118. On occurrence of the fault, the active power

output of the machine drops but it increases back to

its pre-fault steady state value after approximately

10-15 seconds.

Figure 4.4 – Active Power Output

The reactive power output of the machine initially

increases. However, the reactive power then

decreases back to its pre-fault value after the fault has

been cleared.

Figure 4.5 – Reactive Power Output

As can be seen from Figures 4.1 - 4.5, the system can

cope with a three-phase fault of 100ms duration. That

is, a fault in which a zero crossing occurs and

therefore circuit breakers can act within 100ms.

Section 4.2 presents a situation where the fault is not

cleared within the first 100ms.

4.2 Effect of 326ms Delay

Figure 4.6 shows the voltage at bus 118 where a fault

with a delayed zero crossing is applied. A time of

326ms for the delayed zero crossing is used. This is

the maximum time calculated using the Delayed Zero

Crossing Test System for a simultaneous three-phase

fault. The fault is applied at 1s and sustained until

1.326s when it is cleared.

As can be seen from Figure 4.6, the system cannot

recover the voltages when a fault is sustained for this

long and the system loses stability.

Figure 4.6 - Faulted Bus Voltage

Figures 4.7 and 4.8 show the output of the SVCs at

bus 10106 (-50/+100 MVAr) and 10114 (-50/+200

MVAr). On occurrence of the fault, both SVCs

increase to their maximum output values of reactive

power to raise the system voltages. However, this is

not enough to prevent the system becoming unstable.

Figure 4.7 - SVC at Bus 10114

Figure 4.8 - SVC at Bus 10116

Figures 4.9 and 4.10 show the active and reactive

power outputs of the machine connected to bus 118.

As can be seen the system becomes unstable

approximately 0.5s after the fault is cleared.

Figure 4.9 - Active Power Output

Figure 4.10 - Reactive Power Output

Figures 4.6-4.10 demonstrate that a small power

system cannot cope with a fault being sustained for

326ms. It is important, therefore, to prevent the

occurrence of a fault with delayed zero crossings.

Section 5 presents some possible mitigating actions

to prevent such a fault occurring.

5. DISCUSSION

In essence the phenomenon of delayed zero crossings

is not a new problem but is becoming more of an

issue due to the advent of low(er) loss generators and

transformers.

Unfortunately the matter of delayed zero crossings as

a result of a fault on a high voltage system is an issue

that is not adequately dealt with by international

standards [7]. Therefore, there is no standard with

which HV manufacturers can design and test their

equipment adequately.

Some mitigating actions are discussed in Sections

5.1-5.3.

5.1 Limit Operating Range of Generator If this were considered a viable solution, results

suggest that the generator would have to be limited

from operating with a leading power factor.

This may have serious implications for the control of

voltages in the region and it is questionable that a

system operator would allow such a solution.

If there is a requirement for the plant to provide

voltage control to the system, an adequately sized

reactive compensation provided by a shunt reactor,

SVC or STATCOM, would remove the need for the

generators at the plant to operate in the under-excited

mode.

5.2 Insert Series Resistor in Generator Circuit

One of the most straightforward ways to eliminate

delayed zero crossing is to include additional

resistance in the circuit. This additional resistance

may be provided in a number of ways but the most

straightforward would be to increase the resistive

losses in the transformer. This action will decrease

the X/R ratio and improve the ability of the circuit

breakers in the clearing of worst case possible faults.

It also must be worth noting that this action will

reduce the overall efficiency of the plant. There may

also be issues surrounding the adequate dissipation of

heat from a transformer with increased resistive

losses.

5.3 Protection Coordination

It may also be of value to consider the backup

protection provided by the MV system. With regards

to the adequacy of medium voltage breakers to break

faults resulting in delayed zero crossings [8] states

the following:

“It is generally accepted that the generator circuit

breaker will be required, during its life, to interrupt

short-circuit currents from the generator-source with

delayed current zeros. ……. The determining arc

voltage model is derived from tests with comparable

magnitudes of current.”

As this is the case, it may be prudent to rely more on

MV circuit breakers to break faults on the HV

system. This may be achieved by the adequate

coordination of protection provided by the MV

generator circuit breakers.

Reducing the backup protection time will reduce the

possibility of damage to the high voltage circuit

breaker and other plant. However, the employment of

this solution may result in an increased number of

generator trips.

5.4 Operational Considerations The phenomenon of delayed zero crossings occurs as

a result of a three-phase fault. Two of the most

probable ways in which a three-phase fault can occur

is a result of lightning or leaving earths connected to

a line or busbar. An exhaustive assessment of a

particular site may conclude that the actual

probability of occurrence of such a three-phase fault

may be at an acceptable level without the need for

additional mitigating actions.

6. CONCLUSIONS

From the simulations on the voltage stability test

system, it was found that the system remained stable

for a fault on the system for 100ms. However, if a

fault is sustained on the system for 326ms, the system

loses stability. Calculations from the delayed zero test

system showed that fault of a duration of 326ms

could occur as a result of a delayed zero crossing. It

is clear that this would have drastic consequences for

a small/medium sized power system.

If it is required that plant be designed to be protected

from this phenomenon, the following mitigating

actions may prevent a loss of system stability in the

event of a three-phase fault:

• Limit operating range of generator in

conjunction with the use of a SVC or

STATCOM

• Use of series resistance

• Protection coordination

Naturally, there are drawbacks associated with each

of these measures and each one would have to be

studied individually to assess its effectiveness. As

part of this detailed assessment, the operational

aspects of a particular plant would also have to be

considered.

REFERENCES [1]. H. Hamada et al “Sever Duties on High-

Voltage Circuit Breakers Observed in

Recent Power Systems” Cigre 13-103

Session 2002

[2]. S. Henschel et al “Breaking Capability of High

Voltage SF6 Breakers in Power Plants” XI

Symposium of Specialists in electric

Operational and Expansions Planning,

Brazil 2009.

[3]. B. Kulicke et al “Clearance of Short-Circuits

with Delayed Current Zeros in the ITAIPU

550kV Substation”

[4]. L Van Der Sluis, Transients in Power Systems,

John Wiley and Sons, 2001

[5]. P. Kundur, Power System Stability and

Control, McGraw-Hill, 1994

[6]. L. T. G. Lima et al “PSS®E Test System for

Voltage Collapse Analysis”

[7]. R.E Cossé et al “IEC Medium Voltage Circuit

Breaker Interruption Ratings – Unstated

Short-Circuit Considerations

[8]. IEEE Std C37.013™-1997 (R2008) IEEE

Standard for AC High-Voltage Generator

Circuit Breakers Rated on a Symmetrical

Current Basis