COVER SHEET

TITLE

5-26-1999_17:09 1

** PLEASE NOTE THESE SCHEMATICS ARE SUBJECT TO CHANGE

UNIPROCESSOR CUSTOMER REFERENCE SCHEMATICS

PAGE

REVISION 1.3

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF 40

1.3

PROJECT:INTEL(R) 810CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

INTEL(R) CELERON(TM) PROCESSOR (PPGA)/INTEL(R) 810 CHIPSET

Cover Sheet 1Block Diagram 2370-Pin Socket 3,4GTL Termination 5Clock Synthesizer 6GMCH 7,8,9Frame Buffer 10DIMM Sockets 11,12ICH0 13,14FWH 15Super I/O 16PCI Connectors 17,18ATA33 IDE Connectors 19USB Connectors 20Parallel Port 21Serial/Game Ports 22Keyboard/Mouse/Floppy Disk 23Digital Video Out (TBD) 24Graphics Connectors 25AC’97 Riser Connector 26LAN 27,28System Voltage Regulators 29Processor Voltage Regulator 30System 31,32Pullup Resistors and Unused Gates 33Decoupling 34,35

THESE SCHEMATICS ARE PROVIDED “AS IS” W ITH NO W ARRANTIESW HATSOEVER, INCLUDING ANY W ARRANTY OF MERCHANTABILITY,FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY W ARRANTYOTHERW ISE ARISING OUT OF PROPOSAL, SPECIFICATION OR SAMPLES.

Inform ation in this docum ent is provided in connection with Intel products. Nolicense, express or im plied, by estoppel or otherwise, to any intellectual propertyrights is granted by this docum ent. Except as provided in Intel's Term s andConditions of Sale for such products, Intel assum es no liability whatsoever, andIntel disclaim s any express or im plied warranty, relating to sale and/or use of Intelproducts including liability or warranties relating to fitness for a particular purpose,m erchantability, or infringem ent of any patent, copyright or other intellectualproperty right. Intel products are not intended for use in m edical, life saving, or lifesustaining applications.

Intel m ay m ake changes to specifications and product descriptions at any tim e,without notice.

The Intel CeleronTM processor and Intel 810 chipset m ay contain design defectsor errors known as errata which m ay cause the product to deviate from publishedspecifications. Current characterized errata are available on request.

Copyright © Intel Corporation 1998.

*Third-party brands and nam es are the property of their respective owners.

BLOCK DIAGRAM

11-23-1998_13:43 2

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF 40

1.3

PROJECT:INTEL(R) 810

CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

DA

TA

CT

RL

AD

DR

Term

VRM

ICH0

Keyboard

Mouse

Floppy Parallel

Serial 1

SIO

Clock

PC

I CO

NN

1

PC

I CO

NN

2

PC

I CO

NN

3

Block Diagram

Device Table

2 DIMMModules

USB Port 1

USB Port 2

Audio/ModemAMC’97

PCI CNTRL

CT

RL

DA

TA

AD

DR

IDE Primary

IDE Secondary

UltraDMA/33

USB

PCI CNTRL

PCI ADDR/DATA

AC’97 Link

FirmWare Hub

PCI ADDR/DATA

LPC

Bus LAN

GMCH

Game Conn

Display CacheMemory

Out DeviceDigital Video

370-Pin Socket Processor REFERENCE DESIGNATOR DEVICE TYPE GATES USED

SHEET NUMBER

U12 74lvc14a A,B,C,D 32U16,U17 gd75232 22U15 lpc47b27_a 16U3 74lvc06a A,B,C,D 29,32U1 ck-whitney 6U2 82810-DC100 7,8,9U14 82801AB 13,14U7 sii-dfp 24U13 82559 27U8,U9 1x16sdram 10U10 74lvc08a A,B 32U6 qst3384 25U18 93c46 27U4 74ls132 A,B 29,32U5 74lvc07a A,B,C 29,31U11 74lvc07a A,B,C 19,31VR2,VR3 lt1587ad 29VR4 lt1117_3 29VR1 ltc1753 30VR5 lt1585ad 29

311-23-1998_13:44

370-PIN SOCKET, PART 1

HD#0

HD#4

HD#9

HD#14

HD#19

HD#24

HD#29

HD#34

HD#39

HD#44

HD#49

HD#54

HD#59

HD#63

HD#62

HD#61

HD#60

HD#58

HD#57

HD#56

HD#55

HD#53

HD#52

HD#51

HD#50

HD#48

HD#47

HD#46

HD#45

HD#43

HD#42

HD#41

HD#40

HD#38

HD#37

HD#36

HD#35

HD#33

HD#32

HD#31

HD#30

HD#28

HD#27

HD#26

HD#25

HD#23

HD#22

HD#21

HD#20

HD#18

HD#17

HD#16

HD#15

HD#13

HD#12

HD#11

HD#10

HD#8

HD#7

HD#6

HD#5

HD#3

HD#2

HD#1

5,7HD#[63:0]

HREQ#0HREQ#[4:0]

7

HREQ#3

HREQ#1

HREQ#2

HREQ#4

RS#0

RS#2

7RS#[2:0]

RS#1

VID[3:0]30VID0

VID3

VID2

VID1

HA#31

HA#26

HA#21

HA#16

HA#11

HA#6

HA#5

HA#7

HA#8

HA#9

HA#10

HA#12

HA#13

HA#14

HA#15

HA#17

HA#18

HA#19

HA#20

HA#22

HA#23

HA#24

HA#25

HA#27

HA#28

HA#29

5,7HA#[31:3]

HA#4

HA#3

HA#30

X2

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF 40

1.3

PROJECT:INTEL(R) 810

CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

VCCVID

AM

2G

ND

1

D2

GN

D10

GN

D11

AL3

AK

4G

ND

12

GN

D13

AG

5

AC

5G

ND

14

GN

D15

Y5

U5

GN

D16

GN

D17

Q5

L5G

ND

18

GN

D19

G5

AM

34G

ND

2

D4

GN

D20

GN

D21

B4

AM

6G

ND

22

GN

D23

AJ7 E

7G

ND

24

GN

D25

B8

AM

10G

ND

26

GN

D27

AJ1

1

E11

GN

D28

GN

D29

B12

GN

D3

AH

2

AM

14G

ND

30

GN

D31

AJ1

5

E15

GN

D32

GN

D33

B16

AM

18G

ND

34

GN

D35

AJ1

9

E19

GN

D36

GN

D37

F20

B20

GN

D38

GN

D39

AM

22

AD

2G

ND

4

AJ2

3G

ND

40

GN

D41

D22

F24

GN

D42

GN

D43

B24

AM

26G

ND

44

GN

D45

AJ2

7

D26

GN

D46

GN

D47

F28

B28

GN

D48

GN

D49

AM

30

GN

D5

Z2

D30

GN

D50

V2

GN

D6

GN

D7

M2

D18

GN

D8

GN

D9

H2

HA#10AH6

AK10HA#11

HA#12AN5

AL7HA#13

HA#14AK14

HA#15AL5

AN7HA#16

HA#17AE1

Z6HA#18

HA#19AG3

AC3HA#20

HA#21AJ1

AE3HA#22

HA#23AB6

HA#24AB4

AF6HA#25

HA#26Y3

AA1HA#27

HA#28AK6

Z4HA#29

AK8HA#3

HA#30AA3

HA#31AD4

HA#4AH12

AH8HA#5

HA#6AN9

AL15HA#7

HA#8AH10

AL9HA#9

W1HD#0

HD#1T4

Q3HD#10

HD#11M4

Q1HD#12

HD#13L1

HD#14N3

HD#15U3

H4HD#16

HD#17R4

P4HD#18

HD#19H6

N1HD#2

L3HD#20

HD#21G1

F8HD#22

G3HD#23

K6HD#24

HD#25E3

E1HD#26

HD#27F12

HD#28A5

A3HD#29

HD#3M6

HD#30J3

HD#31C5

HD#32F6

C1HD#33

HD#34C7

B2HD#35

C9HD#36

HD#37A9

D8HD#38

D10HD#39

U1HD#4

C15HD#40

HD#41D14

D12HD#42

HD#43A7

A11HD#44

HD#45C11

A21HD#46

A15HD#47

A17HD#48

HD#49C13

HD#5S3

C25HD#50

HD#51A13

D16HD#52

HD#53A23

C21HD#54

C19HD#55

C27HD#56

HD#57A19

C23HD#58

HD#59C17

T6HD#6

A25HD#60

HD#61A27

E25HD#62

F16HD#63

J1HD#7

S1HD#8

HD#9P6

AK18REQ#0

REQ#1AH16

AH18REQ#2

REQ#3AL19

REQ#4AL17

AH26RS#0

RS#1AH22

RS#2AK28

RSRVD1AH20

RSRVD10AF4

AK16RSRVD11

RSRVD12AK24

AK30RSRVD13

RSRVD14AL11

AL13RSRVD15

RSRVD16AL21

AN11RSRVD17

RSRVD18AN13

RSRVD2AH4

A29RSRVD3

RSRVD4A31

A33RSRVD5

RSRVD6AA33

AA35RSRVD7

RSRVD8AC1

AC37RSRVD9

B26

VC

C1

E5

VC

C10

VC

C11

AM

4

AE

5V

CC

12

VC

C13

AA

5

W5

VC

C14

VC

C15

S5

N5

VC

C16

VC

C17

J5 F2

VC

C18

VC

C19

AJ5

C3

VC

C2

D6

VC

C20

VC

C21

B6

AM

8V

CC

22

VC

C23

AJ9

E9

VC

C24

VC

C25

B10

AM

12V

CC

26

VC

C27

AJ1

3

E13

VC

C28

VC

C29

B14

VC

C3

AK

2

AM

16V

CC

30

VC

C31

AJ1

7

E17

VC

C32

VC

C33

B18

AM

20V

CC

34

VC

C35

AJ2

1

D20

VC

C36

VC

C37

F22

AM

24V

CC

38

VC

C39

AJ2

5

AF

2V

CC

4

D24

VC

C40

VC

C41

F26

AM

28V

CC

42

VC

C43

AJ2

9

D28

VC

C44

VC

C45

AK

34

F30

VC

C46

VC

C47

B30

AM

32V

CC

48

VC

C49

AH

32

VC

C5

AB

2

VC

C50

Z32

V32

VC

C51

VC

C52

R32

T2

VC

C6

VC

C7

P2

K2

VC

C8

VC

C9

F4

VID0AL35

AM36VID1

VID2AL37

VID3AJ37

Z32

B26

AM

2

W1

AA1

AJ37

AL37

AM36

AL35

AK28

AH22

AH26

AL17

AL19

AH18

AH16

AK18

P6

S1

J1

F16

E25

A27

A25

T6

C17

C23

A19

C27

C19

C21

A23

D16

A13

C25

S3

C13

A17

A15

A21

C11

A11

A7

D12

D14

C15

U1

D10

D8

A9

C9

B2

C7

C1

F6

C5

J3

M6

A3

A5

F12

E1

E3

K6

G3

F8

G1

L3

N1

H6

P4

R4

H4

U3

N3

L1

Q1

M4

Q3

T4

AL9

AH10

AL15

AN9

AH8

AH12

AD4

AA3

AK8

Z4

AK6

Y3

AF6

AB4

AB6

AE3

AJ1

AC3

AG3

Z6

AE1

AN7

AL5

AK14

AL7

AN5

AK10

AH6

AM

34

AH

2

AD

2

Z2

V2

M2

D18 H

2

D2

AL3

AK

4

AG

5

AC

5

Y5

U5

Q5

L5 G5

D4

B4

AM

6

AJ7 E

7

B8

AM

10

AJ1

1

E11

B12

AM

14

AJ1

5

E15

B16

AM

18

AJ1

9

E19

F20

B20

AM

22

AJ2

3

D22

F24

B24

AM

26

AJ2

7

D26

F28

B28

AM

30

D30

C3

AK

2

AF

2

AB

2

T2

P2

K2

F4

E5

AM

4

AE

5

AA

5

W5

S5

N5

J5 F2

AJ5

D6

B6

AM

8

AJ9

E9

B10

AM

12

AJ1

3

E13

B14

AM

16

AJ1

7

E17

B18

AM

20

AJ2

1

D20

F22

AM

24

AJ2

5

D24

F26

AM

28

AJ2

9

D28

AK

34

F30

B30

AM

32

AH

32

V32

R32

Part 1

370-Pin Socket

Part 1370PGA Socket

45-26-1999_17:09

370-PIN SOCKET, PART 2

SLEWCTRL33

33RTTCTRL

6 CPUHCLK

6,9FREQSEL

C204

0.1UF

5,7HADS#

TDI

VC

MO

S

4,33

4,33

VC

MO

S

13,33IGNNE#

13,15,33INIT#13,33NMI13,33INTR13,33

SMI#13,33CPUSLP#13,33STPCLK#13,33A20M#

5,7DBSY#5,7HIT#

5,7DRDY#5,7HLOCK#5,7DEFER#5,7HTRDY#

APICD013,33APICD1

13,33APICCLK_CPU6

32 PWRGOOD

5,7BPRI#5,7BNR#

J2

R7

150

ITP_PON TDO

4 R_TCK

4 R_TMS

6 ITPCLK

5,7HITM#

JP1

4,5 ITPRDY#

32 DBRESET#

0K

R2240

R1ITP_RST

R8

1K

R21

240

ITPRDY# 4,5

47R3

R447

4,5,7 CPURST#

680

R5

FERR# 13,33

75

1%

R102

150

1%

R104

4

GT

LRE

F

C206

0.1UF 0.1UF

C209

0.1UF

C207

4,33VCMOS

4GTLREF

5BR0#

C123

20%33UF

X2

TRST#

ITPREQ#

TCK

TMS

R_ITPRDY#

PLL1

EDGCTRL

PLL2

R_DBRST#

RP2

330

4 R_TCK

4 R_TMS

4,33

VC

MO

S

4.7UH

L22

220

R9

R171

220

C6

0.1UF

4,5,7 CPURST#

51

R76

18PF

C114

VCOREDET 9

VCCVID

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF 40

1.3

PROJECT:INTEL(R) 810

CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

VCCVID

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29 30

4

5 6

7 8

9

3

11

3

9

87

65

4

3029

2827

2625

2423

2221

20

2

19

1817

1615

1413

1211

10

VCC2_5

VTT1_5

VTT1_5

VTT1_5

+2 1

A20M#AE33

ADS#AN31

BCLKW37

AH14BNR#

G33BP2#

E37BP3#

BPM0#C35

BPM1#E35

BPRI#AN17

AN29BR0#

BSEL#AJ33

C37CPUPRES#

DBSY#AL27

DEFER#AN19

DRDY#AN27

AG1EDGCTRL

AC35FERR#

AE37FLUSH#

GN

D51

AF

32

AB

32G

ND

52

GN

D53

X32

T32

GN

D54

GN

D55

P32

F32

GN

D56

GN

D57

B32

AH

34G

ND

58

GN

D59

AD

34

Z34

GN

D60

GN

D61

V34

R34

GN

D62

GN

D63

M34

H34

GN

D64

GN

D65

D34

AK

36G

ND

66

GN

D67

AF

36

X36

GN

D68

GN

D69

T36

P36

GN

D70

GN

D71

K36

F36

GN

D72

A37

GN

D73

GN

D74

AC

33

AJ3

GN

D75

GN

D76

AL1

AN

3G

ND

77

GN

D78

Y37

AJ3

1G

ND

79Y

33G

ND

80

HIT#AL25

HITM#AL23

AE35IERR#

AG37IGNNE#

AG33INIT#

LINT0/INTRM36

LINT1/NMIL37

LOCK#AK20

J33PICCLK

J35PICD0

L35PICD1

W33PLL1

U33PLL2

PRDY#A35

PREQ#J37

AK26PWRGOOD

X4RESET#

RSRVD19AN15

RSRVD20AN21

AN23RSRVD21

RSRVD22B36

C29RSRVD23

RSRVD24C31

C33RSRVD25

RSRVD26E23

E29RSRVD27

RSRVD28E31

F10RSRVD29

RSRVD30G35

G37RSRVD31

RSRVD32L33

N33RSRVD33

N35RSRVD34

RSRVD35N37

Q33RSRVD36

RSRVD37Q35

Q37RSRVD38

RSRVD39S33

RSRVD40S37

RSRVD41U35

U37RSRVD42

RSRVD43V4

W3RSRVD44

RSRVD45W35

X6RSRVD46

RSRVD47Y1

E21RSRVD48

RSRVD49E27

R2RSRVD50

X2RSRVD52

SLP#AH30

SMI#AJ35

STPCLK#AG35

TCKAL33

AN35TDI

TDOAN37

THERMTRIP#AH28

THRMDNAL29

AL31THRMDP

TMSAK32

TRDY#AN25AN33

TRST#

V1_

5A

D36

V2_

5Z

36

VC

C53

M32

H32

VC

C54

VC

C55

AF

34

AB

34V

CC

56

VC

C57

X34

T34

VC

C58

VC

C59

P34

K34

VC

C60

VC

C61

F34

B34

VC

C62

VC

C63

AH

36

B22

VC

C64

VC

C65

V36

R36

VC

C66

VC

C67

H36

D36

VC

C68

VC

C69

D32

AD

32V

CC

70A

H24

VC

C71

VC

C72

F14

K32

VC

C73

VC

C74

AA

37

VR

EF

0E

33

VR

EF

1F

18

VR

EF

2K

4

R6

VR

EF

3

VR

EF

4V

6

VR

EF

5A

D6

VR

EF

6A

K12

VR

EF

7A

K22

V_C

MO

SA

B36

VC

C75

Y35

RSRVD51S35

AB

36

AK

22

AK

12

AD

6

V6

R6

K4

F18

E33

Y35

AA

37

K32

F14

AH

24

AD

32

D32

D36

H36

R36

V36

B22

AH

36

B34

F34

K34

P34

T34

X34

AB

34

AF

34

H32

M32

Z36

AD

36

AN33 AN25

AK32

AL31

AL29

AH28

AN37

AN35

AL33

AG35

AJ35

AH30

X2

S35

R2

E27

E21

Y1

X6

W35

W3

V4

U37

U35

S37

S33

Q37

Q35

Q33

N37

N35

N33

L33

G37

G35

F10

E31

E29

E23

C33

C31

C29

B36

AN23

AN21

AN15

X4

AK26

J37

A35

U33

W33

L35

J35

J33

AK20

L37

M36

AG33

AG37

AE35

AL23

AL25

Y33

AJ3

1

Y37

AN

3

AL1

AJ3

AC

33

A37

F36

K36

P36

T36

X36

AF

36

AK

36

D34

H34

M34

R34

V34

Z34

AD

34

AH

34

B32

F32

P32

T32

X32

AB

32

AF

32

AE37

AC35

AG1

AN27

AN19

AL27

C37

W37

AJ33

AN29

AN17

E35

C35

E37

G33

AH14

AN31

AE33

1 2 3 456788 7 6 5

4321

VCC2_5

VCC3_3

VCCVID

Part 2

370-Pin Socket

ITP Test Port Option

Part 2

GTLREF Inputs (1 cap for every 2 inputs).

Use 0603 Packages and distributewithin 500 mils of Mendocino

GTLREF Generation Circuit

Place 0603 PackageNear VCMOS Processor Pin.

VCMOS Decoupling

370PGA Socket

Place Site w/in 0.5"of clock pin (W37).

Do Not Stuff C114

JP1 is a Test Option Only.

511-23-1998_13:44

GTL TERMINATION

4,7HTRDY#

3,7HREQ#3

4,7HADS#

BNR# 4,7

HA#29

HA#26

HA#27

HA#28

HA#25

HA#24

HA#23

HA#22

HA#21

HA#20

HA#19

HA#17

HA#16

HA#15

HA#11

HA#[31:3]3,7

HA#18

HA#14

HA#10

HA#13

HA#12

HA#3

HA#30

HA#31

HA#4

HA#5

HA#6

HA#7

HA#8

HA#9

56

RP21

4,7HIT#

4,7DEFER#

BPRI# 4,7

ITPRDY# 4

RP19

56

RP18

56

RP8

56

56

RP20

56

RP12

RP7

56

56

RP11

56

RP10

56

RP5

56

RP9

RP35

56

RP24

56

56

RP26

56

RP25

RP43

56

RP41

56

RP42

56

RP40

56

56

RP37

56

RP39

RP36

56

RP32

56

RP38

56

38

RP23

56

56

RP3

56

RP6

4BR0#

4,7DBSY#

DRDY# 4,7

RP33

56

4,7CPURST#

56

RP22

4,7HITM#

4,7HLOCK#

HREQ#03,7

3,7HREQ#1

HREQ#2 3,7

HREQ#4 3,7

RS#0 3,7

3,7RS#1 HD#40

HD#56

HD#61

HD#62

HD#46

HD#60

HD#50

HD#53

HD#58

HD#57

HD#63

HD#59

HD#48

HD#47

HD#27

HD#44

HD#45

HD#49

HD#51

HD#41

HD#42

HD#36

HD#22

HD#43

HD#34

HD#39

HD#37

HD#38

HD#28

HD#52

HD#55

HD#54HD#[63:0]

3,7HD#15

HD#33

HD#35

HD#19

HD#29

HD#26

HD#25

HD#32

HD#31

HD#2

HD#14

HD#18

HD#13

HD#20

HD#11

HD#7

HD#30

HD#17

HD#10

HD#12

HD#3

HD#24

HD#21

HD#16

HD#4

HD#9

HD#5

HD#8

HD#1

HD#0

HD#6

HD#23

RS#2 3,7

1

2

3

4 5

6

7

88

7

6

54

3

2

1

VTT1_5VTT1_5VTT1_5VTT1_5

1

2

3

4 5

6

7

88

7

6

54

3

2

1

1

2

3

4 5

6

7

88

7

6

54

3

2

1

1

2

3

4 5

6

7

88

7

6

54

3

2

1

1

2

3

4 5

6

7

88

7

6

54

3

2

1

1

2

3

4 5

6

7

88

7

6

54

3

2

1

1

2

3

4 5

6

7

88

7

6

54

3

2

1

1

2

3

4 5

6

7

88

7

6

54

3

2

1

1

2

3

4 5

6

7

88

7

6

54

3

2

1

1

2

3

4 5

6

7

88

7

6

54

3

2

1

1

2

3

4 5

6

7

88

7

6

54

3

2

1

1

2

3

4 5

6

7

88

7

6

54

3

2

1

1

2

3

4 5

6

7

88

7

6

54

3

2

1

1

2

3

4 5

6

7

88

7

6

54

3

2

1

1

2

3

4 5

6

7

88

7

6

54

3

2

1

1

2

3

4 5

6

7

88

7

6

54

3

2

1

1

2

3

4 5

6

7

88

7

6

54

3

2

1 1

2

3

4 5

6

7

88

7

6

54

3

2

1

1

2

3

4 5

6

7

88

7

6

54

3

2

1

1

2

3

4 5

6

7

88

7

6

54

3

2

1

1

2

3

4 5

6

7

88

7

6

54

3

2

1

1

2

3

4 5

6

7

88

7

6

54

3

2

1

1

2

3

4 5

6

7

88

7

6

54

3

2

1

1

2

3

4 5

6

7

88

7

6

54

3

2

1

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF

1.3

PROJECT:INTEL(R) 810

CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

1

2

3

4 5

6

7

88

7

6

54

3

2

1

1

2

3

4 5

6

7

88

7

6

54

3

2

1

1

2

3

4 5

6

7

88

7

6

54

3

2

1

1

2

3

4 5

6

7

88

7

6

54

3

2

1

1

2

3

4 5

6

7

88

7

6

54

3

2

1

GTL Termination

6

CLOCK SYNTHESIZER

12-8-1998_13:05

0.1UF

C387

MEMV3

.001UF

C385

PCIV3

SIO_CLK1416

L13 L16

R23

10K

C64

.001UF

C61

0.1UF

R41

8.2K

R4433R52

33 R4533

33R53

R4722

33R51

33R46

33R50

R4333

JP6

4ITPCLK7GMCHHCLK4CPUHCLK

13APICCLK_ICH4APICCLK_CPU

16 PCLK_1

17 PCLK_2

17 PCLK_3

PCLK_418

14 ICH_3V66 MEMCLK0

MEMCLK1

MEMCLK2

MEMCLK3

MEMCLK4

MEMCLK5

MEMCLK6

MEMCLK7

11,12MEMCLK[7:0]

27 PCLK_5

9 DOTCLK14 USBCLK

15 PCLK_6 8DCLK_WR

13PCLK_0/ICH

4,9FREQSEL

Y1

14.318MHZ

0.1UF

C50

.001UF

C60

C55

22UF

C51

12PF

0.1UF

C38

C52

0.1UF

C37

.001UF

.001UF

C53

22UF

C48

C46

.001UF 0.1UF

C47

4.7UF

C56

L17

R4222

R3622R27

22

22R37

22R28

22R38

R2922

22R39

R3022

ICH_CLK1414 R4810

R18410

REFCLK

L18

22UF

C158

L15

R2533

R3233 R35

33

33R26

33R34

C49

12PF

L_VCC2_5

XTAL_IN

XTAL_OUT

DCLK

USB_1

USB_0

3V66_0

3V66_1

PCI_0

PCI_1

PCI_2

PCI_3

PCI_4

PCI_5

PCI_6

DRAM_7

DRAM_6

DRAM_5

DRAM_4

DRAM_3

DRAM_2

DRAM_1

DRAM_0

CPU_2

CPU_0_1

APIC_1

APIC_0

SE

L1_P

U

L_CKVDDA

USBV3

JP1

U1

R4022

25CK_SMBCLK

25CK_SMBDATA

8 GMCH_3V66 R4922

CK_PWRDN# 32

C39

0.1UF

C40

.001UF

C386

0.1UF

C388

.001UF 0.1UF

C63

1 2 1 2

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF 40

1.3

PROJECT:INTEL(R) 810

CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

VCC3_3VCC3_3

XT

AL

21

VCC3_3

+2

1

+1

2

+2

1

1 2

12

VCC3_3

+1

2

VCC2_5

12

7 3V66_0

3V66_18

APIC_0 55

54APIC_1

CPU_0 52

50CPU_1

CPU_2/ITP 49

11PCI_0/ICH

PCI_112

13 PCI_2

PCI_315

16 PCI_4

PCI_518

PCI_619

PCI_720

REF01

31SCLK

SDATA 30

46SDRAM_0

SDRAM_145

43SDRAM_2

SDRAM_342

40SDRAM_4

SDRAM_5 39

37SDRAM_6

SDRAM_7 36

28SEL0

29SEL1

USB_025

USB_126

VDD2_5[0] 51

VDD2_5[1]53

VD

D3_

3[0]

2 9V

DD

3_3[

1]

VD

D3_

3[2]

10 21V

DD

3_3[

3]

VD

D3_

3[4]

27 33V

DD

3_3[

5]

VD

D3_

3[6]

38 44V

DD

3_3[

7]

VDD_A22

48VSS2_5[0]

56VSS2_5[1]

5V

SS

3_3[

0]

VS

S3_

3[1]

6 14V

SS

3_3[

2]

VS

S3_

3[3]

17 24V

SS

3_3[

4]

VS

S3_

3[5]

35 41V

SS

3_3[

6]

VS

S3_

3[7]

47

VSS_A23

3 XTAL_IN

XTAL_OUT4

34DCLK

PWRDWN# 32

CPU

APIC

USB

REF

3V66

PCI

Memory

ICS9250-10CK-Whitney

51

53

56

48

23

22

28

29

30

31

32

34

36

37

39

40

42

43

45

46

49

50

52

54

55

47413524171465

44383327211092

26

25

19

20

18

16

15

13

12

11

8

7

4

3

1

Clock Synthesizer

- Place all decoupling caps as close to VCC/GND pins as possible

Notes:

Minimize Stub Length from

- PCI_0/ICH pin has to go to the ICH.

- CPU_ITP pin has to go to the ITP. It is the onlyCPU CLK that can be shut off through the SMBUS interface.

(This clock cannot be turned off through SMBus)

CLK14 trace to JP6.

APIC Clk Strap JP616MHz in33MHz out*

711-23-1998_13:44

82810-DC100 : HOST INTERFACE

6 GMCHHCLK

18PF

C161

R80

1%

75

R81

1%

150

13,17,18,24,27 PCIRST#

4,5 CPURST#

HLOCK#4,5

4,5 DEFER#

HADS#4,5

4,5 BNR#

BPRI#4,5

4,5 DBSY#

4,5 DRDY#

4,5HIT#

4,5 HITM#

4,5 HTRDY#

3,5HA#[31:3]

HA#3

HA#4

HA#5

HA#6

HA#7

HA#8

HA#9

HA#10

HA#11

HA#12

HA#13

HA#14

HA#15

HA#16

HA#17

HA#18

HA#19

HA#20

HA#21

HA#22

HA#23

HA#24

HA#25

HA#26

HA#27

HA#28

HA#29

HA#30

HA#31

HREQ#4

HREQ#0

HREQ#1

HREQ#2

HREQ#3

3HREQ#[4:0]

3RS#[2:0]

RS#2

RS#1

RS#0

HD#0

HD#1

HD#2

HD#3

HD#4

HD#5

HD#6

HD#7

HD#8

HD#9

HD#10

HD#11

HD#12

HD#13

HD#14

HD#15

HD#16

HD#17

HD#18

HD#19

HD#20

HD#21

HD#22

HD#23

HD#24

HD#25

HD#26

HD#27

HD#28

HD#29

HD#30

HD#31

HD#32

HD#33

HD#34

HD#35

HD#36

HD#37

HD#38

HD#39

HD#40

HD#41

HD#42

HD#43

HD#44

HD#45

HD#46

HD#47

HD#48

HD#49

HD#50

HD#51

HD#52

HD#53

HD#54

HD#55

HD#56

HD#57

HD#58

HD#59

HD#60

HD#61

HD#62

HD#63

3,5HD#[63:0]

0.1UF

C166 C167

.001UF

GMCHGTLREF

U2

VCC1_8

VTT1_5

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF 40

1.3

PROJECT:INTEL(R) 810

CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

HOST INTERFACE

PART1

N3 ADS#T3 BNR#T1 BPRI#M4 DBSY#

R3 DEFER#

N1 DRDY#

M5 GTLREFAW13 GTLREFB

W1 HA10#U4 HA11#

W3 HA12#W4 HA13#T5 HA14#

W2 HA15#V2 HA16#

AC2 HA17#AA2 HA18#

Y3 HA19#AB3 HA20#AA1 HA21#AB2 HA22#AC3 HA23#AA3 HA24#

Y2 HA25#AB5 HA26#AC4 HA27#

Y1 HA28#AC5 HA29#

U5 HA3#

Y4 HA30#AB1 HA31#

U1 HA4#V4 HA5#V1 HA6#T4 HA7#U2 HA8#U3 HA9#

Y5HD0#W5HD1#

AB7HD10#AC8HD11#AA7HD12#Y8HD13#W7HD14#AC6HD15#W9HD16#AC9HD17#Y7HD18#AA10HD19#

W8HD2#

AB8HD20#AC10HD21#AB13HD22#AB10HD23#AB9HD24#AB11HD25#Y10HD26#AB16HD27#AB12HD28#Y11HD29#

AA6HD3#

Y9HD30#AC12HD31#W11HD32#AC11HD33#W12HD34#AA11HD35#AA13HD36#Y13HD37#Y12HD38#AC14HD39#

AB6HD4#

AA15HD40#AC15HD41#Y14HD42#AC13HD43#AA14HD44#AB14HD45#Y17HD46#Y15HD47#AC17HD48#AC16HD49#

Y6HD5#

AA18HD50#AB15HD51#W15HD52#AB18HD53#W17HD54#AA17HD55#W18HD56#W16HD57#AC19HD58#Y16HD59#

AA5HD6#

AB19HD60#Y18HD61#AC18HD62#AB17HD63#

AA9HD7#V5HD8#AC7HD9#

HIT#P1

HITM#R1

R4 HREQ0#T2 HREQ1#P4 HREQ2#R2 HREQ3#R5 HREQ4#

HTRDY#N4

M2 RESETB

N5 RS0#P2 RS1#N2 RS2#

VC

C1_

8[0]

B20

VC

C1_

8[1]

P6

V17

VC

C_C

OR

E[0

]

F14

VC

C_C

OR

E[1

0]

VC

C_C

OR

E[1

1]F

10

F8

VC

C_C

OR

E[1

2]

VC

C_C

OR

E[1

3]F

7

VC

C_C

OR

E[1

]V

16

V15

VC

C_C

OR

E[2

]

VC

C_C

OR

E[3

]V

14

V10

VC

C_C

OR

E[4

]

VC

C_C

OR

E[5

]V

9

V8

VC

C_C

OR

E[6

]

VC

C_C

OR

E[7

]V

7

F17

VC

C_C

OR

E[8

]

VC

C_C

OR

E[9

]F

16

Y22

VS

S[0

]

K11

VS

S[1

0]

VS

S[1

1]K

10

L14

VS

S[1

2]

VS

S[1

3]L1

3

L12

VS

S[1

4]

VS

S[1

5]L1

1

L10

VS

S[1

6]

VS

S[1

7]M

14

M13

VS

S[1

8]

VS

S[1

9]M

12

V18

VS

S[1

]

M11

VS

S[2

0]

VS

S[2

1]M

10

N14

VS

S[2

2]N

13V

SS

[23]

N22

VS

S[2

]

VS

S[3

]J2

2

Y19

VS

S[4

]

VS

S[5

]C

19

E22

VS

S[6

]

VS

S[7

]K

14

K13

VS

S[8

]

VS

S[9

]K

12

V6 HTCLK

U18

VC

C1_

8[2]

AB4 CPURST#P5 HLOCK#

INTEL 82810-DC100

P5

AB4

U18

V6

K12

K13

K14

E22

C19

Y19J22

N22

N13

N14

M10

M11

V18

M12

M13

M14L10

L11

L12

L13

L14

K10

K11

Y22

F16

F17

V7

V8

V9

V10

V14

V15

V16

F7

F8

F10

F14

V17

P6

B20

N2

P2

N5

M2

N4

R5

R2

P4

T2

R4

R1

P1

AC7

V5

AA9

AB17

AC18

Y18

AB19

AA5

Y16

AC19

W16

W18

AA17

W17

AB18

W15

AB15

AA18

Y6

AC16

AC17

Y15

Y17

AB14

AA14

AC13

Y14

AC15

AA15

AB6

AC14

Y12

Y13

AA13

AA11

W12

AC11

W11

AC12

Y9

AA6

Y11

AB12

AB16

Y10

AB11

AB9

AB10

AB13

AC10

AB8

W8

AA10

Y7

AC9

W9

AC6

W7

Y8

AA7

AC8

AB7

W5

Y5

U3

U2

T4

V1

V4

U1

AB1

Y4

U5

AC5

Y1

AC4

AB5

Y2

AA3

AC3

AB2

AA1

AB3

Y3

AA2

AC2

V2

W2

T5

W4

W3

U4

W1

W13

M5

N1

R3

M4

T1

T3

N3

Place Site w/in 0.5"of clock ball (V6).

Do Not Stuff C161

82810-DC100, PART 1: HOST INTERFACE

85-26-1999_17:13

82810-DC100: SYSTEM MEMORY AND HUB

SM_MAA3

SM_MAA4

SM_MAA0SM_MAA[11:0]

11,12SM_MAA1

SM_MAA2

SM_MAA11

SM_MAA10

SM_MAA9

SM_MAA8

SM_MAA7

SM_MAA6

SM_MAA5

R_MAA7

R_MAA6

R_MAA5

R_MAA4

SM_MAB4#

SM_MAB5#

SM_MAB6#

SM_MAB7#

12SM_MAB[7:4]#

SM_MD22

SM_MD11

11,12SM_MD[63:0]

SM_MD35

SM_MD28

SM_MD0

SM_MD63

SM_MD62

SM_MD61

SM_MD60

SM_MD59

SM_MD58

SM_MD57

SM_MD56

SM_MD55

SM_MD54

SM_MD53

SM_MD52

SM_MD51

SM_MD50

SM_MD49

SM_MD48

SM_MD47

SM_MD46

SM_MD45

SM_MD44

SM_MD43

SM_MD42

SM_MD41

SM_MD40

SM_MD39

SM_MD38

SM_MD37

SM_MD36

SM_MD34

SM_MD33

SM_MD32

SM_MD31

SM_MD30

SM_MD29

SM_MD27

SM_MD26

SM_MD25

SM_MD24

SM_MD23

SM_MD21

SM_MD20

SM_MD19

SM_MD18

SM_MD17

SM_MD16

SM_MD15

SM_MD14

SM_MD13

SM_MD12

SM_MD10

SM_MD9

SM_MD8

SM_MD7

SM_MD6

SM_MD5

SM_MD4

SM_MD3

SM_MD2

SM_MD1

56R177

R17656

8,13HUBREF

C299

470PF

SM_DQM7

SM_DQM6

SM_DQM5

SM_DQM4

SM_DQM3

SM_DQM2

SM_DQM1

SM_DQM0SM_DQM[7:0]

11,12

SM_BS0

SM_BS111,12

SM_BS[1:0]

SM_CS#3

SM_CS#[3:0]11,12

SM_CS#2

SM_CS#1

SM_CS#0

SM_RAS#11,12SM_CAS#11,12SM_WE#11,12

SM_CKE1

SM_CKE[1:0]11,12 SM_CKE0

SCLK

GHCOMP

R82

1%40

C241

0.1UF

C168

22PF

6 DCLK_WRR31

0K

HL[10:0]13

HL10

HL9

HL8

HL7

HL6

HL5

HL4

HL3

HL1

HL2

HL0

HLSTB8,13

HLSTB#8,13

6,8 GMCH_3V66

HUBREF

18PF

C236

C300

470PF

R1313011%

1%301R130

HUBREF_CV

HUBREF_CG

U2

R_MAB#6

R_MAB#7

R_MAB#5

R_MAB#4

10 OHMSRP70

10 OHMSRP71

VCC3_3

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF 40

1.3

PROJECT:INTEL(R) 810

CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

VCC1_8 VCC3SBY

VCC1_8

AND

HUB I/F

PART 2

SYSTEM MEMORY

HUB INTERFACE

INTEL 82810-DC100

D18 HCOMP

C21 HL0B23 HL1

A19 HL10

B22 HL2A23 HL3B19 HL4B18 HL5C18 HL6A18 HL7A22 HL8C20 HL9

D19 HLCLK

A21 HLSTBA20 HLSTB#

D20 HUBREF

C5 SBS0

A11 SCAS#

A3 SCKE0A2 SCKE1E6 SCLK

C4 SCS0#C3 SCS1#B3 SCS2#C2 SCS3#

C10 SDQM0A10 SDQM1B1 SDQM2D1 SDQM3

B10 SDQM4D9 SDQM5C1 SDQM6D2 SDQM7

C9 SMAA0E7 SMAA1

D5 SMAA10A5 SMAA11

A9 SMAA2D7 SMAA3B8 SMAA4A8 SMAA5B7 SMAA6A7 SMAA7D6 SMAA8C6 SMAA9

B6 SMAB4#A6 SMAB5#B4 SMAB6#A4 SMAB7#

E17SMD0C16SMD1

B14SMD10A14SMD11D13SMD12C13SMD13A13SMD14A12SMD15E1SMD16F2SMD17G4SMD18G1SMD19

D15SMD2

D3SMD20H2SMD21H1SMD22J4SMD23J1SMD24K2SMD25K1SMD26K3SMD27L1SMD28L2SMD29

D17SMD3

M3SMD30K4SMD31D16SMD32E15SMD33D14SMD34E14SMD35E13SMD36E12SMD37D12SMD38B15SMD39

C17SMD4

B12SMD40C12SMD41D11SMD42D10SMD43E10SMD44E9SMD45E8SMD46C8SMD47F3SMD48F1SMD49

A17SMD5

G2SMD50H3SMD51E4SMD52E3SMD53F4SMD54J3SMD55F5SMD56G5SMD57H5SMD58H4SMD59

A16SMD6

H6SMD60J5SMD61K5SMD62L5SMD63

B16SMD7A15SMD8C14SMD9

D8 SRAS#

B11 SWE#

VC

C3_

3[0]

D4

VC

C3_

3[10

]B

2

L21

VC

C3_

3[11

]

F18

VC

C3_

3[13

]

VC

C3_

3[14

]J1

8

R18

VC

C3_

3[15

]

C11

VC

C3_

3[1]

VC

C3_

3[2]

C7

C15

VC

C3_

3[3]

VC

C3_

3[4]

L3 G3

VC

C3_

3[5]

VC

C3_

3[6]

F15

F9

VC

C3_

3[7]

VC

C3_

3[8]

K6

F6

VC

C3_

3[9]

N12

VS

S[2

4]N

11V

SS

[25]

VS

S[2

6]N

10

P14

VS

S[2

7]

VS

S[2

8]P

13

P12

VS

S[2

9]

VS

S[3

0]P

11

P10

VS

S[3

1]

VS

S[3

2]A

C1

AA

4V

SS

[33]

VS

S[3

4]A

A8

AA

12V

SS

[35]

VS

S[3

6]A

A16 W6

VS

S[3

7]

VS

S[3

8]W

10

W14

VS

S[3

9]

VS

S[4

0]V

3

R6

VS

S[4

1]

VS

S[4

2]P

3

M1

VS

S[4

3]

VS

S[4

4]L4

VS

S[4

5]J2

E5 SBS1

VC

C3_

3[12

]G

21G

21

E5

J2L4M1

P3

R6

V3

W14

W10W6

AA

16

AA

12

AA

8

AA

4

AC

1

P10

P11

P12

P13

P14

N10

N11

N12

F6

K6

F9

F15

G3

L3C15

C7

C11

R18

J18

F18

L21

B2

D4

B11

D8

C14

A15

B16

L5

K5

J5

H6

A16

H4

H5

G5

F5

J3

F4

E3

E4

H3

G2

A17

F1

F3

C8

E8

E9

E10

D10

D11

C12

B12

C17

B15

D12

E12

E13

E14

D14

E15

D16

K4

M3

D17

L2

L1

K3

K1

K2

J1

J4

H1

H2

D3

D15

G1

G4

F2

E1

A12

A13

C13

D13

A14

B14

C16

E17

A4

B4

A6

B6

C6

D6

A7

B7

A8

B8

D7

A9

A5

D5

E7

C9

D2

C1

D9

B10

D1

B1

A10

C10

C2

B3

C3

C4

E6

A2

A3

A11

C5

D20

A20

A21

D19

C20

A22

A18

C18

B18

B19

A23

B22

A19

B23

C21

D18

1

2

3

45

6

7

88

7

6

5 4

3

2

1

1

2

3

45

6

7

88

7

6

5 4

3

2

1

AND HUB INTERFACE

as possible to GMCH

Circuit in middle ofGMCH and ICH.

Place HUBREF Generation

Place C241 as close

82810-DC100 PART 2: SYSTEM MEMORYPlace Resistor as Close

as possible to GMCH

RP70 and RP71 should be placedwithin 0.5" of the GMCH balls.

95-26-1999_17:09

82810-DC100: DISPLAY CACHE AND VIDEO

GR

S_P

U31

9,10DC_MD29

18PF

C379

25VID_BLUE25VID_GREEN25VID_RED25CRT_HSYNC

CRT_VSYNC 25

IREFPD

3VDDCCL 25

3VDDCDA 25

3VFTSDA 24,25

3VFTSCL 24,25

24FTHSYNC

FTVSYNC24

24FTCLK1

FTCLK0 24

SL_STALL 24

10 DC_CS#

DC_DQM0

DC_DQM1

DC_DQM2

DC_DQM3

DC_DQM[3:0]10

10 DC_RAS#

10 DC_CAS#

10DC_WE#

24FTBLNK#

FTD3

FTD2

FTD1

FTD0

FTD11

FTD10

FTD9

FTD8

FTD7

FTD6

FTD5

FTD4

24FTD[11:0]

DC_MA0

DC_MA1

DC_MA2

DC_MA3

DC_MA4

DC_MA5

DC_MA6

DC_MA7

DC_MA8

DC_MA9

DC_MA10

DC_MA11

10DC_MA[11:0]

DC_MD31

DC_MD30

DC_MD29

DC_MD28

DC_MD27

DC_MD26

DC_MD25

DC_MD24

DC_MD23

DC_MD22

DC_MD21

DC_MD20

DC_MD19

DC_MD18

DC_MD17

DC_MD16

DC_MD15

DC_MD14

DC_MD0

DC_MD1

DC_MD2

DC_MD3

DC_MD4

DC_MD5

DC_MD6

DC_MD7

DC_MD8

DC_MD9

DC_MD10

DC_MD11

DC_MD12

DC_MD13

10DC_MD[31:0]

R_LTCLK

RCLK

OCLK

9,10DC_MD31

10K

RP46

9,10DC_MD28

9,10DC_MD30

1%174

R125

JP14

10K

RP48

JP15

JP16

R129

33

L24

68NH-0.3A

0.1UF

C216

0.01UF

C217

C238

22PF

0K

R128

DC_CLK10

9,10DC_MD26

22

R127

DC_MD27 9,10

JP13

VCOREDET4

33U

F20

%

C222

VCCDACAG

RS

_PU

26

GR

S_P

U28

4,6 FREQSEL

GR

S_P

U30

OCLK_FB

U2

6DOTCLK

1 2 3 45678

1 2 3 45678

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF 40

1.3

PROJECT:INTEL(R) 810

CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

1 2 3 456788 7 6 5

4321

VCC1_8VCC1_8

VCC3_3

+2

1

INTERFACE

VIDEO DIGITAL OUT

GRAPHICS INTERFACE

INTERFACEDISPLAY CACHE

V19BLANK#

AC23BLUE

CLKOUT0 V21

CLKOUT1 V22

AA21DCLKREF

DDCCL W20DDCDA W19

AC22GREEN

AB20HSYNC

AA23IREF

IWASTE Y23

K20 LCAS#

L20 LCS#

P21 LDQM0R23 LDQM1C23 LDQM2F20 LDQM3

M19 LMA0P19 LMA1

M20 LMA10L19 LMA11

P20 LMA2N19 LMA3J21 LMA4H19 LMA5H20 LMA6H18 LMA7G19 LMA8F19 LMA9

M22 LMD0M21 LMD1

P23 LMD10P22 LMD11N23 LMD12N21 LMD13N20 LMD14M23 LMD15F23 LMD16E20 LMD17E21 LMD18E23 LMD19

L23 LMD2

D22 LMD20D23 LMD21D21 LMD22C22 LMD23H21 LMD24H22 LMD25H23 LMD26G20 LMD27G22 LMD28G23 LMD29

L22 LMD3

F21 LMD30F22 LMD31

K21 LMD4K23 LMD5R19 LMD6R20 LMD7R22 LMD8R21 LMD9

J23 LOCLK

K19 LRAS#

J20 LRCLK

K22 LTCLK

LTVCL T19

LTVDA T20

Y21LTVDATA0Y20LTVDATA1

LTVDATA10 T22

T21LTVDATA11

W23LTVDATA2W22LTVDATA3W21LTVDATA4V23LTVDATA5U23LTVDATA6U22LTVDATA7U21LTVDATA8

LTVDATA9 T23

J19 LWE#

AC21RED

U20TVCLKIN/SL_STALL

TVHSYNC U19TVVSYNC V20

E19

VC

CB

A

VC

CD

AA

C20

AB

23V

CC

DA

CA

1A

B21

VC

CD

AC

A2

VC

CH

AU

6

E18

VS

SB

A

VS

SD

AA

A22

VS

SD

AC

AA

B22T6

VS

SH

A

VS

S[4

6]J6 G6

VS

S[4

7]

VS

S[4

8]E

2

A1

VS

S[4

9]

VS

S[5

0]B

5

B9

VS

S[5

1]

VS

S[5

2]E

11

B13

VS

S[5

3]

VS

S[5

4]E

16

B17

VS

S[5

5]

VS

S[5

6]B

21

G18

VS

S[5

7]K

18V

SS

[58]

P18

VS

S[5

9]T

18V

SS

[60]

AA

19V

SS

[61]

AA20VSYNC

VIDEO INTERFACE

AND

DISPLAY CACHE

PART3

INTEL 82810-DC100

AA20A

A19

T18

P18

K18

G18

B21

B17

E16

B13

E11B9

B5

A1

E2

G6J6T6

AB

22

AA

22

E18

U6

AB

21

AB

23

AC

20

E19

V20

U19

U20

AC21

J19

T23

U21

U22

U23

V23

W21

W22

W23

T21

T22

Y20

Y21

T20

T19

K22

J20

K19

J23

R21

R22

R20

R19

K23

K21

F22

F21

L22

G23

G22

G20

H23

H22

H21

C22

D21

D23

D22

L23

E23

E21

E20

F23

M23

N20

N21

N23

P22

P23

M21

M22

F19

G19

H18

H20

H19

J21

N19

P20

L19

M20

P19

M19

F20

C23

R23

P21

L20

K20

Y23

AA23

AB20

AC22

W19

W20

AA21

V22

V21

AC23

V19

AND VIDEO INTERFACE

GMCH RESET STRAPS

of clock ball (AA21).Place Site w/in 0.5"

and via straight toVSS plane.

Place as close asPossible to GMCH

Do Not Populate C238

Place R129 within 0.5" of the GMCH Ball.

Do Not Stuff C379

82810-DC100, PART 3: DISPLAY CACHE

Function Jumper Function

XOR JP16IN=XOR TREE

OUT=NORMAL*

Tri-State JP15IN=TriState Mode OUT=NORMAL*

System Bus Frequency N/A

READS System Bus Frequency

IOQD JP14IN=IO Queue Depth 1

OUT=IO Queue Depth 4*VCORE Detect N/A

Detects Type of Processor I/O Buffers

RESVD JP13 TBD

1011-23-1998_13:44

DISPLAY CACHE

R114

4.7K

10 DC_CKE

DC_MA[11:0]9

DC_MA11

DC_MA0

DC_MA1

DC_MA2

DC_MA3

DC_MA4

DC_MA5

DC_MA6

DC_MA7

DC_MA8

DC_MA9

DC_MA10

DC_MA29

9 DC_MA1

DC_MA39DC_MA49DC_MA59DC_MA69DC_MA79

9DC_DQM[3:0]

DC_DQM2

DC_DQM3DC_DQM1

DC_DQM0

DC_MD[31:0]9

DC_MD16

DC_MD18

DC_MD17

DC_MD19

DC_MD20

DC_MD21

DC_MD22

DC_MD23

DC_MD24

DC_MD25

DC_MD26

DC_MD27

DC_MD28

DC_MD29

DC_MD30

DC_MD31

DC_MD0

DC_MD1

DC_MD2

DC_MD3

DC_MD4

DC_MD5

DC_MD6

DC_MD7

DC_MD8

DC_MD9

DC_MD10

DC_MD11

DC_MD12

DC_MD13

DC_MD14

DC_MD15

DC_CLK9

9DC_CAS#

9 DC_WE#DC_WE#9

DC_CAS#9

DC_RAS#9

DC_CS#9

DC_CLK9

U8

DC_CKE

9 DC_RAS#9 DC_CS#

U9

DC_MA109DC_MA119

DC_MA99

DC_MA89

9 DC_MA0

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF 40

1.3

PROJECT:INTEL(R) 810

CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

VCC3_3

50-P

IN T

SO

PS

DR

AM

21 A022 A1

20 A1019 A11

23 A224 A327 A428 A529 A630 A731 A832 A9

CLK35

2DQ03DQ1

42DQ1043DQ1145DQ1246DQ1348DQ1449DQ15

5DQ26DQ38DQ49DQ511DQ612DQ739DQ840DQ9

LDQM 14

NC_133

NC_237

UDQM 36

7V

DD

Q_1

13V

DD

Q_2

38V

DD

Q_3

44V

DD

Q_4

1V

DD

_125

VD

D_2

47V

SS

Q_1

41V

SS

Q_2

10V

SS

Q_3

4V

SS

Q_4

50V

SS

_1

26V

SS

_2

34 CKE

CAS#16

17 RAS#

CS#18

15 WE#

14

36

48

49

46

45

43

42

40

39

12

11

9

8

6

5

3

2

37

33

15

16

17

18

34

3550264741104

4438137251

19

20

32

31

30

29

28

27

24

23

22

21

VCC3_3

VCC3_3

50-P

IN T

SO

PS

DR

AM

21 A022 A1

20 A1019 A11

23 A224 A327 A428 A529 A630 A731 A832 A9

CLK35

2DQ03DQ1

42DQ1043DQ1145DQ1246DQ1348DQ1449DQ15

5DQ26DQ38DQ49DQ511DQ612DQ739DQ840DQ9

LDQM 14

NC_133

NC_237

UDQM 36

7V

DD

Q_1

13V

DD

Q_2

38V

DD

Q_3

44V

DD

Q_4

1V

DD

_125

VD

D_2

47V

SS

Q_1

41V

SS

Q_2

10V

SS

Q_3

4V

SS

Q_4

50V

SS

_1

26V

SS

_2

34 CKE

CAS#16

17 RAS#

CS#18

15 WE#

21

22

23

24

27

28

29

30

31

32

20

19

1 25 7 13 38 44

4 10 41 47 26 50

35

34

18

17

16

15

33

37

2

3

5

6

8

9

11

12

39

40

42

43

45

46

49

48

36

14

4MB Display Cache

SLAVE ADDRESS = 1010000BDIMM0

11

SYSTEM MEMORY: DIMM0

12-8-1998_13:14

SM_MD[63:0]8,12

SM

_MD

1

SM

_MD

10

SM

_MD

27

SM

_MD

61

SM

_MD

63

SM

_MD

62

SM

_MD

60

SM

_MD

59

SM

_MD

58

SM

_MD

57

SM

_MD

56

SM

_MD

55

SM

_MD

54

SM

_MD

53

SM

_MD

52

SM

_MD

51

SM

_MD

50

SM

_MD

49

SM

_MD

48

SM

_MD

47

SM

_MD

46

SM

_MD

45

SM

_MD

44

SM

_MD

43

SM

_MD

42

SM

_MD

41

SM

_MD

40

SM

_MD

39

SM

_MD

38

SM

_MD

37

SM

_MD

36

SM

_MD

35

SM

_MD

34

SM

_MD

33

SM

_MD

32

SM

_MD

31

SM

_MD

30

SM

_MD

29

SM

_MD

28

SM

_MD

26

SM

_MD

25

SM

_MD

24

SM

_MD

23

SM

_MD

22

SM

_MD

21

SM

_MD

20

SM

_MD

19

SM

_MD

18

SM

_MD

17

SM

_MD

16

SM

_MD

15

SM

_MD

14

SM

_MD

13

SM

_MD

12

SM

_MD

11

SM

_MD

9

SM

_MD

8

SM

_MD

7

SM

_MD

6

SM

_MD

5

SM

_MD

4

SM

_MD

3

SM

_MD

2

SM

_MD

0

8SM_CKE[1:0]

SM

_CK

E0

SM

_CK

E1

8 SM_RAS#8 SM_CAS#8 SM_WE#8

SM_CS#[3:0]

SM

_CS

#1

SM

_CS

#0

8SM_DQM[7:0]

SM

_DQ

M2

SM

_DQ

M4

SM

_DQ

M5

SM

_DQ

M6

SM

_DQ

M7

SM

_DQ

M3

SM

_DQ

M1

SM

_DQ

M0

SM

_BS

1

SM

_BS

0

8SM_BS[1:0]

SM_MAA[11:0]8

SM

_MA

A11

SM

_MA

A1

SM

_MA

A3

SM

_MA

A4

SM

_MA

A6

SM

_MA

A7

SM

_MA

A8

SM

_MA

A9

SM

_MA

A10

SM

_MA

A5

SM

_MA

A2

SM

_MA

A0

6MEMCLK[7:0]

ME

MC

LK3

ME

MC

LK2

ME

MC

LK0

ME

MC

LK1

SMBCLK12,14,25,28,33

SMBDATA12,14,25,28,33

J11

12SAO_PU

VCC3SBY

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF 40

1.3

PROJECT:INTEL(R) 810

CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

A0

33 117

A1

A10

38 123

A11

A12

126

A13

132

A2

34 118

A3

A4

35 119

A5

A6

36 120

A7

A8

37 121

A9

122

BA

0

BA

139 11

1C

AS

#

128

CK

E0

CK

E1

63

CLK

112

5

79C

LK2

163

CLK

3

2D

Q0

DQ

13 14

DQ

10

DQ

1115 16

DQ

12

DQ

1317 19

DQ

14

20D

Q15

55D

Q16

DQ

1756 57

DQ

18

DQ

19584

DQ

2

60D

Q20

DQ

2165 66

DQ

22

DQ

2367 69

DQ

24

DQ

2570 71

DQ

26

DQ

2772 74

DQ

28

DQ

2975

DQ

35 76

DQ

30

DQ

3177 86

DQ

32

DQ

3387 88

DQ

34

DQ

3589 91

DQ

36

DQ

3792 93

DQ

38

DQ

39947

DQ

4

DQ

4095

DQ

4197 98

DQ

42

DQ

4399 10

3D

Q46

DQ

4710

4

139

DQ

48

DQ

4914

0

DQ

58 14

1D

Q50

DQ

5114

2

DQ

5314

9

DQ

5615

3

154

DQ

57

DQ

5815

5

156

DQ

59

9D

Q6

DQ

6015

8

161

DQ

63

10D

Q7

11D

Q8

28D

QM

B0

29D

QM

B1

DQ

MB

246 47

DQ

MB

3

DQ

MB

411

2

113

DQ

MB

5

DQ

MB

613

0

DQ

MB

713

1

21E

CC

0

EC

C1

22 52E

CC

2

EC

C3

53 105

EC

C4

EC

C5

106

136

EC

C6

EC

C7

137

115

RA

S#

147

RE

GE

S0#

30 114

S1#

S2#

45 129

S3#

165

SA

0

SA

116

6

167

SA

2

83S

MB

CLK

82S

MB

DA

TA

27W

E#

VSS1 1

VSS212

23VSS3

VSS432

43VSS5

VSS654

64VSS7

VSS8 68

78VSS9

VSS10 85

96VSS11

VSS12 107

116VSS13

VSS14 127

138VSS15

VSS16148

152VSS17

VSS18162

NC

124 25

NC

2

NC

331 44

NC

4

NC

548 50

NC

6

NC

751 61

NC

8

NC

962 80

NC

10

WP

81 108

NC

11

NC

1210

9

134

NC

13

NC

1413

5

145

NC

15

NC

1614

6

164

NC

17

144

DQ

52

42C

LK0

6VCC1

VCC218

26VCC3

VCC440

41VCC5

VCC690

102VCC7

VCC8110

124VCC9

49VCC10

VCC1159

73VCC12

VCC1384

133VCC14

VCC15143

157VCC16

VCC17168

DQ

913 10

0D

Q44

DQ

4510

1

150

DQ

54

DQ

5515

1

159

DQ

61

DQ

6216

016

0

159

151

150

101

100

13168

157

143

133

84

73

59

49

124

110

102

90

41

40

26

18

6

42

144

164

146

145

135

134

109

108

81 80626151504844312524

162

152

148

138

127

116

107

96

85

78

68

64

54

43

32

23

12

1

27 82 83 167

166

165

129

45114

30 147

115

137

136

106

105

53522221

131

130

113

112

47462928

1110 161

158

9 156

155

154

153

149

142

141

8 140

139

104

103

999897957 949392918988878677765 757472717069676665604 5857565520191716151432

163

79125

63128

111

39122

121

37120

36119

35118

34 132

126

123

38117

33

SYSTEM MEMORY

DIMM1SLAVE ADDRESS = 1010001B

12

SYSTEM MEMORY: DIMM1

12-8-1998_13:14

11,14,25,28,33SMBCLK

11,14,25,28,33 SMBDATA

8SM_WE#

8 SM_CAS#

8 SM_RAS#

SM

_CK

E0

SM

_CK

E1

8SM_CKE[1:0]

ME

MC

LK4

ME

MC

LK5

ME

MC

LK6

ME

MC

LK7

6MEMCLK[7:0] S

M_M

AB

4#

SM

_MA

B5#

SM

_MA

B6#

SM

_MA

B7#

8SM_MAB[7:4]#

SM

_MA

A0

SM

_MA

A1

SM

_MA

A2

SM

_MA

A3

SM

_MA

A8

SM

_MA

A9

SM

_MA

A10

SM

_MA

A11

SM_MAA[11:0]8

SM

_BS

0

SM

_BS

1

8SM_BS[1:0]

SM

_DQ

M0

SM

_DQ

M1

SM

_DQ

M2

SM

_DQ

M3

SM

_DQ

M4

SM

_DQ

M5

SM

_DQ

M6

SM

_DQ

M7

8SM_DQM[7:0]

8SM_CS#[3:0]

SM

_CS

#3

SM

_CS

#2

SM

_MD

62

SM

_MD

61

SM

_MD

60

SM

_MD

59

SM

_MD

58

SM

_MD

57

SM

_MD

56

SM

_MD

55

SM

_MD

54

SM

_MD

53

SM

_MD

52

SM

_MD

51

SM

_MD

50

SM

_MD

49

SM

_MD

48

SM

_MD

47

SM

_MD

46

SM

_MD

45

SM

_MD

44

SM

_MD

43

SM

_MD

42

SM

_MD

41

SM

_MD

40

SM

_MD

39

SM

_MD

38

SM

_MD

37

SM

_MD

36

SM

_MD

35

SM

_MD

34

SM

_MD

33

SM

_MD

32

SM

_MD

31

SM

_MD

30

SM

_MD

29

SM

_MD

28

SM

_MD

27

SM

_MD

26

SM

_MD

25

SM

_MD

24

SM

_MD

23

SM

_MD

22

SM

_MD

21

SM

_MD

20

SM

_MD

19

SM

_MD

18

SM

_MD

17

SM

_MD

16

SM

_MD

15

SM

_MD

14

SM

_MD

13

SM

_MD

12

SM

_MD

11

SM

_MD

10

SM

_MD

9

SM

_MD

8

SM

_MD

7

SM

_MD

6

SM

_MD

5

SM

_MD

4

SM

_MD

3

SM

_MD

2

SM

_MD

1

SM

_MD

0

8,11SM_MD[63:0]

SM

_MD

63

2.2K

R60

J13

SAO_PU

VCC3SBY

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF 40

1.3

PROJECT:INTEL(R) 810

CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

VCC3SBY

A0

33 117

A1

A10

38 123

A11

A12

126

A13

132

A2

34 118

A3

A4

35 119

A5

A6

36 120

A7

A8

37 121

A9

122

BA

0

BA

139 11

1C

AS

#

128

CK

E0

CK

E1

63

CLK

112

5

79C

LK2

163

CLK

3

2D

Q0

DQ

13 14

DQ

10

DQ

1115 16

DQ

12

DQ

1317 19

DQ

14

20D

Q15

55D

Q16

DQ

1756 57

DQ

18

DQ

19584

DQ

2

60D

Q20

DQ

2165 66

DQ

22

DQ

2367 69

DQ

24

DQ

2570 71

DQ

26

DQ

2772 74

DQ

28

DQ

2975

DQ

35 76

DQ

30

DQ

3177 86

DQ

32

DQ

3387 88

DQ

34

DQ

3589 91

DQ

36

DQ

3792 93

DQ

38

DQ

39947

DQ

4

DQ

4095

DQ

4197 98

DQ

42

DQ

4399 10

3D

Q46

DQ

4710

4

139

DQ

48

DQ

4914

0

DQ

58 14

1D

Q50

DQ

5114

2

DQ

5314

9

DQ

5615

3

154

DQ

57

DQ

5815

5

156

DQ

59

9D

Q6

DQ

6015

8

161

DQ

63

10D

Q7

11D

Q8

28D

QM

B0

29D

QM

B1

DQ

MB

246 47

DQ

MB

3

DQ

MB

411

2

113

DQ

MB

5

DQ

MB

613

0

DQ

MB

713

1

21E

CC

0

EC

C1

22 52E

CC

2

EC

C3

53 105

EC

C4

EC

C5

106

136

EC

C6

EC

C7

137

115

RA

S#

147

RE

GE

S0#

30 114

S1#

S2#

45 129

S3#

165

SA

0

SA

116

6

167

SA

2

83S

MB

CLK

82S

MB

DA

TA

27W

E#

VSS11

VSS212

23VSS3

VSS432

43VSS5

VSS654

64VSS7

VSS868

78VSS9

VSS1085

96VSS11

VSS12107

116VSS13

VSS14 127

138VSS15

VSS16 148

152VSS17

VSS18 162

NC

124 25

NC

2

NC

331 44

NC

4

NC

548 50

NC

6

NC

751 61

NC

8

NC

962 80

NC

10

WP

81 108

NC

11

NC

1210

9

134

NC

13

NC

1413

5

145

NC

15

NC

1614

6

164

NC

17

144

DQ

52

42C

LK0

6VCC1

VCC218

26VCC3

VCC440

41VCC5

VCC690

102VCC7

VCC8110

124VCC9

49VCC10

VCC1159

73VCC12

VCC1384

133VCC14

VCC15143

157VCC16

VCC17168

DQ

913 10

0D

Q44

DQ

4510

1

150

DQ

54

DQ

5515

1

159

DQ

61

DQ

6216

016

0

159

151

150

101

100

13

168

157

143

133

84

73

59

49

124

110

102

90

41

40

26

18

6

42

144

164

146

145

135

134

109

108

81 80626151504844312524

162

152

148

138

127

116

107

96

85

78

68

64

54

43

32

23

12

1

27 82 83 167

166

165

129

45114

30 147

115

137

136

106

105

53522221

131

130

113

112

47462928

1110 161

158

9 156

155

154

153

149

142

141

8 140

139

104

103

999897957 949392918988878677765 757472717069676665604 5857565520191716151432

163

79125

63128

111

39122

121

37120

36119

35118

34 132

126

123

38117

33

SYSTEM MEMORY

13

ICH0, PART 1

2-22-1999_10:37

0K

R181

R175

8.2K

R174

8.2K

4,33A20M#

4,15,33INIT#

4,33NMI

4,33INTR

4,33CPUSLP#

16,33RCIN#4,33STPCLK#4,33SMI#

4,33IGNNE#4,33FERR#

17,18,27,33DEVSEL#

17,18,27,33 IRDY#

17,18,27,33 TRDY#

17,18,27,33 STOP#

7,15,16,17,18,19,24,27 PCIRST#

17,18,33 PLOCK#

17,18,27 PAR

17,18,27,33 SERR#

17,18,27 PCI_PME#

18,33 PCPCI_REQ#A

18PCPCI_GNT#A

33 REQ#B/GPIO1

C_BE#3

C_BE#2

C_BE#1

C_BE#017,18,27C_BE#[3:0]

17,18,33PIRQ#C

17,18,33PIRQ#D

19,33IRQ14

19,33IRQ15

17,33PREQ#0

17,33PREQ#1

18,33PREQ#2

27,33PREQ#3

17,33PGNT#0

27,33PGNT#3

AD31

AD30

AD29

AD28

AD27

AD26

AD25

AD24

AD23

AD22

AD21

AD20

AD19

AD18

AD17

AD16

AD15

AD14

AD13

AD12

AD11

AD10

AD9

AD8

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD017,18,27AD[31:0]

4,33APICD1

4,33APICD0

PIRQ#B 17,18,33

PIRQ#A 17,18,27,33

8HLSTB

6APICCLK_ICH

17,33PGNT#1

18,33PGNT#2

HL2

HL3

HL4

HL6

HL7

HL8

HL9

HL10

HL0 8HL[10:0]

HL1

HL5

8HLSTB#

16,33A20GATE

17,18,27,33 FRAME#6 PCLK_0/ICH

U14

16,18,33SERIRQ

8HUBREF

33 GNT#B/GPIO17

C302

0.1UF

R18240, 1%

RESV0PU

RESV1PU

RESV2PD

IHCOMP_PU

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF 40

1.3

PROJECT:INTEL(R) 810

CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

A20GATE B15

F13A20M#AD0G2

AD1G4

E4 AD10

AD11C2

C1 AD12

AD13B1

D4 AD14

AD15C3

A4 AD16

AD17B4

C5 AD18

AD19C6

F2 AD2

B5 AD20

AD21E7

A6 AD22

AD23B6

D7 AD24

AD25B8

A7 AD26

AD27A8

B7 AD28

AD29C9

AD3F3

D8 AD30

AD31C7

F4 AD4

AD5F5

E1 AD6

AD7E2

D1 AD8

AD9D3

C16APICCLK

E16APICD0

C17APICD1

E12CPUSLP#

D2 C_BE#0

C_BE#1B2

A3 C_BE#2

C_BE#3D6

D9 DEVSEL#

FERR# F15

FRAME#B3

GNT#0 A13

GNT#1 C13

GNT#2 A12

C12GNT#3

GNT#A/GPIO16P5

GNT#B/GPIO17/GNT5#R5

M17HCOMP

HL0 D17

E17HL1

HL10 J14

HL2 F17

HL3 G16

J15HL4

HL5 K16

K17HL6

HL7 L17

H15HL8J17HL9

HLSTB G17

H17HLSTB#

J13HUBREF

B17IGNNE#

INIT# E15

INTR E14

A2 IRDY#

P11IRQ14N14IRQ15

B16NMI

PARA9

PCICLKC14

PCIRST#J5

D10PIRQ#AA10PIRQ#BB10PIRQ#CC10PIRQ#D

B9 PLOCK#

PME#K1

RCIN# A15

REQ#0 A14

REQ#1 B13

REQ#2 B12

D12REQ#3

N6 REQ#A/GPIO0

REQ#B/GPIO1/REQ5#P4

A11GNT4#B11REQ4#F16HL11

R4SERIRQ

A1 SERR#

SMI# F14

D5 STOP#

A17STPCLK#

TRDY#C4

VC

C1_

8_1

G13

H14

VC

C1_

8_2

VC

C1_

8_3

K14

G15

VC

C1_

8_4

VC

C1_

8_5

L15

H16

VC

C1_

8_6

VC

C1_

8_7

J16

VC

C3_

3_1

E3

C8

VC

C3_

3_10

VC

C3_

3_11

A5

VC

C3_

3_12

E6

E5

VC

C3_

3_13

D16

VC

C3_

3_14

VC

C3_

3_15

N5

N13

VC

C3_

3_16

VC

C3_

3_17

E13

G5

VC

C3_

3_2

VC

C3_

3_3

P6

T7

VC

C3_

3_4

U10

VC

C3_

3_5

VC

C3_

3_6

R13

T16

VC

C3_

3_7

VC

C3_

3_8

M14

C11

VC

C3_

3_9

VS

S1

R2

J10

VS

S10

VS

S11

K10

G14

VS

S12

VS

S13

K15G3

VS

S2

VS

S3

H8 J8

VS

S4

VS

S5

K8

H9

VS

S6

VS

S7

J9 K9

VS

S8

VS

S9

H10

HUB I/F

IRQ

PCI

PCI

PART 1INTEL 82801AB

PC/PCI

CPU

H10K9J9H9

K8J8H8

G3

K15

G14

K10J10

R2

C11

M14

T16

R13

U10

T7

P6

G5

E13

N13

N5

D16

E5

E6

A5

C8

E3

J16

H16

L15

G15

K14

H14

G13

C4

A17

D5

F14

A1

R4

F16

B11

A11

P4

N6

D12

B12

B13

A14

A15

K1

B9

C10

B10

A10

D10

J5

C14

A9

B16

N14

P11

A2

E14

E15

B17

J13

H17

G17

M17

J17

H15

L17

K17

K16

J15

G16

F17

J14

E17

D17

R5

P5

C12

A12

C13

A13

B3

F15

D9

D6

A3

B2

D2

E12

C17

E16

C16

D3

D1

E2

E1

F5

F4

C7

D8

F3

C9

B7

A8

A7

B8

D7

B6

A6

E7

B5

F2

C6

C5

B4

A4

C3

D4

B1

C1

C2

E4

G4

G2 F13

B15

VCC3_3

VCC1_8VCC3_3

VCC1_8

ICH0, Part 1

as possible to ICH0.

For Test/Debug

Place C302 as close

possible to ICH0.

Place R182as close as

Don’t Stuff R181

14

ICH0, PART 2

5-26-1999_17:09

29,32 SLP_S3#33 THERM#

28,32 PWROK

31 PWRBTN#

ICH_RI#22

28,32 RSMRST#

28 SUS_STAT#

11,12,25,28,33 SMBDATA

11,12,25,28,33 SMBCLK

SMBALERT#33

INTRUDER#33

6 ICH_CLK14

6 USBCLK

ICH_3V666

VBIAS

RTCX1

RTCX2

RTCRST#

26 AC_RST#

26 AC_SYNC

26 AC_BITCLK

14,26 AC_SDOUT

26,33 AC_SDIN0

26,33 AC_SDIN1

14,31 ICH_SPKR

LPC_SMI#16,33LPC_PME#16,33

18,33GPIO7

GPIO1233GPIO1333

18,33 GPIO21

33 GPIO22

31 GPIO23_FPLED

GPIO26_FPLED31

28 GPIO27

28 GPIO28

15,16 LAD0/FWH0

15,16 LAD1/FWH1

15,16 LAD2/FWH2

15,16 LAD3/FWH3

15,16 LFRAME#/FWH4

16 LDRQ#0

LDRQ#133

20 USBP1P

20 USBP1N

20USBP0P

20 USBP0N

SDD15

SDD14

SDD13

SDD12

SDD11

SDD10

SDD9

SDD8

SDD7

SDD6

SDD5

SDD4

SDD3

SDD2

SDD1

SDD0 19SDD[15:0]

19PDD[15:0]

PDD0

PDD1

PDD2

PDD3

PDD4

PDD5

PDD6

PDD7

PDD8

PDD9

PDD10

PDD11

PDD12

PDD13

PDD14

PDD15

19SIORDY19PIORDY19SDIOW#19PDIOW#19SDIOR#19PDIOR#19SDDACK#19

PDDACK#19SDREQ19PDREQ

SDA0

SDA1

SDA2

19SDA[2:0]

PDA0

PDA1

PDA2

19PDA[2:0]

19SDCS#319PDCS#319SDCS#119PDCS#1

20 OC#0

ICH5VREF

R173

1K

R220

10MY3

32.768KHZ

CR11

BA

T17

10K

R209

R187

10K

1.0UF

C290

0.1UF

C294

14,31 ICH_SPKR

JP17

JP18

14,26AC_SDOUT

R202 1K

C347

2200PF

R219

8.2K

10M

R197

BA

T17

CR14

JP20

1K

R206

1.0UF

C349

BAT17

CR13

VBATC

VBATC_DLY

JP13

_PD

JP14

_PU

R_VBIAS

JP24

_PD

C366

12PF

C293

18PF

2.2UF

C364

12PF

C346

X3

VB

AT

R216

1K

VRTC

U1410K

R85

10K

R203

SLP_S5#

VCC3SBY

VCC3_3

VCC3SBY

VCC3_3 VCC5

1 2

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF 40

1.3

PROJECT:INTEL(R) 810

CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

C

A

A

C

1

2

33

2

1

CA

+2

1

+2 13

VCC3SBY

C15

5VR

EF

R3 AC_BITCLK

T1 AC_RST#

U1 AC_SDIN0P3 AC_SDIN1/GPIO9

T2 AC_SDOUT

T3 AC_SYNC

U6 CLK14

CLK48U2

CLK66A16

GPIO12N4

GPIO13L2

B14 GPIO21

GPIO22D13

GPIO23D15

K4 GPIO26/SUSCLKM5 GPIO27L5 GPIO28

D11 GPIO5

GPIO6E11

GPIO7/PERR#E9

J4 INTRUDER#/GPIO10

R6 LAD0/FWH0

LAD1/FWH1U5

T5 LAD2/FWH2

LAD3/FWH3T4

LDRQ#0T6

N3 LDRQ#1/GPIO8

LFRAME#/FWH4U4

OC#0M3OC#1M4

PDA0 R12

PDA1 T12

PDA2 P12

PDCS#1 N12

PDCS#3 U13

PDD0 R10

N9PDD1

PDD10 T8

P8PDD11

PDD12 T9

P9PDD13

PDD14 T10

PDD15 P10

PDD2 R9

U9PDD3

PDD4 R8

U8PDD5

PDD6 R7

U7PDD7

PDD8 P7

N7PDD9

PDDACK# U12

PDDREQ U11

PDIOR# R11

PDIOW# T11

PIORDY N11

M2 PWRBTN#

J3 PWROK

L3 RI#F1 RSMRST#

RTCRST#H1

RTCX1H3

RTCX2H4

SDA0 M16

SDA1 M15

SDA2 L13

SDCS#1 L14

SDCS#3 L16

SDD0 P15

R16SDD1

SDD10 P14

T15SDD11

SDD12 U17

R15SDD13

SDD14 R17

SDD15 P16

SDD2 T17

U16SDD3

SDD4 U15

R14SDD5

SDD6 P13

T13SDD7

SDD8 U14

T14SDD9

SDDACK# M13

SDDREQ P17

SDIOR# N16

SDIOW# N15

SIORDY N17

K3 SLP_S3/GPIO24K2 SLP_S5

M1 SMBALERT#/GPIO11

SMBCLKJ2

J1 SMBDATA

U3 SPKR

L4 SUSSTAT#/GPIO25

D14 THRM#

USBP0NN2USBP0PP1USBP1NP2USBP1PR1

VBIASH2

G1

VC

CR

TC

VC

CS

US

1L1N

1V

CC

SU

S2

IDE

SYSTEM

AC97

GPIO

LPC

USB

PART 2INTEL 82801AB

ICH0PART 2

Minimize Stub Lengthto Jumpers

SocketedCR2032

R85 and R203 for Test/Debug

JP17 STRAP (SPKR)IN No Reboot on 2nd watchdog timeoutOUT Reboot on 2nd watchdog timeout

JP18 (AC_SDOUT)IN Force CPU freq strap to safe mode (1111)OUT Use CPU freq strap in ICH register

1-2 Normal 2-3 Clear CMOS

JP20 Config

152-22-1999_10:37

FIRMWARE HUB (FWH)

6 PCLK_6

13,17,18,24,27 PCIRST#

19 S66DETECT

19P66DETECT

14,16LAD0/FWH014,16LAD1/FWH114,16LAD2/FWH214,16LAD3/FWH3

4,13,33INIT#

WPROT

TBLK_LCK

R223

4.7K

0KR218

JP21

C211

0.1UF 0.1UF

C355 C361

0.1UF

C259

0.1UF

C353

0.1UF

C36

0.1UF

4.7K

R222

RP638.2K

FWH_ID0

FWH_ID1

FWH_ID2

FWH_ID3

RP640K

40PIN_TSOP_SKTX4

R_VPP

FG

PI2

_PD

IC_P

D

FG

PI4

_PD

FG

PI3

_PD

LFRAME#/FWH4 14

VCC3_3

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF 40

1.3

PROJECT:INTEL(R) 810

CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

VCC3_3 VCC3_3

VCC3_3VCC3_3

12345 6 7 88765

4 3 2 1 12345 6 7 8

12345 6 7 8

1NC1

NC33

NC44

5NC5

NC66

8NC8

IC2

CLK9

VCC1010

VPP11

RST#12

13 NC13

NC1414

WP#19

TBL#20 21ID3

ID222

ID123

ID024

FWH025

FWH1 26

FWH227

FWH3 28

GND2929

GND30 30

VCC3131

RFU32 32

33RFU33

34RFU34

RFU3535

RFU3636

INIT# 37

FWH438

VCCA 39

40GNDA

7FGPI4

FGPI315

16FGPI2

FGPI117

18FGPI0

18

17

16

15

7

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

2120

19

14

13

12

11

10

9

2

8

6

5

4

3

1

Distribute close to each power pin.

FirmWare Hub (FWH) SocketNOTE: This is a Socketed Implementation

RP64 for Test/Debug

JP21 CONFIGIN Unlocked

OUT Locked Default

16

SUPER I/O

11-23-1998_13:44

R183

4.7K

IRRX31

470PF

C371

IRTX31

J23

22 DCD#122

RI#122 DTR#1

22 RTS#122 DSR#1

22 CTS#1

14,15 LAD3/FWH3

14,15 LAD2/FWH2

14,15 LAD1/FWH1

14,15 LAD0/FWH0

14 LDRQ#0

13,17,18,24,27 PCIRST#

14,33LPC_PME#

13,18,33 SERIRQ

6 PCLK_1

13,33 RCIN#

13,33A20GATE

22RXD#0

22 TXD0

22DSR#0

22RTS#0

22CTS#0

DTR#02222 RI#0

DCD#022

23DRVDEN#1

23DRVDEN#0

23MTR#0

23DS#0

23 DIR#

23 STEP#

23WDATA#

23 WGATE#

23HDSEL#

23 INDEX#

23 TRK#0

23WRTPRT#

JOY2Y 23

23JOY2X23JOY1Y23JOY1X23

J2BUTTON223J2BUTTON123J1BUTTON223J1BUTTON1

23MIDI_OUT

MIDI_IN 23

31TACH131TACH2

31PWM1

31PWM2

STROBE#21

21ALF#

21ERROR#

21ACK#21BUSY21PE21

SLCT#

21PDR[7:0]

PDR6

PDR5

PDR4

PDR2

PDR1

PDR0

PDR7

PDR3

21SLCTIN#

23 RDATA#

21PAR_INIT#

23 DSKCHG#

6 SIO_CLK14

SIO_GP43

SIO_GP21

SIO_GP22

14,33LPC_SMI#

2.2UF

C99 C297

0.1UF 0.1UF

C229

SIO_GP61

TXD122

C287

0.1UF 0.1UF

C246C323

0.1UF

470PF

C356

SYSOPT

SIO_GP60

KEYLOCK# 31

RXD#122

23KCLK

23KDAT

23MDAT

23MCLK

14 LFRAME#/FWH4

R180

4.7K

SUSSTAT_PU

U15

VCC3_3

5

1

3

2

4

66

4

2

3

1

5

VCC5VCC3_3

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF 40

1.3

PROJECT:INTEL(R) 810

CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

VCC5

+2

1VCC3_3

SIOLPC47B27X

A20GATE64

ACK# 80

ALF# 82

40A

VS

S

BUSY79

CLKI326

CLOCKI19

CTS1#88

99CTS2#

DCD1#91

94DCD2#

DIR#8

DRVDEN01

DRVDEN12

DS0#5

DSKCHG#4

DSR1#86

DSR2#97

DTR1#89

100DTR2#

ERROR#81

FAN1/GP33 55

FAN2/GP3254

FDC_PP/DDRC/GP43 28

GN

D1

7

GN

D2

31

GN

D3

60 76G

ND

4

GP10/J1B1 32

GP11/J1B233

GP12/J2B134

GP13/J2B235

GP14/J1X36

GP15/J1Y 37

GP16/J2X38

GP17/J2Y 39

GP20/P1741

GP21/P16 42

GP22/P1243

GP25/MIDI_IN46

GP26/MIDI_OUT 47

GP27/IO_SMI#50

GP30/FAN_TACH251

GP31/FAN_TACH1 52

GP60/LED148

GP61/LED249

HDSEL#12

INDEX#13

INIT# 66

IRRX2/GP3461

IRTX2/GP3562

KBDRST63

KCLK57

KDAT56

LAD020

LAD121

LAD222

LAD323

LDRQ#25

LFRAME#24

LRESET#26

MCLK59

MDAT58

MTR0#3

PCI_CLK29 PD0 68

PD169

PD270

PD371

PD472

PD5 73

PD674

PD7 75

PE 78

PME#17

RDATA#16

RI1#90

92RI2#

RTS1#87

RTS2#98

RXD184

RXD2_IRRX95

SERIRQ30

SLCT#77

SLCTIN#67

STEP#9

STROBE#83

TRK0#14

TXD185

TXD2_IRTX96

VC

C1

53

VC

C2

65

VC

C3

93

WDATA#10

WGATE#11

WRTPRT#15

44V

RE

F

GP24/SYSOPT45

VT

R18

LPCPD#27

SERIAL PORT 1

SERIAL PORT 2

FDC I/F

LPC I/F

INFRARED I/F

CLOCKS

KYBD/MSE I/F

PARALLEL PORT I/F27

18

45

44

15

11

10

936553

96

85

14

83

9

67

77

30

95

84

98

87

92

90

16

17

78

75

74

73

72

71

70

69

6829

3

58

59

26

24

25

23

22

21

20

56

57

63

62

61

66

13

12

49

48

52

51

50

47

46

43

42

41

39

38

37

36

35

34

33

32

766031

7

28

54

55

81

100

89

97

86

4

5

2

1

8

94

91

99

88

19

6

79

40

82

80

64

Pulldown on SYSOPT for IO address of 0x02E

Super I/O

Decoupling

Place nearVREF pin

Place 1 0.1UF cap near each power pin

Test/Debug HeaderUnused GPIOs

17

PCI CONNECTORS 1 AND 2

11-23-1998_13:44

R191

100

J16

AD0

AD2

AD4

AD6

AD9

AD11

AD13

AD15

AD16

AD18

AD20

AD22

AD24

AD26

AD28

13,17,18,27AD[31:0]AD30

33PU2_REQ64#

C_BE#0 13,17,18,27

13,17,18,27PAR

33SBOP233SDONEP2

13,17,18,27,33FRAME#

PCI_PME# 13,17,18,27

PGNT#113,33

13,17,18,27,33 PIRQ#A

AD31

AD29

AD27

AD25

AD23

AD21

AD19

AD17

AD14

AD12

AD10

AD8

AD7

AD5

AD3

AD1

13,17,18,27AD[31:0]

C_BE#3

C_BE#2

C_BE#1

13,17,18,27C_BE#[3:0]

18 PRSNT#22

18 PRSNT#21

17,18PTRST#

PTMS 17,18,33

17,18,33PTDI

PIRQ#B13,17,18,33

13,17,18,33PIRQ#D

PCIRST# 7,13,15,16,17,18,19,24,27

R_AD17

13,17,18,27,33TRDY#

13,17,18,27,33STOP#

13,17,18,27,33 SERR#

17,18,27 PERR#13,17,18,33 PLOCK#

13,17,18,27,33DEVSEL#

13,17,18,27,33 IRDY#

13,33 PREQ#1

6 PCLK_3

13,17,18,33 PIRQ#C

PTCK17,18

17,18 PTCK

PIRQ#B13,17,18,33

PCLK_26

PREQ#013,33

IRDY#13,17,18,27,33

DEVSEL#13,17,18,27,33

PLOCK#13,17,18,33PERR#

17,18,27

SERR#13,17,18,27,33

STOP# 13,17,18,27,33

TRDY# 13,17,18,27,33

R_AD16

7,13,15,16,17,18,19,24,27PCIRST#

PIRQ#C 13,17,18,33

13,17,18,27,33PIRQ#A

PTDI 17,18,33

17,18,33PTMS

PTRST# 17,18

PRSNT#1118

PRSNT#1218

C_BE#[3:0]13,17,18,27

C_BE#2

C_BE#1

C_BE#3

AD[31:0]13,17,18,27

AD29

AD25

AD23

AD19

AD17

AD14

AD10

AD8

AD7

AD5

AD3

AD1

AD31

AD27

AD21

AD12

PIRQ#D13,17,18,33

PU1_ACK64#33

13,33PGNT#0

13,17,18,27PCI_PME#

FRAME# 13,17,18,27,33

SDONEP133

SBOP1 33

PAR 13,17,18,27

13,17,18,27C_BE#0

PU1_REQ64#33

AD0

AD2

AD4

AD6

AD9

AD11

AD13

AD15

AD16

AD18

AD20

AD22

AD24

AD26

AD28

AD30 AD[31:0]13,17,18,27

AD16 13,17,18,27

13,17,18,27AD17

33 PU2_ACK64#

J17

100

R168

PCI3_CON

A2

A21

A27

A33

A39

A45

B25

B31

B36

B41

B43

A53

B54

A5

A10

A16

B5

B6

A59

A61

A62

B61

B19

B1

B60

A58B58

B48

A47B47

A46

B45

B32

A31

B30

A29B29

B27

A25

B24

B23

A22

B21

B56

B20

A55B55

A54

B53

B52

A49

A52

B44

B33

B26

B16

A9

B37

A34

A12

A13

A18

A24

A30

A35

A37

A42

A48

B3

B12

B13

B15

B17

B22

B34

B38

B46

B49

A56

B57

B28

A17

A26

A6

B7 A7

B8

B35

B39

A43

B40

B9

B11

B2

B4 A4

A3

A1

B18

A60

A11

A14

B10

B14

A15

A41

A40

B42

A36

A57

A44

B59

A38

A32

A28

A8

B62

A19

A20

A23

key

A2

A21

A27

A33

A39

A45

B25

B31

B36

B41

B43

A53

B54

A5

A10

A16

B5

B6

A59

A61

A62

B61

B19

B1

B60

A58B58

B48

A47B47

A46

B45

B32

A31

B30

A29B29

B27

A25

B24

B23

A22

B21

B56

B20

A55B55

A54

B53

B52

A49

A52

B44

B33

B26

B16

A9

B37

A34

A12

A13

A18

A24

A30

A35

A37

A42

A48

B3

B12

B13

B15

B17

B22

B34

B38

B46

B49

A56

B57

B28

A17

A26

A6

B7 A7

B8

B35

B39

A43

B40

B9

B11

B2

B4 A4

A3

A1

B18

A60

A11

A14

B10

B14

A15

A41

A40

B42

A36

A57

A44

B59

A38

A32

A28

A23

A8

B62

A19

A20

VCC3SBY

VCC3_3

VCC5

VCC12

VCC12M

VCC5

VCC3_3

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF 40

1.3

PROJECT:INTEL(R) 810

CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

VCC3_3

VCC5

VCC12M

VCC12

VCC5

VCC3_3

VCC3SBY

PCI3_CON

A2

A21

A27

A33

A39

A45

B25

B31

B36

B41

B43

A53

B54

A5

A10

A16

B5

B6

A59

A61

A62

B61

B19

B1

B60

A58B58

B48

A47B47

A46

B45

B32

A31

B30

A29B29

B27

A25

B24

B23

A22

B21

B56

B20

A55B55

A54

B53

B52

A49

A52

B44

B33

B26

B16

A9

B37

A34

A12

A13

A18

A24

A30

A35

A37

A42

A48

B3

B12

B13

B15

B17

B22

B34

B38

B46

B49

A56

B57

B28

A17

A26

A6

B7 A7

B8

B35

B39

A43

B40

B9

B11

B2

B4 A4

A3

A1

B18

A60

A11

A14

B10

B14

A15

A41

A40

B42

A36

A57

A44

B59

A38

A32

A28

A8

B62

A19

A20

A23

key

A20

B62

A8

A23

A28

A32

A38

B59

A44

A57

A36

B42

A40

A41

A15

B14

B10

A14

A11

A60

B18

A1

A3

A4B4

B2

B40

A43

B39

B35

B8

A7B7

A6

A26

A17

B28

B57

A56

B49

B46

B38

B34

B22

B17

B15

B13

B12

B3

A48

A42

A37

A35

A30

A24

A18

A13

A12

A34

B37

A9

B16

B52

B53

A54

B55 A55

B20

B56

B21

A22

B23

B24

A25

B27

B29 A29

B30

A31

B32

B45

A46

B47 A47

B48

B58 A58

B60

B1

B19

B61

A62

A61

A59

B6

B5

A16

A10

A5

B54

A53

B43

B41

B36

B31

B25

A45

A39

A33

A27

A21

A2

(DEV Ah) (DEV Bh)PCI Connector 0 PCI Connector 1

18

PCI CONNECTOR 3

11-23-1998_13:44

JP19

100

R167

C342

0.1UF

18PRSNT#31

PRSNT#3218 PCPCI_GNT#A 13

17 PRSNT#11

PRSNT#2217

PRSNT#1217

PRSNT#2117

18 PRSNT#32

17,18 PTCK

PIRQ#D13,17,33

PCLK_46

PREQ#213,33

IRDY#13,17,27,33

DEVSEL#13,17,27,33

PLOCK#13,17,33PERR#17,18,27

SERR#13,17,27,33

STOP# 13,17,27,33

TRDY# 13,17,27,33

R_AD22

PIRQ#A 13,17,27,33

13,17,33PIRQ#C

PTDI 17,33

17,33PTMS

PTRST# 17,18

PRSNT#3118

C_BE#1

C_BE#2

C_BE#3C_BE#[3:0]

13,17,27

AD1

AD3

AD5

AD7

AD8

AD10

AD12

AD14

AD17

AD19

AD21

AD23

AD25

AD27

AD29

AD31AD[31:0]

13,17,18,27

PIRQ#B13,17,33

PU3_ACK64#33

13,33PGNT#2

13,17,27PCI_PME#

FRAME# 13,17,27,33

SDONEP3 33SBOP3

33

PAR 13,17,27

13,17,27C_BE#0

PU3_REQ64# 33

AD[31:0]13,17,18,27

AD28

AD26

AD24

AD22

AD20

AD18

AD16

AD15

AD13

AD11

AD9

AD6

AD4

AD2

AD0

AD30

AD22 13,17,18,27

7,13,15,16,17,19,24,27PCIRST#

R185

13,16,33 SERIRQ

14,33GPIO21

0K

R195

0K

R194

PTRST#17,18

17,18 PTCK

C336

0.1UF 0.1UF

C337 C267

0.1UF 0.1UF

C284 C335

0.1UF

33PERR#_PU

14,33GPIO717,18,27 PERR#

J22

5.6K

R190

R189

5.6K

R193

0K

0K

R192 PCPCI_REQ#A 13,33

VAUX3R_SERIRQ

R_GPO21

R_GNT#A

1

2

3

1

2

3

VCC3_3

VCC5

VCC12M

VCC12

VCC5

VCC3_3

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF 40

1.3

PROJECT:INTEL(R) 810

CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

0K

PCI3_CON

A2

A21

A27

A33

A39

A45

B25

B31

B36

B41

B43

A53

B54

A5

A10

A16

B5

B6

A59

A61

A62

B61

B19

B1

B60

A58B58

B48

A47B47

A46

B45

B32

A31

B30

A29B29

B27

A25

B24

B23

A22

B21

B56

B20

A55B55

A54

B53

B52

A49

A52

B44

B33

B26

B16

A9

B37

A34

A12

A13

A18

A24

A30

A35

A37

A42

A48

B3

B12

B13

B15

B17

B22

B34

B38

B46

B49

A56

B57

B28

A17

A26

A6

B7 A7

B8

B35

B39

A43

B40

B9

B11

B2

B4 A4

A3

A1

B18

A60

A11

A14

B10

B14

A15

A41

A40

B42

A36

A57

A44

B59

A38

A32

A28

A8

B62

A19

A20

A23

key

A20

B62

A8

A23

A28

A32

A38

B59

A44

A57

A36

B42

A40

A41

A15

B14

B10

A14

A11

A60

B18

A1

A3

A4B4

B2

B40

A43

B39

B35

B8

A7B7

A6

A26

A17

B28

B57

A56

B49

B46

B38

B34

B22

B17

B15

B13

B12

B3

A48

A42

A37

A35

A30

A24

A18

A13

A12

A34

B37

A9

B16

B52

B53

A54

B55 A55

B20

B56

B21

A22

B23

B24

A25

B27

B29 A29

B30

A31

B32

B45

A46

B47 A47

B48

B58 A58

B60

B1

B19

B61

A62

A61

A59

B6

B5

A16

A10

A5

B54

A53

B43

B41

B36

B31

B25

A45

A39

A33

A27

A21

A2

VCC3SBY

For Debug Only

PCI Connector 2 (DEV 6h)

For Debug Only

For Debug Only

For Debug Only

Layout Note: Should be in Slot 0 Position (Outside Edge of Board Furthest from CPU)

Do Not Stuff R192

1-2 ICH0 Default2-3 ICH

JP19 - ICH/ICH0 Compatibility

192-22-1999_10:37

ULTRAATA/33 CONNECTORS

13,17,18,24,27 PCIRST# 19PCIRST_BUF#

S66DETECT 15

C186

0.047UF

R_S66DET

470

R132R137

10K

1K

R100

R138

10K

R135

5.6K

1K

R133

33

R140J12

SECONDARYIDE CONN.

J15

PRIMARYIDE CONN.

14 PDREQ

PDIOW#14

PDIOR#14PIORDY14 PRI_PD1

SDIOW#14

SIORDY14

14PDD[15:0]

PDD0

PDD1

PDD2

PDD3

PDD4

PDD5

PDD6

PDD8

PDD9

PDD10

PDD11

PDD12

PDD13

PDD14

PDD15

PDD7

SDD[15:0]14

SDD0

SDD1

SDD2

SDD3

SDD4

SDD5

SDD6

SDD7 SDD8

SDD9

SDD10

SDD11

SDD12

SDD13

SDD14

SDD15

PRI_SD1

PDDACK#14 SDDACK#14

SDCS#3 14PDCS#3 14

IRQ1513,33IRQ1413,33

IDEACTS#31IDEACTP#31

PDCS#114

14SDA[2:0]

SDA1

SDA2

SDA0

19 PCIRST_BUF#

14PDA[2:0]

PDA0

PDA1

PDA2

SDCS#114

19 PCIRST_BUF#

470

R101

5.6K

R134

SDIOR#14

14 SDREQ

R139

33

0K

R96

0K

R95

R_RSTP# R_RSTS#

R_P66DET

C187

0.047UF

R141

8.2KU11

P66DETECT 15

15K

R221

15K

R94

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

5 6

7 8

9

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

5 6

7 8

9

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

5 6

7 8

99

87

65

40

4

39

3837

3635

3433

3231

30

3

29

2827

2625

2423

2221

20

2

19

1817

1615

1413

1211

10

1

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF 40

1.3

PROJECT:INTEL(R) 810

CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

VCC5VCC5

VCC3_3

VCC3_3

SN74LVC07AGND

VCC14

7

5 6

For Host-Side 80-Conductor Cable Detection:

For Drive-Side 80-Conductor Cable Detection:

ULTRAATA/33 IDE CONNECTORS

For Host-Side 80-Conductor Cable Detection:Populate R96 and R221, DePopulate C187

For Drive-Side 80-Conductor Cable Detection:Populate C187, DePopulate R96 and R221

Populate R94 and R95, DePopulate C186

Populate C186, DePopulate R94 and R95

USB CONNECTORS

2011-23-1998_13:44

USBD0P

26 AC97_USB+

26 AC97_USB-

0K

R1480K

R149

330KR147

R63

15K

R12

15K

15

R214

USBD1P

USBD1N

USBV1

14 USBP1P

14 USBP1N

USBV0

USBG1

USBG0

J3

C124

.001UFR11

15K

R14

15KC359

47PF

C202

68UF

C201

68UF

0.1UF

C12

0.1UF

C9

47PF

C358

15R211

470PF

C15

470PF

C14

C357

47PF 47PF

C13

C16

47PF

47PF

C8

47PF

C98

L10

L11

L9

F3

POLYSWITCH RUSB250

2.5A

R201560K

26 AC97_OC#

0KR146

14 USBP0N

14USBP0P

L23

47PF

C348

OC#014

USBV5

470KR72

R205

15

R204

15USBD0NR13

0KR15

0K

R_USBP0N

R_USBP0P

VCC5

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF 40

1.3

PROJECT:INTEL(R) 810

CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

USB-CON21

VCC1

8GND2

2 DATA1-

3DATA1+

4GND1

5VCC2

7 DATA2+

6DATA2-

6

7

5

4

3

2

8

1

+2

1+

12

12

12

1 2

122

1

VCC3_3

1 2

Do Not Stuff

2 - USB Stacked

possible to connector.Place CAPs as close as

USB Connectors

Do Not Stuff

Place R204, R205, C348, and C359 within 1" of ICH0

Place R214, R211, C357, and C358 within 1" of ICH0

PARALLEL PORT

212-22-1999_11:02

33

RP27

C91

180P

F

180P

F

C95

180P

F

C192

C196

180P

F

2.2K

R224

J5

16 SLCTIN#

16 PAR_INIT#

16 ALF#

16 STROBE#

PDR7

PDR0

PDR6

PDR5

PDR4

PDR3

PDR2

PDR116

PDR[7:0]

16 PE

16 SLCT#

16 BUSY

16 ACK#

180P

F

C197 C194

180P

F

C193

180P

F

180P

FC190

C189

180P

F

180P

F

C97 C94

180P

F

180P

F

C96

C90

180P

F

180P

F

C92

180P

F

C88

180P

F

C89

C93

180P

F

16 ERROR#

33

RP1533

RP16

2.2KRP28

2.2KRP17 RP13

2.2KRP14

2.2K

R_SLCTIN#

R_PARINIT#

R_ALF#

R_STROBE#

R_PDR1

R_PDR2

R_PDR3

R_PDR4

R_PDR5

R_PDR6

R_PDR7

R_PDR0

PARV5

1N4148

CR1

1

2

3

4 5

6

7

81

2

3

4 5

6

7

8

VCC5

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF 40

1.3

PROJECT:INTEL(R) 810

CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

3 4

5 6

7 8

99

87

65

43

2625

2423

2221

20

2

19

1817

1615

1413

1211

10

11

2

3

4 5

6

7

88

7

6

54

3

2

1

1

2

3

4 5

6

7

81

2

3

4 5

6

7

8

1 2 3 456788 7 6 5

4321 1 2 3 45678

1 2 3 45678

1 2 3 456788 7 6 5

4321 1 2 3 45678

1 2 3 45678

CA

Parallel Port Header

J5 Pinned Out for IDC (Flow Through) Ribbon Cable Connector

222-22-1999_11:02

SERIAL AND GAME PORTS

C374

1.0UF

DCD#0_C

RXD#0_C

TXD#0_C

DTR#0_C

RI#0_C

RTS#0_C

DSR#0_C

10KR230

R22947K

RI#016

16 RTS#0

CTS#016

16 TXD016 DTR#016 DSR#016 RXD#016

DCD#0

14 ICH_RI#

C310

100PF

C311

100PF

100PF

C309

C315

100PF

100PF

C313

C314

100PF100PF

C316

100PF

C312

CTS#116

U16

DSR#1_C

DCD#1_C

TXD#1_C

DTR#1_C

16 TXD116 DTR#116

DSR#1

16 DCD#1

16 RTS#1

RI#116

RXD#1_C

100PF

C326

100PF

C325 C327

100PF

100PF

C328

C329

100PF

100PF

C330

C368

100PF

C369

100PF

U17

CR15

47KR227

RTS#1_C

CTS#1_C

CTS#0_C

RI#_CR_C

RI#1_C

16 RXD#1

ICHRI#_C

Q10

J21

J19

VCC12

VCC12-

VCC3SBY

DA016

DA115

DA213

DY05

DY1 6

DY2 8

GND11

RA02

RA13

RA24

RA37

RA49

RY019

RY118

RY217

RY314

RY412

VCC20

VCC-12 10

VCC12 1

GD

7523

2

19

18

17

15

14

13

12

11

1

2

3

4

5

6

7

8

9

10

16

20

VCC5

VCC5

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF 40

1.3

PROJECT:INTEL(R) 810

CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

DA016

DA115

DA213

DY05

DY1 6

DY2 8

GND11

RA02

RA13

RA2 4

RA37

RA49

RY019

RY118

RY217

RY314

RY412

VCC20

VCC-12 10

VCC121

GD

7523

2

20

16

10

9

8

7

6

5

4

3

2

1

11

12

13

14

15

17

18

19

BAT54C3

2

1

VCC12

VCC12-

2N7002LT

1

G1

D

3

S

2

S

D

G

1

10

2

3

5 6

7 8

9

44

9

87

65

3

2

10

1

1

10

2

3

5 6

7 8

9

4

1

10

2

3

5 6

7 8

9

4

Serial Port/COM Headers

Place Close to Header

Place Close to Header

2nd COM Header OptionIf not populated at all, remove CR14and short RI#0_C to RI#CR

NOTE: If Wake from S3 onSerial Modem is not supporteddo not stuff CR15 and Q10.

COM1 and COM2 are 2x5 pin Headers for a cabled port.

J19 and J21 pinned out for IDC (Flow Through) Ribbon Cable Connector

232-22-1999_11:02

KEYBOARD/MOUSE/FLOPPYGAME PORTS

16MCLK

16MDAT

KDAT16

KCLK16

470PF

C176

J1BUTTON2 16

J1BUTTON1 16

J2BUTTON116

JOY2X 16

JOY2Y16

JOY1Y 16

JOY1X 16

J2BUTTON2 16

C182

47PF

0.01UF

C195

J7

C198

0.01UF 0.01UF

C191C199

0.01UF

C79

47PF

RP301K

2.2K

RP29

L2

0.1UF

C1

16 HDSEL#

16 WGATE#16 WDATA#

16 DIR#

16 STEP#

16 DSKCHG#

16 DRVDEN#0J14

16 DS#0

16 WRTPRT#

16 RDATA#

INDEX#16

16 DRVDEN#1

16TRK#0

16 MTR#0

C3

470PF 470PF

C4 C5

470PF 470PF

C2

RP31

1KSTACKED PS2 CONNECTOR

J1

1K

R143

L5

L4

L7

L6

4.7KRP1

L3F2

1.25A

MIDI_OUT16

MIDI_IN16

4.7K

R178R89

4.7K

47PF

C179 C178

47PF

R179

47

R88

47

C177

470PF

L1

L_MCLK

L_MDAT

L_KCLK

L_KDAT

PS2V5

PS2_PD

PS2GND

R_JOY1X

R_JOY1Y

R_JOY2Y

R_JOY2X

R_MIDIOUT

R_MIDIIN

PS2V5_F

VCC5 1

10

1112

1314

15162

34

56

78

99

87

65

43

2 1615

1413

1211

10

1

VCC5

VCC5

1 2 3 456788 7 6 5

4321

1

2

3

4 5

6

7

81

2

3

4 5

6

7

8

12

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF 40

1.3

PROJECT:INTEL(R) 810

CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

4

56

78

99

8 7

6 5

4

34 33

32 31

30

3

29

28 27

26 25

24 23

22 21

20

2

19

18 17

16 15

14 13

12 11

10

1

VCC5

1

2

3

4 5

6

7

81

2

3

4 5

6

7

8

1

10

11

12 13

14

15

16

17

2

3

4

5

6

7

8

9

PS

/2 K

ybd

PS

/2 M

se

13

14

15

16

17

12

11

10

9

8

7

6

5

4

3

2

1

VCC5

1 2

1 2

1 2

1 2

1 2 3 456788 7 6 5

4321

1 21 221

12

FLOPPY DISK HEADER

GAME PORT HEADER

KEYBOARD/MOUSE PORTS

J7 Pinned Out for IDC (Flow Through) Ribbon Cable Connector

245-26-1999_17:13

DIGITAL VIDEO OUT

24FPDV3

100P

F

C226

24 FTVREF

R1211K1K

R118

9,24 FTVSYNC9,24 FTHSYNC

FTBLNK#9,24

9,24 FTCLK19,24 FTCLK0

R1131K

253VHTPLG

4.7K

R126

9,24,253VFTSDA9,24,253VFTSCL

FTD[11:0]

9

FTD0

FTD1

FTD2

FTD3

FTD4

FTD5

FTD6

FTD7

FTD8

FTD9

FTD10

FTD11

25TXC-

25TXC+

25TX0-

25TX0+

25TX1-

25TX1+

25TX2-

25TX2+

R165400

1%

10UF

C281C275

100PF

L25

L27

100P

F

C27710

0PF

C276

10U

F

C28

2

C272

100P

F

100P

F

C271

1K

R11

6R

122 1K

C230

10U

F

0.01

UF

C22

8

EXTRS_PU

9,24SL_STALL

A1_PD

A2_PD

A3_PD

100PF

C280

L26

FPP1V3

24FPDV3

FPAV3

100P

F

C231

R1244.7K

TEST_PD

U7

PCIRST# 13,17,18,24,27

+2

1

VCC1_8

1212

VCC3_3

+2

1

VCC1_8

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF 40

1.3

PROJECT:INTEL(R) 810

CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

+2

1

12

VCC3_3

VCC3_3

PG

ND

17

AG

ND

020

AG

ND

126

AG

ND

232

AV

CC

023

AV

CC

129

CTL2/A2/DK27

D063

D162

D1051

D1150

D1247

D1346

D1445

D1742

D261

D2039

D2138

D2237

D2336

D360

D459

D558

D655

D754

D853

D952

DE2

GN

D0

16

GN

D1

48

GN

D2

64

HS4

IDCLK+57

IDCLK-56

18P

VC

C0

49P

VC

C1

TX0+25

TX0- 24

TX1+28

TX1-27

TX2+ 31

TX2-30

TXC+22

TXC- 21

VC

C0

1

VC

C1

12

VC

C2

33

VR

EF

3

VS5

D1841

D1940

D16/PFEN43

D1544

CTL3/A3/DK3 6

CTL1/A1/DK1 8

ISEL13

MSEN 11

PD10

EDGE/CHG 9

BSEL/SCL15

14DSEL/SDA

34TEST

35DKEN/RST

EXT_RS 19

FLAT PANELTRANSMITTER

SII154

5

3 33 12 1

21

22

30

31

27

28

24

25

34

49 18

17

10

11

13

56

57

4

64 48 16

19

9

14

35

2

52

53

54

55

58

59

60

36

37

38

39

61

40

41

42

43

44

45

46

47

50

51

62

63

6

7

8

15

29 23

32 26 20

Digital Video Out

U28, pin 3

Do Not Stuff

TEST pin may betied direct to GND

R124 is for Test Only

Place C226 near

Do Not Stuff R126

VIDEO CONNECTORS

2511-23-1998_13:44

QS4_3V

R105

R103

1N58

21

CR

7

2.2K

R75

24TX2-24TX2+24 TX1+

24 TX1-

24 TXC+

24TXC-

24TX0+

24TX0-

J8 C111

3.3PF

C109

3.3PF

3.3PF

C105

L_GREEN

3.3PF

C103

3.3PF

C106

3.3PF

C104

J6

MONOPU

3VHTPLG24

6 CK_SMBDATA 11,12,14,28,33SMBDATA

U6

9 3VDDCCL9 3VDDCDA

255VHSYNC

11,12,14,28,33SMBCLK

6CK_SMBCLK

R59

2.2K

R58

2.2K

9,24 3VFTSCL

9CRT_HSYNC

9CRT_VSYNC

3VFTSDA9,24

5VHTPLG 25

255VVSYNC

R120

R119

24,255VFTSCL

5VFTSDA 24,25

R67

751%

1%75

R69

R66

751%

C119

3.3PF

C102

3.3PF

9 VID_GREEN

L_RED

C101

10PF

C208

10PFC116

10PF

10PF

C112

L12

FUSE_5

L_HSYNC

L_BLUE

MON2PU

2.2KRP

34

255VDDCDA

5VFTSDA 24,25

4.7K

R11

5

3.3PF

C122

0.1U

F

C22

7

L_VSYNC

C100

3.3PF

0K

R64

5VDDCCL25

25 5VDDCDA

5VHTPLG25

C203

0.01

UF

C200

10U

F

1K

R65

0K

R71

CO

N_F

TS

CL

CO

N_F

TS

DA

CON_HTPLG

QSSDA

QSSCL

CR

T5V

_F

F1

2.5A

1K

R74

CR5

9 VID_BLUE

BLM11B750S

L19

L20

BLM11B750S

BLM11B750S

L21

CR9

CR6

25 5VVSYNC

25 5VHSYNC

24,255VFTSCL

255VDDCCL

CR10

CR8

VID_RED9

1N4148

CR4

VCC1_8

0K

0K

VCC5

-

+

C

A

VCC5

15

6 16

7 17

8 18

9 19

10 20

2 12

3

4 14

5

111

13

5

144

133

122

20

11

10

199

188

177

166

15

1

10

12

13

14

15

2

4

8

9

1

6

11

7

3

5 155

10

6

111

5

3

7

11

6

1

9

8

4

2

15

14

13

12

10

VCC5

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF 40

1.3

PROJECT:INTEL(R) 810

CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

BEA#

2B5

2B4

2B2

2B1

1B51A5

1B41A4

1B3

1A1

1A2 1B2

2A3 2B3

BEB#

1B1

2A5

VCC

2A1

2A2

2A4

1A3

GND

QST3384

12

7

21

17

14

24

22

2

13

1918

54

3

6

8 9

11 10

15

16

20

23

1

0K

0K

12

1 2 3 456788 7 6 5

4321

+2

1

122

1

BAT54S1

2

3

1 2

1 2

1 2

BAT54S1

2

3

BAT54S1

2

3

VCC5

VCC5

VCC5

BAT54S1

2

3

VCC1_8

BAT54S1

2

3

VCC1_8

C A

Protection Circuitfor 20V Tolerance

20 Pin Flat Panel Connector

is also populated.Populate if DFP Device

De-Bounce Circuit

Video Connectors

Do Not Populate

5V to 3.3V Translation/Isolation

VGA Connector

BLM11B750S is rated at 75Ohms at 100MHz

Place R66,R67,&R69 Close to VGA Connector

Do Not Stuff C119 and C122

Do Not Stuff C100 and C102

26

AUDIO/MODEM RISER

11-23-1998_13:44

20AC97_OC#

14,33AC_SDIN0

14AC_SYNC

AC97SPKR31

AC_RST#14

AC_BITCLK 14

20AC97_USB+

20AC97_USB-

14AC_SDOUT

AC_SDIN1 14,33

J18

VCC5

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF 40

1.3

PROJECT:INTEL(R) 810

CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

VCC3_3 VCC3SBY

VCC5 VCC12-

VCC12

AC’97_RISERAMR_CONNECTOR

KEY

KEY

KEY

KEY

+12VB9

B15 +3.3VD A15+3VDUAL/3VSBY

B11+5VD

+5VDUAL/5VSBYA7

-12VB7

A23AC97_BITCLK

B23AC97_MSTRCLK

B18AC97_RESET#

A21AC97_SDATA_IN0

A19AC97_SDATA_IN1

AC97_SDATA_IN2B21

AC97_SDATA_IN3B19

AC97_SDATA_OUTB17 A17AC97_SYNC

AUDIO_MUTE#B1 AUDIO_PWRDWN A1

(ISOLATED)B2

GND[0]

GND[10]A14

GND[11]A16

GND[12]A18

GND[13]A20

GND[14]A22

B8 GND[1]

GND[2]B10

GND[3]B12

B16GND[4]

B20GND[5]

B22GND[6]

A6GND[7]

GND[8]A9

A12GND[9]

MONO_OUT/PC_BEEPB3

A2MONO_PHONE

B4RESV[1]

RESV[2]B5

B13RESV[3]

B14RESV[4]

RESV[5] A3

A4RESV[6]

RESV[7]A5

A13S/P_DIF_IN

B6 PRIMARY_DN#

A10USB+

USB-A11

A8USB_OC A8

A11

A10

B6

A13

A5

A4

A3

B14

B13

B5

B4

A2

B3

A12

A9

A6

B22

B20

B16

B12

B10

B8

A22

A20

A18

A16

A14

B2

A1B1

A17B17

B19

B21

A19

A21

B18

B23 A23

B7 A7

B11

A15B15

B9

AUDIO/MODEM RISER

2711-23-1998_13:44

LAN

R163

619

619

R162

R153

100

C180

0.1UF0.1UF

C334

13,17,18,33 SERR#

13,17,18,27 AD20

13,17,18PCI_PME#

AD013,17,18AD[31:0]

AD1

AD2

AD31

AD30

AD29

AD28

AD27

AD26

AD25

AD24

AD23

AD22

AD21

AD20

AD19

AD18

AD17

AD16

AD15

AD14

AD13

AD12

AD11

AD10

AD9

AD8

AD7

AD6

AD5

AD4

AD3

13,17,18,33 IRDY#

13,17,18,33 TRDY#

17,18 PERR#

6 PCLK_5

13,33 PGNT#313,33 PREQ#3

13,17,18,33 PIRQ#A13,17,18

PAR13,17,18,33 STOP#13,17,18,33 DEVSEL#

13,17,18,33 FRAME#

28TDP

28TDN

28RDP

28RDN

PCIRST#7,13,15,16,17,18,19,24

25MHZ

Y2

28 L_SMBD28 L_SMBCLK

28 LAN_RST#

EESK

EEDO

EEDI

28ACTLED

28SPEEDLED

28LILED

0.1UF

C261

C331

22PF 22PF

C269 C265

0.1UF

0.1UF

C165

0.1UF

C257

0.1UF

C184

C_BE#0

C_BE#1

C_BE#2

C_BE#3

13,17,18 C_BE#[3:0]

5%

4.7K

R159

R_LANIDS

LAN_XTAL2

LAN_XTAL1

VIO

549

R156

R155

619

RBIAS10

RBIAS100

LAN_TEST

LANCLKRUN

62KR154

R152

4.7K

FLD5_PD

FLD6_PD

LANAPWR

U18

R164

3K

EECS

C255

4.7UF

C68

4.7UF

LAN_ISOLATE#28

U13

VCC3SBY

VCC3SBY

VCC3SBY

VCC3SBY VCC3SBY VCC3SBYVCC5

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF 40

1.3

PROJECT:INTEL(R) 810

CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

VCC3SBY

NC27

NC1 6

GND

5

EECS1

EESK2

EEDO4

EEDI3VCC

893C46

8

3

4

2

1

5

6

7

VCC3SBY

VCC3SBY+

12

+2

1

82559

A1NC1

NC2 H4

P14NC3

NC4 L8

D9NC5

NC6 P1

NC8 J4

A14NC9

NC10 G4

ACTLED C11

AD0N7

AD1M7

AD10N2

AD11M1

AD12M2

AD13M3

AD14L1

AD15L2

AD16K1

AD17E3

AD18D1

AD19D2

AD2P6

AD20D3

AD21C1

AD22B1

AD23B2

AD24B4

AD25A5

AD26B5

AD27B6

AD28C6

AD29C7

AD3P5

AD30A8

AD31B8

AD4N5

AD5M5

AD6P4

AD7N4

AD8P3

AD9N3

ALTRST#A9

C/BE0#M4

C/BE1#L3

C/BE2#F3

C/BE3#C4

CLKG1

CLKRUN# C8

CSTSCHG C5

DEVSEL#H3

EECS P7

FLA0/PCIMODE# J13

FLA1/AUXPWR J12

FLA10/MRING# N13

FLA11/MINT M12

FLA12/MCNTSM# M11

FLA13/EEDI P10

FLA14/EEDO N10

FLA15/EESK M10

FLA16 P9

FLA2 K14

FLA3 L14

FLA4 L13

FLA5 L12

FLA6 M14

FLA7 M13

FLA8/IOCHRDY N14

FLA9/MRST P13

FLCS# N9

FLD0 F14

FLD1 F13

FLD2 F12

FLD3 G12

FLD4 H14

FLD5 H13

FLD6 H12

FLD7 J14

FLOE# M8

FLWE# M9

FRAME#F2

GNT#J3

IDSELA4

INTA#H2

IRDY#F1

ISOLATE#B9

LILED A12

PARJ1

PERR#J2

PME# A6

RBIAS10 B14

RDN E14RDP E13

REQ#C3

RST#C2

SERR#A2

SMBALRT# B10

SMBCLKA10

SMBDC9

SPEEDLED B11

STOP#H1

TCK D14

TDN C14TDP C13

TEST A13

TEXEC D13

TO B12

TRDY#G3

VC

CP

L[0]

G13

VC

CP

L[1]

K13

VC

CP

L[2]

N8

VC

CP

L[3]

P12

VC

CP

P[0

]A

3

VC

CP

P[1

]A

7

VC

CP

P[2

]E

1

VC

CP

P[3

]K

3

VC

CP

P[4

]N

6

VC

CP

P[5

]P

2

VC

CP

TA

11

VC

C[0

]E

12

VC

C[1

0]J8 J9

VC

C[1

1]

VC

C[1

2]J1

0

J11

VC

C[1

3]

VC

C[1

4]K

4

K5

VC

C[1

5]

VC

C[1

6]K

6

K7

VC

C[1

7]

VC

C[1

8]K

8

K9

VC

C[1

9]

G5

VC

C[1

]

VC

C[2

0]K

10

K11

VC

C[2

1]

VC

C[2

2]L4 L5

VC

C[2

3]

VC

C[2

4]L9

VC

C[2

5]L1

0

VC

C[2

]G

6

H5

VC

C[3

]

VC

C[4

]H

6

H7

VC

C[5

]

VC

C[6

]H

8

J5V

CC

[7]

VC

C[8

]J6 J7

VC

C[9

]

VIOG2

VS

SP

L[0]

G14

VS

SP

L[1]

K12

VS

SP

L[2]

P8

VS

SP

L[3]

N12

VS

SP

P[0

]B

3

VS

SP

P[1

]B

7

VS

SP

P[2

]E

2

VS

SP

P[3

]K

2

VS

SP

P[4

]M

6

VS

SP

P[5

]N

1

VS

SP

TC

10

VS

S[0

]D

4

E8

VS

S[1

0]

VS

S[1

1]E

9

E10

VS

S[1

2]

VS

S[1

3]E

11 F4

VS

S[1

4]

VS

S[1

5]F

5

F6

VS

S[1

6]

VS

S[1

7]F

7

F8

VS

S[1

8]F

9V

SS

[19]

D5

VS

S[1

]

F10

VS

S[2

0]

VS

S[2

1]F

11 G7

VS

S[2

2]

VS

S[2

3]G

8

G9

VS

S[2

4]

VS

S[2

5]G

10

G11

VS

S[2

6]

VS

S[2

7]H

9

VS

S[2

8]H

10

VS

S[2

9]H

11

VS

S[2

]D

6

VS

S[3

0]L6

VS

S[3

1]L1

1

D7

VS

S[3

]

VS

S[4

]D

8

D11

VS

S[5

]

VS

S[6

]E

4

E5

VS

S[7

]

VS

S[8

]E

6

VS

S[9

]E

7

X1N11

X2P11

VREF C12RBIAS100 B13

D12TI

D10NC11

L7NC7 L7

D10

D12

B13

C12

P11

N11

E7

E6

E5

E4

D11D8

D7

L11L6D6

H11

H10H9

G11

G10G

9

G8

G7

F11

F10D5 F9

F8

F7

F6

F5

F4

E11

E10E9

E8

D4

C10 N1

M6

K2

E2

B7

B3

N12P8

K12

G14

G2

J7J6J5H8

H7

H6

H5

G6

L10

L9L5L4K11

K10

G5

K9

K8

K7

K6

K5

K4

J11

J10

J9J8E12

A11

P2

N6

K3

E1

A7

A3

P12

N8

K13

G13

G3

B12

D13

A13

C13

C14

D14

H1

B11

C9

A10

B10

A2

C2

C3

E13

E14

B14

A6

J2

J1

A12

B9

F1

H2

A4

J3

F2

M9

M8

J14

H12

H13

H14

G12

F12

F13

F14

N9

P13

N14

M13

M14

L12

L13

L14

K14

P9

M10

N10

P10

M11

M12

N13

J12

J13

P7

H3

C5

C8

G1

C4

F3

L3

M4

A9

N3

P3

N4

P4

M5

N5

B8

A8

P5

C7

C6

B6

B5

A5

B4

B2

B1

C1

D3

P6

D2

D1

E3

K1

L2

L1

M3

M2

M1

N2

M7

N7

C11

G4

A14

J4

P1

D9

L8

P14

H4

A1

LAN

Do Not Stuff

Distribute aroung PowerPins Close to 82559.

LAN Decoupling

Close to Ball A10Place C68/C255

LAN

2811-23-1998_13:44

27LAN_ISOLATE#

PWROK14,29,32

4.7KR186

4.7KR215

R108

330 330

R145

75

R109R106

7575

R110

50R161R160

5050R158

C268

0.1UF0.1UF

C266

27 RDN

J9

14,32 RSMRST#

27LAN_RST#

14 GPIO28

GPIO2714

L_SMBD 27

27L_SMBCLK

11,12,14,25,33 SMBDATA

11,12,14,25,33 SMBCLK

JP8

27 RDPJP12

TDP27

27 TDNJP7

27,28 LILED

AC

T_C

R

27,28 SPEEDLED

75

R107 C213

0.1UF

470PF-1500V

C210

R151

R150

TD

C

RJMAG_CONN

JP9_SMBD

JP8_SMBC

50R157

TD_PD RD_PD

RJ4

5_P

D

RJ7

8_P

D

RX

C_P

D

TX

C_P

D

JP7_

PU

JP11

330

R144

JP18

_PU

JP23

_PU

JP10

JP9

RD

C

C212

0.1UF

LI_CR

330

R111

ACTLED27,28

ACTLED 27,28

LILED 27,28

SPEEDLED 27,28

SUS_STAT#14

R112

330

0K

R210

0K

R198

VCC3SBY

RJMAG

17S

HLD

118

SH

LD2

10 TD+

TD-12

9 RD+

RD-7

RJ-45

6 RJ-5

RJ-73

RJ-84

15

16

13

14

1T

XC

RX

C2

11T

DC

8R

DC

RJ-

45

811

21

14

13

16

15

4

3

6

5

7

9

12

10

1817

1

2

33

2

1

VCC3SBY

VCC3SBY

VCC3SBY

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF 40

1.3

PROJECT:INTEL(R) 810CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

0K

0K

1

2

3

1

2

3

1

2

33

2

1

use plane for this signalNote: Chassis Ground,

LAN

Do Not Stuff

Note: Chassis Ground,use plane for this signal

Place Termination near 82559

Default Config:

Do Not Stuff

Do Not StuffFor EST Testing

Note: This circuit is for debug purpose only.

Do Not Stuff R198

ICH0 1-2 DefaultICH 2-3

Select JP8/JP9

Normal 1-2 DefaultDisable 2-3

LAN DISABLE - JP10

2911-23-1998_13:44

VOLTAGE REGULATORS

C173

1200UF 1200UF

C375

R57

2401%

240

R561%

1%R55

301

10K

R87

0K

R83

U4

14,32 SLP_S3#

28,32PWROK

V_GQ6

4.7K

R61

MM

BT

3904

LT1

Q7

PLANE_CTL1

VR3

LT1587-1_5

VR5

VR4

1N5822

CR2

VR2

0.1UF

C65

Q9

Q8

C43

1.0UF

C57

1.0UF

C71

22U

F-T

AN

T

100U

F-T

AN

T C76

100U

F-T

AN

T C59

100U

F-T

AN

T

C159

22U

F-T

AN

T

C74

100U

F-T

AN

T C270

100U

F-T

AN

T C225

47UF

C75

47UF

C174

VR1_ADJVR5_ADJ

U5

PLANE_CTL0PCTL_IN

Q5

Q6

130

R541%

+1

2

+1

2

V3SB

74LS132 VCC

GND7

14

32

1

VTT1_5VCC3_3

VCC2_5

VCC5SBY

VCC3SBYVCC5SBY

B 13

C

2

EE

C

B

VCC12

VCC5VCC1_8VCC5SBY VCC3_3V3SB

VCC3_3 VCC3SBY

VIN3

2VOUT

1ADJ

LT1587ADJ

2

3

1

VIN3

2VOUT

1ADJ 1

2

3

1

GND

IN3

OUT2

LT1117-3_3

3 2

CA

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF 40

1.3

PROJECT:INTEL(R) 810

CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

VIN3

2VOUT

1ADJ

LT1587ADJ

1

2

3

SI4410DY

8

7

6

54

3

2

11

2

3

4

8

7

6

5

SI4410DY

8

7

6

54

3

2

1

5

6

7

8

4

3

2

1

+2

1

+2

1 +2

1

+2

1 +2

1

+2

1

+2

1

+1

2

+2

1

SN74LVC07AGND

VCC

14

7

1 2

NDS356AP

GG

D

D

S

S

S D

G

NDS356AP

GG

D

D

S

S

G

DS

Voltage Regulators

VCC 2.5 VOLTAGE REGULATOR

VTT 1.5V VOLTAGE REGULATOR

the Regulator

VCC 1.8 VOLTAGE REGULATOR

Do Not Populate

Place C76 at

VCC 3.3VSB Regulator

VCC 3.3V Standby VOLTAGE SWITCHThis generates 3.3V Standby Power which ison in S0,S1,S3,S4,&S5. It passes 3.3V fromthe ATX supply in S0/S1, and 3.3VSB (generatedby VR2 below) in S3/S4/S5.

SN74LVC07A has 5V input and output tolerance.

Place C159 at the Regulator

302-22-1999_11:02

VRM 8.4

PV

12

R_VID2

R_VID1

R_VID0

L8

1.0U

H-6

.8A

C31

2700

UF

Q2

Q4

C128

2700

UF

2700

UF

C28

R19

20

220

R33

OUTEN

JP5JP2 JP3 JP4

5.6K

R18

0.1UF

C147

150PF

C18

10K

R17

220PF

C35

Q3

Q1

2700

UF

C54C58

2700

UF

0.1UF

C19

L14

0.8UH-20A

1200UF

C30

1200UF

C26C22

0.1UF 10UF

C27

C25

1.0UF

C24

1.0UFFAULT#_PU

VRM_PWRGD 32

G1

G2

L_VCCVIDR_VCCVID

VFB_PD

SS_PD

VRCOMP_PD

R_V

RC

OM

PR16

8.2K

0.01UF

C17

VR1

3VID[3:0]

VID0

VID1

VID2

VID3

R22

5.1

C21

1.0UF

0.01UF

C20R20

2.7K

IMAX

5VIN

R_VID3

RP4

0K

C29

1200UF 1200UF

C7

+1

2

G1

4

S1

1

S2

2

S3

3

D1

8

D2

7

D3

6

D4

5

SI4410D

Y

4 123

8765G

14

S1

1

S2

2

S3

3

D1

8

D2

7

D3

6

D4

5

SI4410D

Y

5 6 7 8

3 2 14

+1

2

+1

2

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF 40

1.3

PROJECT:INTEL(R) 810

CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

VCC3_3

VCCVID

VCC5

G1

4

S1

1

S2

2

S3

3

D1

8

D2

7

D3

6

D4

5

SI4410D

Y

4 123

8765G

14

S1

1

S2

2

S3

3

D1

8

D2

7

D3

6

D4

5

SI4410D

Y

5 6 7 8

3 2 14

+1

2

+2

1

VCC5

+2

1

+1

2

+2

1

LTC1753 6S

EN

SE

9S

S

4S

GN

D

3G

ND

VC

C

5

PV

CC

2

CO

MP

10

VID414

VID315

VID216

VID117

VID018

OUTEN19 IMAX 7

13PWRGD

FAULT# 12

G120

G21

8IFB

11VFB

11

8

1

20

12

13

719

18

17

16

15

14

10

25

349 6

VCC12

1

2

3

4 5

6

7

88

7

6

54

3

2

1

+1

2

+1

2

VID Override Jumpers

Close to FETs

Place CAPs

The LTC1753 incorporates internal pull-ups on VID[4:0].If your VR IC does not incorporate these, they mustgo on the motherboard.

Refer to VR Supplier for Layout Guidelines

Processor Voltage Regulator

Do Not Stuff C147

3111-23-1998_13:44

SYSTEM, PART 1

R17

2

4.7K

330

R188

2.2K

R235

10K

R93

10K

R136

R228

470

R225

0K

1M

R226

R232

220

68

R233

C378

0.1UF

KEYLOCK#16

J25J27

J24

Q11

JP22

14 ICH_SPKRSP1

J20

26 AC97SPKR

16 TACH2

16 PWM2

J26

16 TACH1

16 PWM1

82

R212

4.7K

R213IRTX16

4.7K

RP

62

IRRX16

19 IDEACTP#

U11

14 PWRBTN#

U11

19 IDEACTS#

IDE_ACTIVE

68

R234

C29

2

10U

F16

V

10K

R231

0.1UF

C23

C258

470PF

0.1UF

C365

0.1UF

C363

0.1UF

C362

U5U5

14GPIO26_FPLED

R21

7

100K

R97

330

14GPIO23_FPLED

330R98

CR3

CR

12

C27

9

0.1UF

C370

1.0UF

C373

470PF

SPKR_NEG

R_SPKRIN

SPKR

SPKR_IN

SPKR_Q1G

FP

_PD

R_IRTX

PWRLED

V3S

BLE

D

GP26LEDGP23LED

PBTN_IN

SW2

VCC3SBY

1

2

33

2

11

2

3

1

2

3

1

2

3

1

2

3

2N39

04

B 13

C

2

EE

C

B

VCC5

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF 40

1.3

PROJECT:INTEL(R) 810

CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

1

2

33

2

1

2NEG

1 POS+

1

2

FNT_PNL_CONN

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

3

4

5

6

7

8

9

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

VCC12VCC12

VCC12VCC12

VCC3_3

1

2

33

2

1

VCC3_3

12345 6 7 88765

4 3 2 1

SN74LVC07AGND

VCC

3

7

4

14

SN74LVC07AGND

VCC

14

2

7

1

VCC5

VCC5

VCC3SBY

+2

1

VCC5 VCC5 VCC3_3 VCC3_3 VCC3_3

SN74LVC07AGND

VCC

5

7

6

14

SN74LVC07AGND

VCC

14

4

7

3

VCC3SBY VCC3SBY

VCC3SBY VCC3SBY

211 2

12

PBSWITCH

1 2

3 443

21

Standby Well is on to preventOn-Board LED indicates the

KEY

KEY

KEY

KEY

KEYSPEAKER

KEYLOCK

H.D. LED

POWER SW.

INFRARED

ICH has internal pullup and debounce on PWRBTN#

Speaker Circuit

SYSTEM

FAN Headers

No stuff.For test only

No stuff.For test only

POWER LEDKEY

Hot-Swapping Memory.

3212-6-1998_12:54

SYSTEM, PART 2

RST_PD

R868.2K

C183

1.0UF

1M

R196

R142

22K

1M

R199

R200

4.7K

330

R10

C45

0.01UF

22

R24

R62

4.7K

R90

0K

240

R99

14,28RSMRST#U12

U3

U3

U3

4PWRGOOD

U4

U12

4 DBRESET#

U12

U12

10UF

C185

30 VRM_PWRGD

5VPSON

PWROK#ATX_PWOK

APOK_STDBRST

ST23

ST69

J4

0K

R91

32DBRPOK

C264

1.0UF

V3RSMRST

U10

DBRPOK_DLYSLP_S3#

14,32R92

0K

U10

14,29,32 SLP_S3#

CK_PWRDN# 632 DBRPOK

PWROK 14,28,29

R84

0K

CK_PWRD

SW1

JP23

74LVC14A

14

7

89

SN74LVC06AGND

VCC65

14

7

VCC3SBY

SN74LVC06AGND

VCC43

14

7

SN74LVC06AGND

VCC21

14

7

VCC5SBY

VCC3SBY

VCC3_3

VCC_5-

VCC3SBY

VCC3SBY

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF 40

1.3

PROJECT:INTEL(R) 810

CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

VCC3SBY

VCC5SBY

74LS132 VCC

GND7

14

65

4

VCC5

VCC5SBY

VCC2_5

74LVC14A

14

7

21

VCC3SBY

VCC3SBY

74LVC14A

14

7

65

74LVC14A

3 4

7

14

VCC3SBY

+2

1

VCC12-

VCC12

ATX

3_3V11

-12V

GND13

PS_0N

GND15

GND16

GND17

-5V

5V19

5V20

3_3V1

3_3V2

GND3

5V4

GND5

5V6

GND7

PW_OK

5VSB

12V 10

9

8

7

6

5

4

3

2

1

20

19

18

17

16

15

14

13

12

11

SN74LVC08A

2

13

7

14

VCC3SBY

VCC3SBY

SN74LVC08A

14

7

64

5

PBSWITCH

1 2

3 443

21

Place JP23 Near Front Panel Header (J20)

Do Not StuffFor Debug Only

For Debug OnlyDo Not Stuff

SYSTEMPower Connector and Reset Control

Schmitt Trigger Logicusing a 22msec delay

Resume Reset Circuitry

Power Good Circuit

ITP RESET CIRCUIT - FOR DEBUG ONLY

220 Ohm Pull-up to 3.3V is on VRM Sheet

SN74LVC06A has 5V input tolerance

74LVC14A is 5V input tolerant

SN74LVC06A is 5V output tolerance

CLOCK POWERDOWN CONTROL

Reset Button

Do Not Stuff R84 - For Test Only:If R84 is Populated, R86 Must Be De-Populated

Do Not Stuff C183

33

PULLUP/PULLDOWN RESISTORS

5-26-1999_17:09

PCPCI_REQ#A13,18

RP60

4.7K

RP49

150

U11

U11

U11

R166

10K R170

10K

IRQ1513,19

13,19 IRQ14

150

R6

110, 1%

R70

PU1_ACK64#17PU1_REQ64#17PU2_ACK64#17PU2_REQ64#17

4 SLEWCTRL

4 RTTCTRL

17 SDONEP1

17 SDONEP2

17SBOP1

17 SBOP2

PTMS17,18

PTDI17,18

18 SBOP318 SDONEP3

PU3_ACK64#18

PU3_REQ64#18

13,17,18,27 SERR#

13,17,18 PLOCK#

13,17,18,27STOP#

13,17,18,27 DEVSEL#

13,17,18,27 TRDY#

13,17,18,27 IRDY#

13,17,18 PIRQ#D

13,17,18 PIRQ#C

13,17,18 PIRQ#B

13,17,18,27 PIRQ#A

18 PERR#_PU

13,18 PREQ#2

13,17 PREQ#1

13,27 PGNT#3

13,17 PGNT#0

13,17PGNT#1

13,18 PGNT#2

13,27 PREQ#3

13,17,18,27 FRAME#

13,17 PREQ#0

4,13 APICD0

4,13 APICD1

2.7K

RP59

RP45

2.7K

RP47

5.6K

5.6K

RP58

RP51

2.7K

150

R73

RP55

8.2K

R207

2.7K

R208

2.7K

14,26AC_SDIN0

14,26 AC_SDIN1

U12

U12

U3

U3

U10

U10

U4

U4

U5

U5

U5

RP57

8.2K

RP54

8.2K

RP53

8.2K

150

RP50

RP56

8.2K

RP52

8.2K

RP61

4.7K

13,16 A20GATE

A20M#4,13

4,13 CPUSLP#

4,13 FERR#

13 GNT#B/GPIO17

14,18 GPIO21

14 GPIO22

14,18GPIO7

IGNNE#4,13

INIT#4,13,15

4,13 INTR

14 INTRUDER#

14,16 LPC_PME#

14,16 LPC_SMI#

NMI4,13

13,16 RCIN#

13 REQ#B/GPIO1

13,16,18 SERIRQ

GPIO1314

14SMBALERT#

SMBCLK11,12,14,25,28

LDRQ#114GPIO1214

SMBDATA11,12,14,25,28

SMI#4,13

STPCLK#4,13

THERM#14

R68

110, 1%

VC

MO

S

4,33

150

R169

1

2

3

4 5

6

7

88

7

6

54

3

2

1

1

2

3

4 5

6

7

81

2

3

4 5

6

7

8

VCC5SBY

VCC3_3

SN74LVC07AGND

VCC

13

7

12

14

SN74LVC07AGND

VCC

14

10

7

11

SN74LVC07AGND

VCC

9

7

8

14

VCC3SBY

VCC5

VCC5

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF 40

1.3

PROJECT:INTEL(R) 810

CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

RESISTOR PAK9 PULLUP/DOWN

1

10

3

2

9

8

7

6

5

4

RESISTOR PAK9 PULLUP/DOWN

1

10

3

2

9

8

7

6

5

4

VCC5

1

2

3

4 5

6

7

81

2

3

4 5

6

7

8

1

2

3

4 5

6

7

88

7

6

54

3

2

1

1

2

3

4 5

6

7

81

2

3

4 5

6

7

8

VCC5

VCC5

VCC5

1

2

3

4 5

6

7

88

7

6

54

3

2

1

74LVC14A

14

7

1011

74LVC14A

13 12

7

14

SN74LVC06AGND

VCC1011

14

7

SN74LVC06AGND

VCC

7

14

13 12

VCC3SBY

SN74LVC08A

14

7

89

10

SN74LVC08A

13

1211

7

14

74LS132 VCC

GND

12

1311

14

7

VCC3SBY

74LS132 VCC

GND7

14

810

9

VCC3SBY

SN74LVC07AGND

VCC

14

8

7

9

SN74LVC07AGND

VCC

11

7

10

14

SN74LVC07AGND

VCC

14

12

7

13

VCC3_3

1

2

3

4 5

6

7

81

2

3

4 5

6

7

8

1

2

3

4 5

6

7

81

2

3

4 5

6

7

8

1

2

3

4 5

6

7

88

7

6

54

3

2

1

1

2

3

4 5

6

7

88

7

6

54

3

2

1

1

2

3

4 5

6

7

88

7

6

54

3

2

1

1

2

3

4 5

6

7

81

2

3

4 5

6

7

8

1

2

3

4 5

6

7

81

2

3

4 5

6

7

8

VCC3_3

VCC3SBY

CPUICH0

For Future Compatibility Upgrade

UNUSED GATES

PULL-UP RESISTORS AND UNUSED GATESPCI BUS

34

VRM DECOUPLING

12-8-1998_14:04

22UF

C384

1.0UF

C118 C113

1.0UF

C142

1.0UF1.0UF

C121 C120

1.0UF

0.1UF

C33 C34

0.1UF 0.1UF

C129 C11

0.1UF

C32

0.1UF

C133

0.1UF 0.1UF

C144 C150

0.1UF 0.1UF

C157

0.1UF

C218

0.1UF

C220 C219

0.1UF 0.1UF

C205 C221

0.1UF

C134

1.0UF

C143

1.0UF1.0UF

C141C108

1.0UF1.0UF

C151C138

1.0UF

C137

1.0UF1.0UF

C132C135

1.0UF1.0UF

C148

1.0UF

C156

1.0UF

C154C107

1.0UF1.0UF

C145C149

1.0UF

C125

4.7UF 4.7UF

C152 C136

4.7UF 4.7UF

C117 C110

4.7UF 4.7UF

C115 C153

4.7UF 4.7UF

C146 C126

4.7UF 4.7UF

C139 C155

4.7UF

C140

4.7UF

C42

0.1UF

+2

1

VTT1_5

VCCVID

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF 40

1.3

PROJECT:INTEL(R) 810

CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

VCCVID

0603 Package placed within 200mils of VTT Termination R-packs

0805 Package

1206 Packages

370-pin Socket Decoupling

Bulk Decoupling

High Frequency Decoupling

VCCVID Decoupling

VTT DecouplingOne Capacitor for every 2 R-Packs

Place in 370 PGA Socket Cavity

355-26-1999_17:09

DRAM, ICH, AND GMCH DECOUPLING

0.01UF

C262

0.01UF

C169

0.01UF

C170

0.01UF

C383

0.01UF

C380

C318

0.1UF0.1UF

C340

0.1UF

C172 C240

0.1UF 0.1UF

C338C127

0.1UF 0.1UF

C322

0.1UF

C78

0.1UF

C250C285

0.1UF 0.1UF

C339C354

0.1UF0.1UF

C283

C81

0.1UF

C72

0.1UF

C87

0.1UF

C67

0.1UF0.01UF

C305C381

0.1UF

22UF

C188

C163

0.1UF0.1UF

C215

0.1UF

C382C239

0.1UF0.1UF

C130

0.1UF

C73

0.1UF

C253C77

0.1UF

C175

0.1UF

C181

0.1UF0.1UF

C254C248

0.1UF

0.1UF

C223C252

0.1UF0.1UF

C251

0.1UF

C232C247

0.1UF 0.01UF

C308 C171

0.1UF

C288

0.1UF0.1UF

C278C350

0.1UF0.1UF

C343

C233

0.01UF

C242

0.01UF 0.01UF

C237

0.01UF

C214

0.01UF

C131

0.01UF

C164

0.01UF

C304 C41

0.01UF

C289

0.01UF

C263

0.1UF

C303

0.1UF

22UF

C162

C260

0.1UF 0.1UF

C245

C341

0.1UF

0.1UF

C66 C360

0.1UF

0.1UF

C244 C243

0.1UF

C249

0.1UF

0.1UF

C83C82

0.1UF

0.1UF

C352 C298

0.1UF 0.1UF

C291 C160

0.1UF 0.1UF

C376 C320

0.1UF 0.1UF

C256

10UF

C44

C273

10UF

C286

10UF

C319

0.1UF 0.1UF

C307 C295

0.1UF 0.1UF

C296

0.1UF

C10 C345

0.1UF

C332

0.01UF

2.2UF

C372

0.1UF

C86

22UF

C70C85

22UF

C62

22UF

22UF

C69

22UF

C84

C317

0.1UF0.1UF

C80 C324

0.1UF0.1UF

C333

0.1UF

C367

0.1UF

C321

0.1UF

C234

C377

0.01UF

VCC3SBY

VCC3_3

VCC3_3

VCC3SBY

VCC1_8

VCC3_3VCC1_8

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF 40

1.3

PROJECT:INTEL(R) 810

CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

VCC3_3

VCC3SBY

+1

2

VCC1_8

+2

1

VCC5 VCC_5-

VCC3_3

+1

2

+2

1

+1

2

+2

1

+2

1

+2

1

+1

2+1

2

+2

1

VCC12-VCC12

VCC3SBY

GMCH 3.3V IO Decoupling:

GMCH Decoupling Display Cache Decoupling

of both SDRAM components.

Distribute near the power pins

DRAM, CHIPSET, and BULK POWER DECOUPLING

Distribute near the VCCSUSpower pins of the ICH0.power pins of the ICH0.

Distribute near the 1.8V

if they fit.and 2 on opposite sides close to componentPlace 1 .1uF/.01uF pair in each corner,

ICH0 3.3V Plane Decoupling:

Distribute near DIMM1 Power Pins.DIMM1 Decoupling:

Distribute near DIMM0 Power Pins.DIMM0 Decoupling:

ICH0 Decoupling

System Memory Decoupling Bulk Power Decoupling

3 VOLT Decoupling

Place 1 .1uF/.01uF pair in each corner,GMCH Core Plane Decoupling:

and 2 on opposite sides closeto component if they fit.

Place near GMCH Display Cache Quadrant

Distribute as close as possible toGMCH System Memory Quadrant

3611-23-1998_13:43

REVISION HISTORY, PART 1

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF 40

1.3

PROJECT:INTEL(R) 810

CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

Revision History (Changes from Rev 0.7)Sheet Description Sheet DescriptionALL Cosmetic changes to all pages (Re-names nets, re-organized symbol arrangement, etc.) 10 Ganged the tw o CKEs of f of one 4.7K Pull-Up to 3.3V.

4 Changed FB1 (ferrite bead for PLL analog isolation) to Inductor L2. 11 Fixed Symbol PinoutChanged value of R36 to 10 ohms. 12 Fixed Symbol PinoutReplaced R21-R23 w ith 1K R-pack (RP50). Replaced R24-26 and R34 w ith RP44. Removed SMBUS pullups f rom this page. There are pullups on page 32.

Changed R184 value to 220 ohms Removed Reset Straps f rom MD lines.

Changed Pull-Up/Dow n Resistor Values on signals to ITP interface and grouped into Rpacks/Discretes to make true populate/de-populate Mfg. Option. 13 Updated BalloutFloated THERMTRIP# Signal Changed C172 to 0.1UF Cap (HUBREF decoupling)Generate GTLREF w ith 1% resistors. Move f rom page 5 to page 4. Added Resistor Site to Pull F16 to GND for test/debug.

Changed BR0# Pull-Dow n to 56Ohm to use existing GTL Term Rpack Slot on sheet 5 14 Updated BalloutAdded Jumper Test Option to GND BSEL line. Routed PME# and SMI# to GPIO[13:12] respectively to support w ake events f rom S1.

Change R35 f rom 51Ohm, 1% to 51Ohm, 5% Pull RTCRST# signal f rom input node of f irst RC delay rather than output node (just other side of diode).

Added VCMOS Decoupling Moved Clear CMOS to RTCRST# signal and Added 1K resistor to GND on pin 3 of jumper.

6 Changed VDDA (pin22) of CK-Whitney to 3.3V Supply pet 0.5 Spec. Change RTC Circuit to pow er Vbias straight f rom positive terminal of battery (BAT1). Was charged f rom VCCRTC input.

Added/Modif ied Decoupling and Pow er Isolation Changed AC_SYNC pull-dow n strap (CPU Safe Mode Jumper JP14) to AC_SDOUT pull-up strap.

Ganged CPU and GMCH Clock Lines Change C8 and C9 to 12pF caps.

Isolated USB/DotCLK pow er (pin 27) f rom SDRAM pow er Tied OC#0 and OC#1 together.

Changed Pow erDow n control signal to NAND of SLP_S3# and PWR_OK Add jumper straps to SPKR and AC_SYNC

Change C146 and C147 f rom 10pF to 12pF Remove Pull-up f rom SLP_S3# signal

7 Updated GMCH BallOut 15 Updated FWH pinout and labelled symbol as a TSOP Socket.Changed GTLREF divider to 1% resistors and GTLREF Decoupling to a 0.1uF (C2) and 0.001UF (C72) in parallel

Updated FWH (Socket) Symbol to include FGPI[4:0], routed ATA66 cable detect to GPI[1:0] and pulled rest dow n through 8.2K.

8 Updated GMCH BallOut Cominbed Decoupling Caps and reduced to appropriate amount.

HUBREF Generated f rom tw o 1% resistors w ith 0.1uF (C171) at GMCH HUBREF pin. Changed JP4 to a 2 pole instead of 3 pole jumper.

Changed C3 to 20pF Cap Replace discrete resistors w ith R-packs. Replaced R84-87 w ith RP42.

Decoupled System Memory 3.3V balls f rom Local Memory 3.3V balls. System Memory quadrant connects to 3.3Vsb plane and Local Memory connects to 3.3V plane.

16 Updated Pinout. Connected new VREF pin to 5V. Added Decoupling to IRRX/IRTX lines.

9 Updated GMCH BallOut Routed PME# and SMI# to GPIO[13:12] respectively to support w ake events f rom S1.

Connected VCCDACA and VCCDA signals to 1.8V through f iltering circuitry. Connected VSSDACA and VSSDA to Digital GND.

Routed Game Port to game port header, 2nd Serial Port to serial header, PWM/Tach signals to fan headers, and unused signals to test header.

Added Reset Strap jumpers to LMD[31:26]. Routed Unused GPIOs signals to test header.

Added Oscillator to DotCLK for Test/Debug option Removed JP6 and Grounded CLOCKI.

Connected Digital Video Out signals Connected VTR to VCC3.3 (removed f rom VCC3SB w ell) and added pow er decoupling.

Changed R70 to 33Ohm and C4 to 20pF. Pulled SYSOPT pin dow n to GND through 4.7K resistor. Moved Keylock pull-up sheet 31.

3711-23-1998_13:43

REVISION HISTORY, PART 2

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF 40

1.3

PROJECT:INTEL(R) 810

CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

Revision History (Changes from Rev 0.7)

Sheet Description Sheet Description17 Changed device num ers (IDSEL wiring) for s lots to AD16, AD17, and AD22.

Routed additional s ignals required to AD22 s lot to s upport ISA bridge tes t card.27 Changed 93C46 Pinout.

18 Changed device num ers (IDSEL wiring) for s lots to AD16, AD17, and AD22. Routed additional s ignals through 0K res is tors to AD22 s lot to support ISA bridge tes t card.

28 Replaced RJ45 connector and discrete m agnetics with integrated RJ45/m agnetics part and connected accordingly.

Added Jum per to route PERR# to ICH/ICH0 if ICH is populated. Added LAN Dis able Jum per.19 Connected pin 34 of each connector to P66DETECT and S66DETECT(FWH_GPI0

and FWH_GPI1 respectively).Added ICH/ICH0 s calability jum pers .

Buffered PCIRST# s ignal going to pin 1 of IDE connectors to isolate cable loading. 29 Moved Power Connector to Sheet 32Rem oved Series Term inations from IRQ lines (pulled into ICH0). Replaced old VCC5dual circuit, with VCC3Sby Circuit which generates s upply for

devices which m us t s tay powered in S3. Rem oved LT1585-3.3 (U36 on rev0.7).20 Is olated each VCC input to USB s tacked connector through dedicated filtering

circuitry.Changed U27 from LT1585-1.5 to LT1587-1.5 and changed discretes .

Added 47pF EMI caps on USB data lines . Added V3SB regulator (generated V3SB from V5SB from ATX power supply).Connect USB through Audio/Modem Ris er through 0K res is tors . Changed 1.8V Regulator des ign from LT1585ADJ to LT1587ADJ and changed

discretes .Make OC detect circuitry unique to each port and update polyfuse value. Changed 2.5V Regulator des ign from LT1585ADJ to LT1587ADJ and changed

discretes .21 Replaced DB25 connector w ith 2x13 header s o we can cable out. SMB 30 Added VRM Override Jum pers to VID bus .

Rem oved Series Term ination Res is tors from Ack# and Bus y# s ignals . Change VR Des ign to VRM8.4 com pliant des ign. Us e LTC1753 per Linear App Note.

Changed Pull-ups to 2.2K 31 Moved Reset and Power circuitry to sheet 3222 Added 2nd s erial port and connected both through 2x5 headers to cable out

(Rem oved 1 DB9 Connector).Added Infrared, Power Switch, Hard Drive/Power LEDs , Keylock, and Speaker Circuitry to Com m on Sys tem Header.

Added dis crete s olution to level trans late and route Ring Indicate from Serial ports to ICH for Wake from S3 on serial m odem .

Added 12V Fan Headers (2 supporting TACH outputs , and 2 support PWM inputs ).

23 Added MIDI/Gam e Port circuitry connected through 2x8 header to cable out. Added Debug LED to m onitor 3.3VSBY PlaneIncreas ed Cap values on Keybd/Mouse lines from 100pF to 470pF. 32 Moved Pull-ups to sheet 33.Changed the keyboard and m ous e s ym bols to a PS/2 s tacked connector. 32 Updated new PWROK/PWRGOOD Generation, RESET, RSMRST# circtuitry.

25 Changed RGB PI filter caps from 22pF to 3.3pF. 33 Pulled-Up SMBUS interface to 3.3VSby ins tead of 3.3V.Added Quick Switch to level trans late the CRT Sync, CRT DDC, and Flat Panel DDC Signals .

Rem oved R164 (FLUSH#) and R168 (THERMTRIP#) pull-ups . Rem oved pull-up on PWRGOOD (pulled up on sheet 32). Grouped rem aining pull-ups to 1 1K Rpack.

Is olated CK-Whitney from SMBUS in Power Down through Voltage trans lation Quick Switch.

Changed all PCI 3.3V pull-ups to 8.2K per PCI s pec.

Changed VGA Connector sym bol. Com bined like pullups into R-packs where poss ible. Added EMI Caps on SYNC and DDC Signals . Added 8.2K pull-ups to SERIRQ and ICH0 unused GPIOs .

26 Routed USB up the AMR Connector. Added Pull-Up Sites for FLUSH# and 370PGA Socket Pin W35 to VCMOS for future com patibility upgrade.

Ran 5V (ins tead of 5VSB) to Audio Modem Ris er. 34 Updated Process or Decoupling per lates t Guidelines for 370PGA s ocket. Added s tuffing option AC’97 debug port 35 Added Sys tem Decoupling

3811-23-1998_13:43

REVISION HISTORY, PART 3

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF 40

1.3

PROJECT:INTEL(R) 810

CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

Revision History (Changes from Rev0.9 to Rev0.95)Sh e e t De s cr ip t io n Sh e e t De s cr ip t io n

2 Changed "V ideo Enc oder " box on Bloc k Diagram to "Dig ita l V ideo Out Dev ic e" Box . 20 Changed R117,R118,R121,R122 f rom 27ohm to 15ohm-1% Res is tors

A dded Dev ic e Table 22 Change R207 f rom 47K to 10K

3 Changed Ref erenc e Des ignator on 370-pin Soc ket f rom J20 to X1 23 Mov ed RP31 f rom pg. 16 to pull-up Key /Mous e lines to f iltered V CC5.

4 Changed Ref erenc e Des ignator on 370-pin Soc ket f rom J20 to X1 A dded 470pF Caps on MIDI lines (C327,C328) .

Changed C1 f rom 22uF,30% to 47uF,10% 25 Mov ed R67,R68,R69 f rom Sheet 9.

6 Changed Ser ies Termination Res is to r V alues f rom 22 Ohms to: R37,R38,R55,R56,R57=43ohm,2% ; R39,R40,R41,R42,R43,R46,R47,R58,R59,R60,R61=33ohm,2% ; R45,R48,R49,R50,R51,R52,R53,R54,R63=33ohm,5% ; R44,R226=10ohm,5%

Cleaned Up V GA Connec tor Sc hematic

T’ed REFCLK and added R226 ( to s eparate termination to ICH and SIO) . Renamed CLK14 to SIO_CLK14 and ICH_CLK14 f or eac h new NET out of the T.

A dded Prov is ions to add PI Filters on V SY NC and HSY NC Lines

Changed C144 and C185 f rom 4 .7uF to 22uF. Changed 5V Supply to Quic k Sw itc h to pull-dow n on DIODE output. A ls o pulled DDC lines up to the s ame s upply pow er ing the Quic k Sw itc h.

8 A dded Cap Site to GMCH Hub Clk Change R132,R133 f rom 8.2K to 1K Pull-Ups

A dded 0K Res is tor (R231) in s er ies w ith DCLK_W R 26 Remov ed A C97 Debug Connec tor (J5)

9 Changed Ref erenc e Des ignator on Os c illa tor Soc ket f rom U34 to X2 27 Changed R4 pull-up f rom 62K to 4.7K and added 0.1uF Dec oupling to V IO pin (C262) .

Correc ted Connec tion of Debug Os c illa tor f rom DDCSDA to DOTCLK NET. A dded Dec oupling f or LA N Pow er (C336-C341)

Updated Pin Numbers to matc h GMCH 0.7 EDS Ballou t 28 Change R140/R141 to 4.7K Res is tors

A dded 0K Res is tor (R232) in s er ies w ith LRCLK 29 Modif ied CK_PW RDW N# Generation Circ uitry to pull o f f U33 NA ND gate and inv er t th rough U13 to get c or rec t log ic lev e l. Prev ious ly it w as tapped of f the bas e of BJT Q6. Th is w ou ld hav e kept CK_PW RDW N# f rom c harging h igher than 0.7V (drop ac ros s BE junc tio

A dded Cap Site to ICH Hub Clk Changed R191 to 10K, R192 to 0K, and R193 to 4.7K

Replac e Bead FB21 w ith Induc tor (L4) - 68nH to c reate LC f ilter (<130kHz ) 30 Changed Ref e renc e Des ignato r on U15 and U25 to Q9 and Q10 res pec tiv e ly .

A dded LC f ilter to 1.8V p lane c onnec ted to ba lls U6 and E19. Changed Ref e renc e Des ignato r on U8 to V R5, U11 to V R3, and U27 to V R4

Changed Tes t Os c illa tor Circ uit (U34) to remov e s horted jumper and add dec oup ling. Changed p in names on 48MHz os c illa tor s y mbo l.

Changed C268 and C259 to 1.0uF,X7R c aps

Mov ed R67,R68,R69 to Sheet 25. A dded 2 more Si4410DY FETs in para lle l w ith tw o there (Q7/Q8)

14 Rename NET CLK14 to ICH_CLK14 Changed C160-C163 to 2700uF and added one more (C342) in para lle l.

Rename Pin L1 to V CCSUS1 and Pin N1 to V CCSUS2 Change C153 to 220pF

Rename NET GPIO23 to GPIO23_FPLED, and NET GPIO26 to GPIO26_FPLED Changed c onnec tions of COMP and SS to s how them return ing d irec tly to SGND pin.

Routed LPC_SMI# and LPC_PME# to GPIO[5:6] res pec tiv e ly f rom GPIO[12:13] res pec tiv e ly . A dded Induc tor (L13) to f ilte r 5V input to V RM

Changed V alue of C11 f rom 0.1uF to 1.0uF 31 Change ref erenc e des ignator S1 to SW 1

15 Changed Ref erenc e Des ignator on U9 to X3 Change C79 to 1.0uF

15 A dded 0K RPA CK(RP68) in s er ies to GROUND on FW H ID lines f or Tes t/Debug. A dd Front Panel Dual LED Circ uit c ontro lled by ICH GPIOs

16 Changed Pin 87 Name f rom RTS1#_SY SOP to RTS1# and Pin 50 name f rom GP27/IO_SMI#/TEST to SP27/IO_SMI#

32 Change A TX c onnec tor Ref erenc e Des ignator f rom U6 to J29.

16 Rename NET CLK14 to SIO_CLK14 Change ref erenc e des ignator S2 to SW 2

33 Remov ed Pull-Ups f rom GPIO23/GPIO26

16 Mov ed RP31 to pg. 23 to pull-up Key /Mous e lines to f iltered V CC5. Pulled LDRQ#1 Up to 3.3V Sby ( ins tead of 3.3V ).

17 Sw apped A CK64# and REQ64# to route to c o rrec t p ins per PCI s pec . Changed PCI Pull-Up Res is tor (R99,R100 ,RP53,RP46,RP47) v alues f rom 8.2K to 2.7K and c onnec ted to 5V . A ls o c onnec ted RP40 and RP43 to 5V ( f rom 3.3V ) to ma inta in c ompatib ility w ith more 5V PCI c ards .

18 Sw apped A CK64# and REQ64# to route to c o rrec t p ins per PCI s pec . Remov ed RP49 (V ID Pull-Ups ) Sinc e in ternal to LTC1753

Replac ed JP6 Jumper w ith 0K Res is tor Stuf f ing Option (R233 , R234) 35 A dded additional Dec oupling f or V ar ious Components (C343-C389)

19 Ins er ted 0K Stuf f ing Res is tors in Ser ies w ith A TA 66 Cab le Detec t (R235,R236) Changed C217-C220 f rom 0.1uF to 0.01uF

19 Sw apped 74LS07 out f or 74LV C07A and c onnec ted to 3.3V . A LL Changed Ref e renc e Des ignato rs on A ll Fer r ite Beads f rom FB* to L*.

3911-23-1998_13:43

REVISION HISTORY, PART 4

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF 40

1.3

PROJECT:INTEL(R) 810

CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

Revision History (Changes from Rev0.95 to Rev0.99)S he e t De scription S he e t De scription

4 Changed C1 to 33uF and L2 to 4.7uH. 24 Change C330 to a 100pF c ap and S caled B ac k Decoupling on power planes to U28..

Connec ted E 21 to V CC_DE T P ull-Up S wapped Connec tivity of FTCLK 0 and FTCLK 1.A dded 0603 Cap S ite on CP UHCLK 25 Fixed Connec tivity of CR2, CR4, CR5, CR6 and CR7. In all cases P ins 1 and

2 were swapped.Rem oved RP 50 and routed TCK and TM S to 330ohm pull-ups in RP 44. Change L8,L9,L10 P art Num ber to B LM 11B 750S

5 Changed Rpack connec tions per Layout Back A nnotation Changed F3 from 2.0A Fuse to 2.5A Fus e.6 Changed R39-R43,R46,R47,R58-R61 to 33ohm ,5% (from 2% ) 27 Rem oved P ull-up from LA NTCK (U29.D14) and m ade No Connec t. R136

m oved to S heet 16 to P ull-up LP CP D (U16.27).Routed CK _P W RDN# to Clock Chip (S LP _S 3# thru 8.2K res is tor by default). Rem oved C338,C339,C340,C341 and Changed C336,C337 to 4.7uF P olarized

Capac itors . 7 A dded 0603 Cap S ite on GM CHHCLK Changed INTA # (U29.H2) from P IRQ#D to P IRQ#A and Changed LA N IDS E L

(R142.1) from A D19 to A D20.8 Changed HUB RE F V oltage Divider Res is tor V alues (R182 and R185) from 1K -

1% to 301ohm -1% and added A C Dec ouping Disc rete S ites (C394,C395,R245,R246)

28 M ade C74 a 470pF-1500V cap and added "For E S T Tes ting" Note.

9 A dded 22ohm series term (R242) to LTCLK Net (U22.K 22). Changed J28.14 connec tion from A CTLE D to S P E E DLE D and Changed R219.1 c onnec tion from V CC3S B Y to A CTLED

M oved C323, C324 to page 34 and m ade C324 0.01uF. A dded P rovis ion for Isolating 82559 either on S US _S TA T# or P W ROKRem oved L5 and C325. Change C5 to 33uF. Connec t U22.U6 and U22.E 19 direc t to V CC1_8 P lane. Change U22.A B 21 and U22.A B 23 to connec t to V CC1_8.

29 Changed Referenc e Des ignator U14 to Q10 and U16 to Q11.

Rem oved S eries Term s on Digital V ideo Out P ort Renam ed NE T CK _P W RD to IN_U5, and Deleted connec tion to U13 pin 9A dded 0K (R31) in series with Debug Os c illator Rem oved CK _P W RDW N# NE T, R240

Routed DC_M D27 (c ore detec t S trap) to 10K to 220 pull-up on V CCDE T net. 30 Connec ted Q4.{5-8}/Q7.{5-8}, C193, R150 to Net 5V IN ins tead of direc t to V CC5.

14 Changed C148 from 2.2uF M onolithic to 2.2uF P olariz ed A dded 0K Rpack (RP 69) in S eries to V ID[3:0] pins of V R3. Changed Referenc e Des ignator on B A T1 to X4 (it is a soc ket footprint). 31 Changed S witch S y m bol to 4-pin devic e to m atch phy s ical device.

16 P ulled Up S US S TA T to 3.3V through 4.7K (R136, which was rem oved from LA N page) res is tor and dis connec ted from ICH0.

32 Changed RefDes U6 to J29.

19 Changes to P 66DE TE CT and S 66DETE CT NE Ts to support both Drive and Hos t S ided 80 c onduc tor c able detec tion: A dded C392 and C393 (0.047uF, X7R, 16V , 10% ) to GND, 0ohm Res is tors in S eries (R235,R236), and 15K P ull-downs (R243,R244) to GND.

Changed S witch S y m bol to 4-pin devic e to m atch phy s ical device.

20 F ixed Connec t ivity of Res is tor R124. US B V 5 Net now Connec ts direc tly to L26 term inal 1, and R124 disconnec ted from L26 term inal 1. E lim inated unwanted res is tor divider on 5V power pins at US B port.

A dded provis ion for sending early powerok to Cloc k P D# pin for c lean P ower-up

A dded S eries Res is tors (0K ) to decouple ICH US B s ignals from s tack ed c onnec tor if routed up A M R connec tor.

33 S wapped S IP Rpack s on CP U and ICH pull-ups to 4-E lem ent Rpac ks per Lay out B ac k A nnotation

22 Changed Net Nam e G_ICHRI# to ICHRI#_C Change RP 48 from 1K Rpac k to 330ohm Rpac k , and R202, and R203 from 1K res is tors to 330ohm res is tors for future upgrade c om patibility .

35 A dded A ddit ional Decoupling on V CC12- and V CC12

405-26-1999_17:09

REVISION HISTORY, PART 5

38

B

C

D

8 7 6 5 4 3 2 1

D

C

B

A

345678

A

2 1FOLSOM, CALIFORNIA 95630

DRAWN BY:

1900 PRAIRIE CITY ROAD SHEET:LAST REVISED:

PLATFORM COMPONENTS DIVISION

INTEL CORPORATIONPCD PLATFORM DESIGN

REV:

OF

1.3

PROJECT:INTEL(R) 810

CHIPSET

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R

- Changed Series Term Values on CPU and APIC Clocks to 33ohm (Sheet 6)- Changed Series Term Values on Memory, Hub, and DOT Clocks to 22ohm (Sheet 6)- Added 10K Pull-Ups on SLP_S3# and SLP_S5# (Sheet 14)- Added 2 1200uF Caps on VCC3_3SBY Plane (Sheet 29)

- Back Annotated from Layout (Reference Designator Changes/Rpack Routing Swaps)

- Connected C377 to VCC3_3SBY Plane- Corrected Pinout of 2x5 Com Port Headers (Sheet 22)- Added 2x1 Header (JP23) to sheet 32 for Chasses Reset Button

- Removed X1, R77, R78, R79 (Debug Oscillator Socket) from Sheet 9

- Added RP70 and RP71 to Sheet 8 (SM_MA Series Terms)

- Added 110Ohm, 1% Pull-Downs to pins S35 and E27 of 370-pin Socket (RTTCTRL and SLEWCTRL)- Removed 330Ohm Pull-Ups from FLUSH# and TestHi (W35 on 370-Pin Socket)

- Changed C347 from a 2200pF Cap to a 0.047uF Cap

Changes from Rev0.99 to Rev1.0

Changes from Rev1.0 to Rev1.1

Changes from Rev1.1 to Rev1.2

Revision History:Changes from Rev0.99 and On

Changes from Rev1.2 to Rev1.3

- Changed VCCDET Net name to VCOREDET- Changed Value of R125 to 174ohm, 1% (from 178ohm, 1%)- Changed value of C347 back to 2200pF Cap (from 0.047uF Cap)- Designated R126 as No Stuff per SiI 154 Specification- Removed R123 pull-up and connected SiI154 pin 13 to reset.- Changed RP50, RP49, and R169 from 330ohm to 150ohm