experiment number: 0 experiment name:...

Department of Electronics & Communication Engineering, SMIT Page |1

EXPERIMENT NUMBER: 0

EXPERIMENT NAME: Introduction to the basic components of Digital

Electronics Laboratory.

AIM: To know the Digital IC trainer Kit, its internal and external components

and to study the logic gate ICs, their PIN configurations and verify their truth

tables.

INTRODUCTION TO THE BASIC COMPONENTS:

DIGITAL IC TRAINER KIT:

This trainer kit provides facilities for hands on experience to various

experiments in Digital Electronics.

The major components and parts in a digital IC trainer kit are:

(i) Breadboard – circuits are constructed on this board

(ii) Input LEDs – indicates the level of inputs (LOW or HIGH)

(iii) Output LEDs - indicates the level of outputs (LOW or HIGH)

(iv) Input switches – used to apply logic inputs to the circuit

(v) Power supplies – supplies power to the circuit components

(vi) Clock pulse inputs (Continuous and Manual) – supplies clock input


Figure 1: A Digital IC Trainer Kit

BREADBOARD:

A breadboard is a rectangular plastic board with a bunch of tiny holes in it.

These holes help to fix and hold any circuit component like resistor, diode,

transistor, IC or connecting wires required to build on the bread board.

Below the hole (inside the breadboard) there are rows of tiny metal clips. When

the lead of any component in inserted into a hole of a breadboard, one of these

clips grabs onto it. Figure 2 below is an image of such clip.

Figure 2: Look of a Breadboard Clip


Most breadboards are marked with some numbers, letters and plus & minus

signs on them. These marks or labels are there to help the users to locate the

position of a hole on the breadboard. Every hole on the breadboard can thus be

identified with its column letter and row number; e.g. A15, H24 etc. (Figure 3).

Figure 3: Physical structure of a Breadboard

Fixing of an IC on a breadboard:

When an IC is placed on a breadboard, following two points must be ensured:

(i) The IC must be fixed firmly on the breadboard. A loose IC on a

breadboard will never produce reliable result.

(ii) All the pins of the IC must be isolated from each other. Therefore an IC

needs to be placed on the divider (the gap between the two banks) of a

breadboard (Figure 4).


Figure 4: Position of an IC on a breadboard

JUMPER WIRES:

Jumper wires are used to make connections on a breadboard. Jumper wires

are covered with insulating materials like plastic. These wires usually come in

packs of varying colours. This helps in colour coding the circuits. The cover of

the wire is removed from the two ends with a cutter. Jumper wires are stiff

enough to push them into the breadboard holes. There are several different

varieties available for jumper wires.

Input and Output LEDs

As digital logic circuits work on binary system, their inputs and outputs accept

and produce only two levels of voltages. Thus, in most of the basic experiments,

outputs and inputs of digital circuits are observed in LEDs. A “RED” light in

the LEDs indicates a HIGH level and LOW level is indicated by a “GREEN” or

“NO LIGHT”.


Important Points to remember when connecting a circuit on the

breadboard:

1. At the beginning, before start of the circuit connection, connect the

power supply cable of the digital trainer kit and examine its working.

2. Check the functioning of every circuit component individually before

connecting them in the circuit. It is difficult to find or locate the faulty

component when they are in a circuit.

3. Keep the power supply of the digital trainer kit OFF while making the

circuit connections. Connecting a circuit with power supply turned ON

may damage the circuit component and/or the trainer kit.

4. IC must be placed on the divider on the breadboard (refer to Figure 4).

5. IC must be firmly fixed on the breadboard. A loose IC always results

unreliable output.

6. The uncovered lead of the connecting wires at the two ends should not

be too long or too short. Long uncovered wires may get connected with

other such wires. On the other hand, a too short end may not touch the

metal clip inside the breadboard.

7. Every connection point on the breadboard must be properly and firmly

fixed.

8. Avoid connecting many inputs from a single point. This will reduce

current in the inputs and hence may lead to erratic operation of the

circuit.

9. After connecting the complete circuit, turn the digital trainer kit ON

and verify the circuit operation.

10. Never keep a circuit turned ON and unattended.


VERIFICATION OF LOGIC GATES

APPARATUS REQUIRED:

SL NO. COMPONENT SPECIFICATION QUANTITY

1. NAND gate IC 7400 1

2. NOR gate IC 7402 1

3. NOT gate IC 7404 1

4. AND gate IC 7408 1

5. OR gate IC 7432 1

6. XOR gate IC 7486 1

8. IC trainer kit - 1

9. Wires - As required

Logic Gates:

Logic gates are the basic components in digital circuits. All the logic gates

follow their own logic and accordingly produce the output. Each gate has one

or more input and only one output. Characteristic of a gate is depicted in a

truth table. A truth table shows all the possible input combination for a logic

gate or circuit and the corresponding output. There are 7 (seven) different logic

gates. They are (i) NAND (ii) NOR (iii) NOT (iv) AND (v) OR (vi) XOR and (vii)

XNOR gate. NOT, AND & OR gates are basic gates. NAND, NOR, XOR and

XNOR gates are combination of the basic gates and hence are called composite

gates.


NAND GATE (IC 7400):

The NAND gate is a combination of AND and NOT gate. The output of a NAND

is LOW only when all of its inputs are HIGH.


NOR GATE (IC 7402):

The NOR gate is an inverted output OR gate. In a NOR gate, the output is high

only when all of its inputs are low.


NOT GATE (IC 7404):

The NOT gate is called an inverter. Its output is HIGH when applied input is

LOW and the output is LOW when the input is HIGH.


AND GATE (IC 7408):

The AND gate performs a logical multiplication. In an AND gate, the output is

HIGH only when all of its inputs are HIGH.


OR GATE (IC 7432):

The OR gate performs a logical addition. The output of an OR gate is HIGH

when at least one of the inputs is HIGH. That is its output is LOW only when

all of its inputs are LOW.


XOR GATE (IC 7486):

XOR gate is a composite gate. Its output is HIGH only when odd number of

inputs is HIGH. Output of an XOR gate is given by Y = A B + A B = A B⊕

Practical Procedure:

1. ICs are placed properly on the bread board of the IC trainer kit.

2. Connections are made as per the PIN diagram of the IC.

3. Power supply to the board is turned ON.

4. One gate in every IC is verified as per the truth table of the logic gate.

Observation:

Essential parts of an IC trainer kit are studied and logic gates are verified.



EXPERIMENT NAME: Design of a (i) Half adder and (ii) Full adder

AIM: To design a Half Adder and Full Adder circuit using logic gates and to

verify them using truth tables.

APPARATUS REQUIRED:

SL. NO. COMPONENT SPECIFICATION QUANTITY

1. AND gate IC 7408 1

2. X-OR gate IC 7486 1

3. NOT gate IC 7404 1

4. OR gate IC 7432 1

5. IC trainer kit - 1

6. Connecting Wires - As required

THEORY:

HALF ADDER:

A half adder is a combinational circuit that can add two bits and produces the

sum of the input bits as the result or output. A half adder has two inputs for

the two bits to be added and two outputs - one is the sum ‘S’ and other one is

the carry ‘C’. A half adder cannot consider a previous carry (third input bit).

Due to this limitation, a half adder circuit can’t be used in cascade adder. Two

half adders can be combined together to form a full adder.

FULL ADDER:

A full adder is adds three input bits and produces the arithmetic sum of the

input bits as its output. Thus a full adder has two output lines – the sum ‘S’

and the carry ‘C’. Because a full adder can add three bits, it is useful in


designing a cascade adder or a parallel adder, where two numbers with more

than one bit can be added.

TRUTH TABLE OF A HALF ADDER:

Input Output

X Y C (Carry) S (Sum)

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

K-Map for S (Sum) K-Map for C (Carry)

S = X Y + X Y C=AB

S=X Y⊕

CIRCUIT DIAGRAM OF A HALF ADDER:


TRUTH TABLE OF FULL ADDER:

Inputs Outputs

X Y Z C (Carry) S (Sum)

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

K-Map for S (Sum):

S = X Y Z + X Y Z + X Y Z + X Y Z

( ) ( )X Y Z + Y Z + X Y Z + Y Z=

( ) ( ) X Y Z + X Y Z= ⊕ ⊕

∴ S X Y Z= ⊕ ⊕

K-Map for C (Carry):

C = XY + YZ + ZX


CIRCUIT DIAGRAM OF A FULL ADDER:

DESIGN PROCEDURE:

1. Truth tables of the (i) Half adder and (ii) Full adder are prepared.

2. K-map for each output variable present in the truth tables is drawn.

3. Simplified expression for each output variable is obtained.

4. Circuit diagram is drawn as per the simplified expressions of the output

variables obtained in step 3.

PRACTICAL PROCEDURE:


2. Connections are made as per the designed circuit diagram.


4. Circuit is verified as per the truth table of the circuit.

RESULT and CONCLUSION:

Thus the half adder and full adder were designed and their truth tables have

been verified.



EXPERIMENT NAME: Design of a (i) Half subtractor and (ii) Full subtractor

AIM: To design a Half subtractor and Full subtractor circuit using logic gates

and to verify them.

APPARATUS REQUIRED:

Sl. No. COMPONENT SPECIFICATION QUANTITY

1. AND GATE IC 7408 1

2. XOR GATE IC 7486 1

3. NOT GATE IC 7404 1

4. OR GATE IC 7432 1

5. IC TRAINER KIT - 1

6. CONNECTING WIRES - AS REQUIRED

THEORY:

HALF SUBTRACTOR:

The half subtractor is a combinational circuit that takes two input bits and

subtracts one bit from the other. Half subtractor produces the result of the

subtraction of the two bits through the two outputs – the Borrow ‘B’ and the

Difference ‘D’.

FULL SUBTRACTOR:

The full subtractor is combinational circuit with three inputs and two outputs.

The operation performed by a full subtractor is arithmetic subtraction. If X, Y

and Z are the inputs of a full subtractor circuit, then, the output of the circuit

is (X - Y) - Z . A full subtractor can be designed using two half subtractors.


TRUTH TABLE OF A HALF SUBTRACTOR:

Input Output

X Y B (Borrow) D (Difference)

0 0 0 0

0 1 1 1

1 0 0 1

1 1 0 0

K-Map for D (Difference): K-Map for B (Borrow):

D = X Y + X Y B = X Y

D = X Y⊕

CIRCUIT DIAGRAM OF A HALF SUBTRACTOR:


TRUTH TABLE OF A FULL SUBTRACTOR:

Inputs Outputs

X Y Z B (Borrow) D (Difference)

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 1 0

1 0 0 0 1

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

K-Map for Difference:

D = X Y Z + X Y Z + X Y Z + X Y Z

( ) ( )X Y Z + Y Z + X Y Z + Y Z=

( ) ( ) X Y Z + X Y Z= ⊕ ⊕

∴ D X Y Z= ⊕ ⊕

K-Map for Borrow:

B = X Y + Y Z + Z X


CIRCUIT DIAGRAM OF A FULL SUBTRACTOR:

DESIGN PROCEDURE:

1. Truth tables of the (i) Half subtractor and (ii) Full subtractor are prepared.











Thus the half subtractor and full subtractor were designed and their truth

tables have been verified.



EXPERIMENT NAME: Design of a 1-bit Comparator

AIM: To design a 1-bit Comparator using logic gates and to verify it.

APPARATUS REQUIRED:



2. X-OR GATE IC 7486 1




THEORY:

1-Bit Comparator is a combinational logical circuit that compares two single

bits A and B. Result of the comparison is produced at the output. As there can

be three different possibilities of result – (i) A>B (ii) A<B or (iii) A=B, there are

three outputs of a comparator. Depending upon the applied input bits, any one

of the three conditions is satisfied and thus the corresponding output goes

HIGH, other two outputs remain LOW.

TRUTH TABLE:

INPUTS OUTPUTS

A B X (A<B) Y (A=B) Z (A>B)

0 0 0 1 0

0 1 1 0 0

1 0 0 0 1

1 1 0 1 0


X=A B Y = A B + A B Z=A B

=A B⊕

CIRCUIT DIAGRAM OF A 1 BIT COMPARATOR:

DESIGN PROCEDURE:

1. Truth table of the One bit comparator is prepared.












Thus the one bit comparator was designed and its truth table has been verified.



EXPERIMENT NAME: Design of a 3-BIT Even Parity Generator.

AIM: To design a 3-bit Even Parity Generator using logic gates.

APPARATUS REQUIRED:





THEORY:

A parity bit is used for the purpose of detecting errors during transmission of

binary information. A parity bit is an extra bit included with a binary message

to make the number of 1’s either odd or even. The message including the parity

bit is transmitted and then checked at the receiving end for errors.

An error is detected if the checked parity does not correspond with the one

transmitted. The circuit that generates the parity bit in the transmitter is called

a parity generator and the circuit that checks the parity in the receiver is called

a parity checker. In even parity, the included parity bit will make the total

number of 1’s an even amount and in odd parity the added parity bit will make

the total number of 1’s an odd amount. In a three bit odd parity generator the

three bits in the message together with the parity bit are transmitted to their

destination, where they are applied to the parity checker circuit. The parity

checker circuit checks for possible errors in the transmission. Since the

information was transmitted with odd parity the four bits received must have

an odd number of 1’s. An error occurs during the transmission if the four bits

received have an even number of 1’s, indicating that one bit has changed


during transmission. The output of the parity checker is denoted by PEC

(parity error check) and it will be equal to 1 if an error occurs, i.e., if the four

bits received has an even number of 1’s.

TRUTH TABLE for 3 BIT EVEN PARITY GENERATOR:

Input Output

X Y Z P

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 0

1 0 0 1

1 0 1 0

1 1 0 0

1 1 1 1

K-Map for P:

P = X Y Z + X Y Z + X Y Z + X Y Z

( ) ( )X Y Z + Y Z + X Y Z + Y Z=

( ) ( ) X Y Z + X Y Z= ⊕ ⊕

∴ P X Y Z= ⊕ ⊕


CIRCUIT DIAGRAM OF A 3 BIT EVEN PARITY GENERATOR:

DESIGN PROCEDURE:

1. Truth table of the 3 bit even parity generator is prepared.

2. K-map for the output variable (P) is drawn.

3. Simplified expression for the output variable is obtained using manual

simplification.

4. Circuit diagram is drawn as per the simplified expression of the output

variable obtained in step 3.







The 3 bit even parity generator was designed and its truth table has been

verified.



EXPERIMENT NAME: Design of a 3-BIT Odd Parity Checker.

AIM: To design a 3-bit Odd Parity Checker using logic gates and to verify it.

APPARATUS REQUIRED:






THEORY:

A parity bit is used for the purpose of detecting errors during transmission of

binary information. A parity bit is an extra bit included with a binary message

to make the number of 1’s either odd or even. The message including the parity

bit is transmitted and then checked at the receiving end for errors.

An error is detected if the checked parity does not correspond with the one

transmitted. The circuit that generates the parity bit in the transmitter is called

a parity generator and the circuit that checks the parity in the receiver is called

a parity checker. In even parity the added parity bit will make the total number

of 1’s an even amount and in odd parity the included parity bit will make the

total number of 1’s an odd amount. In a three bit odd parity generator the

three bits in the message together with the parity bit are transmitted to their

destination, where they are applied to the parity checker circuit. The parity

checker circuit checks for possible errors in the transmission. Since the

information was transmitted with odd parity the four bits received must have

an odd number of 1’s. An error occurs during the transmission if the four bits

received have an even number of 1’s, indicating that one bit has changed


during transmission. The output of the parity checker is denoted by PEC

(parity error check) and it will be equal to 1 if an error occurs, i.e., if the four

bits received has an even number of 1’s.

TRUTH TABLE OF A 3 BIT ODD PARITY CHECKER:

Input Output

A B C P Y

0 0 0 0 1

0 0 0 1 0

0 0 1 0 0

0 0 1 1 1

0 1 0 0 0

0 1 0 1 1

0 1 1 0 1

0 1 1 1 0

1 0 0 0 0

1 0 0 1 1

1 0 1 0 1

1 0 1 1 0

1 1 0 0 1

1 1 0 1 0

1 1 1 0 0

1 1 1 1 1


From the K-map we have,

( ) ( ) ( ) ( )Y= A B C P + C P + A B C P + C P + A B C P + C P + A B C P + C P

( ) ( ) ( ) ( )Y= A B C P + A B C P + A B C P + A B C P⊕ ⊕ ⊕ ⊕

( ) ( ) ( ) ( )Y= A B C P + A B C P + A B C P + A B C P⊕ ⊕ ⊕ ⊕

( )( ) ( )( )Y= C P A B + A B + C P A B + A B⊕ ⊕

( )( ) ( )( )Y= C P A B + C P A B (i)⊕ ⊕ ⊕ ⊕ ……

Say, A B=W⊕ and C P=X⊕

(i) Y=X W + X W∴ ⇒

Y = W X⇒ ⊕

Y = A B C P⇒ ⊕ ⊕ ⊕


CIRCUIT DIAGRAM OF A 3-BIT ODD PARITY CHECKER:

DESIGN PROCEDURE:

1. Truth table of the 3 bit odd parity checker is prepared.

2. K-map for the output variable (Y) is drawn.

3. Simplified expression for the output variable is obtained using manual

simplification.

4. Circuit diagram is drawn as per the simplified expression of the output

variable obtained in step 3.







The 3 bit odd parity checker was designed and its truth table has been verified.



EXPERIMENT NAME: Design of a 4-Bit Binary to Gray Code Converter.

AIM: To design a 4-Bit Binary to Gray Code converter using logic gates and to

verify its truth table.

APPARATUS REQUIRED:





THEORY:

The availability of large variety of codes for the same discrete elements of

information results in the use of different codes by different systems. A

conversion circuit must be inserted between the two systems if each uses

different codes for same information. Thus, code converter is a circuit that

makes the two systems compatible even though each uses different binary

code.

Gray code is a non-weighted code. Total number of bits in binary and its

corresponding gray code is equal. In the circuit to be designed, each code uses

four bits to represent a decimal digit. Thus, there are four inputs and four

outputs.

The input variable are designated as W, X, Y& Z and the output variables are

designated as A, B, C & D. from the truth table, combinational circuit is

designed. The Boolean functions are obtained from K-Map for each output

variable.


TRUTH TABLE:

BINARY INPUT GRAY OUTPUT

W X Y Z A B C D

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

1 0 0 0 1 1 0 0

1 0 0 1 1 1 0 1

1 0 1 0 1 1 1 1

1 0 1 1 1 1 1 0

1 1 0 0 1 0 1 0

1 1 0 1 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0


K-Map for A: K-Map for B:

A=W B = W X + W X

B = W X⊕

K-Map for C: K-Map for D:

C = X Y + X Y D = Y Z + Y Z

C = X Y⊕ D = Y Z⊕


CIRCUIT DIAGRAM OF A 4 BIT BINARY TO GRAY CODE CONVERTER:

DESIGN PROCEDURE:

1. Truth table of the 4 bit binary to gray code converter is prepared.

2. K-maps for all the output variables (A, B, C and D) are drawn.

3. Simplified expressions for the output variables are obtained using manual

simplification.









The 4 bit binary to gray code converter was designed and its truth table has

been verified.



EXPERIMENT NAME: Design of a 4-Bit Gray to Binary Code Converter.

AIM: To design a 4-Bit Gray to Binary Code converter using logic gates and

verify its truth table.

APPARATUS REQUIRED:





THEORY:

The availability of large variety of codes for the same discrete elements of

information results in the use of different codes by different systems. A

conversion circuit must be inserted between the two systems if each uses

different codes for same information. Thus, code converter is a circuit that

makes the two systems compatible even though each uses different binary

code.


corresponding gray code is equal. In the circuit to be designed, each code uses

four bits to represent a decimal digit. Thus, there are four inputs and four

outputs.

The input variable are designated as A, B, C & D and the output variables are

designated as W, X, Y & Z. from the truth table, combinational circuit is


variable.


TRUTH TABLE:

GRAY INPUT BIANRY OUTPUT

A B C D W X Y Z

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 1

0 1 0 1 0 1 1 0

0 1 1 0 0 1 0 0

0 1 1 1 0 1 0 1

1 0 0 0 1 1 1 1

1 0 0 1 1 1 1 0

1 0 1 0 1 1 0 0

1 0 1 1 1 1 0 1

1 1 0 0 1 0 0 0

1 1 0 1 1 0 0 1

1 1 1 0 1 0 1 1

1 1 1 1 1 0 1 0


K-Map for W: K-Map for X:

W=A X = A B + A B

X = A B⊕

K-Map for Y:

Y = A B C + A B C + A B C + A B C

( ) ( )Y = A B C + B C + A B C + B C

( ) ( )Y = A B C + A B C⊕ ⊕

Y = A B C⊕ ⊕


K-Map for Z:

Z = A B C D + A B C D + A B C D + A B C D + A B C D + A B C D + A B C D + A B C D

Z = A B C D + A B C D + A B C D + A B C D + A B C D + A B C D + A B C D + A B C D

( ) ( ) ( ) ( )Z = A B C D + C D + A B C D + C D + A B C D + C D + A B C D + C D

( ) ( ) ( ) ( )Z = A B C D + A B C D + A B C D + A B C D⊕ ⊕ ⊕ ⊕

( ) ( ) ( ) ( )Z = A B + A B C D + A B + A B C D⊕ ⊕

( )( ) ( ) ( )Z = A B C D + A B C D⊕ ⊕ ⊕ ⊕

Z = A B C D⊕ ⊕ ⊕

CIRCUIT DIAGRAM OF A 4 BIT GRAY TO BINARY CODE CONVERTER:


DESIGN PROCEDURE:

1. Truth table of the 4 bit gray to binary code converter is prepared.

2. K-maps for all the output variables (W, X, Y and Z) are drawn.


simplification.









The 4 bit gray to binary code converter was designed and its truth table has

been verified.



EXPERIMENT NAME: Design of a BCD to Gray Code Converter.

AIM: To design a BCD to Gray Code converter using logic gates and to verify its

truth table.

APPARATUS REQUIRED:






THEORY:

BCD (Binary Coded Decimal) code is a weighted code. BCD code is found from

a decimal number. Each digit of the decimal number is encoded with four (4)

equivalent bits to find its BCD code. Therefore BCD code from decimal 0 to 9

has 4 bits; but from decimal 10 to 15, 8 bits are required to represent the BCD

code (whereas straight binary needs only 4 bits for these numbers).


corresponding gray code is equal. In the circuit to be designed, each input code

(BCD code) uses four bits to represent a decimal digit. Thus, there are four

inputs and four outputs.

The input variable are designated as W, X, Y& Z and the output variables are

designated as A, B, C & D. from the truth table, combinational circuit is


variable.


TRUTH TABLE:

BCD GRAY OUTPUT

W X Y Z A B C D

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

1 0 0 0 1 1 0 0

1 0 0 1 1 1 0 1

1 0 1 0 × × × ×

1 0 1 1 × × × ×

1 1 0 0 × × × ×

1 1 0 1 × × × ×

1 1 1 0 × × × ×

1 1 1 1 × × × ×



A=W B = W+X


C = X Y + X Y D = Y Z + Y Z

C = X Y⊕ D = Y Z⊕


CIRCUIT DIAGRAM OF A BCD TO GRAY CODE CONVERTER:

DESIGN PROCEDURE:

1. Truth table of the BCD to gray code converter is prepared.



simplification.









The BCD to gray code converter was designed and its truth table has been

verified.



EXPERIMENT NAME: Design of a BCD to Excess-3 Code Converter.

AIM: To design a BCD to Excess-3 Code Converter using logic gates.

APPARATUS REQUIRED:








THEORY:

BCD (Binary Coded Decimal) code is a weighted code. Origin of a BCD number

is a decimal number. Each digit of the decimal number is encoded with four (4)




Excess 3 (XS3) code of a number is found by adding 3 (112) with its BCD code.

Therefore there is no fixed weightage of the bit positions in an XS3 number.

Thus, XS3 code is non-weighted code.

Output side of the truth table of a BCD to XS3 code converter is found by

adding 112 with the corresponding BCD code. After 10012 (decimal 9) as 4bit

BCD is not valid, outputs are don’t cares (x).


TRUTH TABLE:

BCD INPUT EXCESS-3 OUTPUT

A B C D W X Y Z

0 0 0 0 0 0 1 1

0 0 0 1 0 1 0 0

0 0 1 0 0 1 0 1

0 0 1 1 0 1 1 0

0 1 0 0 0 1 1 1

0 1 0 1 1 0 0 0

0 1 1 0 1 0 0 1

0 1 1 1 1 0 1 0

1 0 0 0 1 0 1 1

1 0 0 1 1 1 0 0

1 0 1 0 × × × ×

1 0 1 1 × × × ×

1 1 0 0 × × × ×

1 1 0 1 × × × ×

1 1 1 0 × × × ×

1 1 1 1 × × × ×


K-Map for W: K-Map for X:

W = BD + BC + A X = B C D + B C + B D

( )W = A + B C+D ( ) ( )X = B C+D + B C+D

( )X = B C+D⊕

K-Map for Y: K-Map for Z:

Y = C D + C D Z = D

Y = C D⊕


CIRCUIT DIAGRAM OF A BCD TO XS-3 CODE CONVERTER:

DESIGN PROCEDURE:

1. Truth table of the BCD to XS-3 code converter is prepared.

2. K-maps for all the output variables (W, X, Y and Z) are drawn.


simplification.









The BCD to XS-3 code converter was designed and its truth table has been

verified.



EXPERIMENT NAME: Design of an Excess-3 to BCD Code Converter.

AIM: To design an Excess-3 to BCD Code Converter using logic gates and to

verify its outputs.

APPARATUS REQUIRED:





4. OR GATE IC7432 1



THEORY:

BCD (Binary Coded Decimal) code is a weighted code. Origin of a BCD number

is a decimal number. Each digit of the decimal number is encoded with four (4)




Excess 3 (XS3) code of a number is found by adding 3 (112) with its BCD code.

Therefore there is no fixed weightage of the bit positions in an XS3 number.

Thus, XS3 code is non-weighted code.

Output side of the truth table of an XS3 to BCD code converter is found by

subtracting 112 from the corresponding XS3 code (Input). XS3 code with 4bit


ranges from 00112 to 11002. Therefore, XS3 codes before 00112 and after 11002

are not valid. So their corresponding outputs are don’t cares (x).

TRUTH TABLE:

EXCESS-3 INPUT BCD OUTPUT

W X Y Z A B C D

0 0 0 0 × × × ×

0 0 0 1 × × × ×

0 0 1 0 × × × ×

0 0 1 1 0 0 0 0

0 1 0 0 0 0 0 1

0 1 0 1 0 0 1 0

0 1 1 0 0 0 1 1

0 1 1 1 0 1 0 0

1 0 0 0 0 1 0 1

1 0 0 1 0 1 1 0

1 0 1 0 0 1 1 1

1 0 1 1 1 0 0 0

1 1 0 0 1 0 0 1

1 1 0 1 × × × ×

1 1 1 0 × × × ×

1 1 1 1 × × × ×



A = W X + W Y Z B = X Y + X Z + X Y Z

( )A = W X + Y Z ( ) ( )B = X Y + Z + X YZ

( ) ( )B = X YZ + X YZ

( )B = X YZ⊕


C = Y Z + Y Z D = Z

C = Y Z⊕


CIRCUIT DIAGRAM OF AN XS-3 TO BCD CODE CONVERTER:

DESIGN PROCEDURE:

1. Truth table of the XS-3 to BCD code converter is prepared.



simplification.









The XS-3 to BCD code converter was designed and its truth table has been

verified.



EXPERIMENT NAME: Design of a 2 to 4 line active HIGH outputs Decoder.

AIM: To design a 2 to 4 line Decoder with active HIGH outputs using logic

gates and verify it.

APPARATUS REQUIRED:






THEORY:

A decoder is a combinational circuit that connects the binary information from

‘n’ number of input lines to a maximum of 2n unique output lines. Decoder is

also called a minterm generator/Maxterm generator. A minterm generator is a

decoder with active HIGH outputs and is constructed using AND and NOT

gates. Maxterm generator is designed with OR and NOT gates and has active

LOW outputs.

TRUTH TABLE:

INPUT OUTPUT

A B D0 D1 D2 D3

0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1


From the truth table, we get the output expressions as:

OD = A B

1D = A B

2D = A B

3D = A B

CIRCUIT DIAGRAM OF A 2 TO 4 LINE DECODER WITH ACTIVE HIGH

OUTPUTS:


DESIGN PROCEDURE:

1. Truth table of 2 to 4 line decoder with active HIGH outputs is prepared.

2. K-maps for all the output variables (D0, D1, D2 and D3) are drawn.


simplification.









The 2 to 4 line decoder with active HIGH outputs was designed and its truth

table has been verified.



EXPERIMENT NAME: Design of a 1:4 Demultiplexer using logic gates.

AIM: To design a 1:4 Demultiplexer using logic gates.

APPARATUS REQUIRED:






THEORY:

The function of Demultiplexer is in contrast to multiplexer function. It takes

information from one line and distributes it to a given number of output lines.

For this reason, the demultiplexer is also known as a data distributor. Decoder

can also be used as demultiplexer.

In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND

gates. The data select lines enable only one gate at a time and the data on the

data input line will pass through the selected gate associated to the data

output line.


TRUTH TABLE:

INPUT SELECT INPUT

OUTPUT

E A B D0 D1 D2 D3

0 0 0 E=0 0 0 0

0 0 1 0 E=0 0 0

0 1 0 0 0 E=0 0

0 1 1 0 0 0 E=0

1 0 0 E=1 0 0 0

1 0 1 0 E=1 0 0

1 1 0 0 0 E=1 0

1 1 1 0 0 0 E=0

From the truth table, output expressions are:

0D = E A B

1D = E A B

2D = E A B

3D = E A B


CIRCUIT DIAGRAM OF A 1:4 DEMULTIPLEXER:

DESIGN PROCEDURE:

1. Truth table of 1:4 demultiplexer is prepared.

2. K-maps for all the output variables (D0, D1, D2 and D3) are drawn.


simplification.










The 1:4 demultiplexer was designed and its truth table has been verified.



EXPERIMENT NAME: Design of a 4:1 Multiplexer.

AIM: To design a 4:1 Multiplexer using logic gates and to verify its operation.

APPARATUS REQUIRED:







THEORY:

A digital multiplexer is a combinational circuit that receives binary information

from many input lines and directs it to a single output line. The selection of a

particular input line is controlled by a set of selection lines. A multiplexer has

n number of select lines, 2n number of input lines and a single output line. At a

time, any one of the inputs is connected with the output line through the

multiplexer. Combination in the select input determines the input which will be

connected with the output.


FUNCTION TABLE:

SELECT INPUTS OUTPUT

A B Y

0 0 I0

0 1 I1

1 0 I2

1 1 I3

0 1 2 3Y = I A B + I A B + I A B + I A B

CIRCUIT DIAGRAM OF A 4:1 MULTIPLEXER:


DESIGN PROCEDURE:

1. Function table of 4:1 multiplexer is prepared.

2. From the function table, output expression of the multiplexer is found.

3. Circuit diagram is drawn as per the output expression obtained in step 2.







The 4:1 multiplexer was designed and its truth table has been verified.



EXPERIMENT NAME: Design of an 8:1 Multiplexer using two 4:1 Multiplexers

(use multiplexer IC).

AIM: To design an 8:1 Multiplexer using two 4:1 Multiplexer ICs (IC74153) and

to verify it.


1. DUAL 4:1 MUX IC 74153 2





THEORY:

A data selector, more commonly called a Multiplexer, shortened to "Mux" or

"MPX", is combinational logic switching devices that operate like a very fast

acting multiple position rotary switches. They connect or control, multiple

input lines called "channels" consisting of 2, 4, 8 or 16 individual inputs, one

at a time to an output. Then the job of a multiplexer is to allow multiple signals

to share a single common output. A single multiplexer as IC is 4:1, i.e., it can

handle a maximum of 4 inputs. When the number of inputs is more then 4, a

multiplexer tree can be used, also known as multiplexer stack.

Two multiplexers can be combined together to form a higher order multiplexer

with the help of their enable input.


Truth Table of 8:1 MUX using two 4:1 MUXs

Select Input Output

E A B Y0 Y1 Y

0 0 0 I0 × I0

0 0 1 I1 × I1

0 1 0 I2 × I2

0 1 1 I3 × I3

1 0 0 × I4 I4

1 0 1 × I5 I5

1 1 0 × I6 I6

1 1 1 × I7 I7

From the columns of Y0, Y1 and Y in the above truth table, we observe that

0 1Y = Y +Y

CIRCUIT SET UP OF AN 8:1 MULTIPLEXER USING TWO 4:1 MUXs:


DESIGN PROCEDURE:

1. Pin configurations of the IC with two 4:1 multiplexers (IC74153) are

examined and assertion levels of the enable terminals are noted.

2. Function table of an 8:1 multiplexer is prepared considering three select

inputs E, A and B.

3. Circuit set up is made so that the combination of the two 4:1 multiplexers

works as 8:1 multiplexer.







The 8:1 Multiplexer using TWO 4:1 Multiplexers (IC74153) was designed and

its truth table has been verified.



EXPERIMENT NAME: Design of a Full Adder using decoder IC.

AIM: To design a Full Adder using decoder IC 74138 (3 to 8 line decoder) and

to verify it.

APPARATUS REQUIRED:


1. 3:8 DECODER IC 74138 1

2. 4 I/P NAND GATE IC 7420 1



THEORY:

A full adder is a combinational circuit that forms the arithmetic sum of input;

it consists of three inputs and two outputs. As a decoder produces minterms at

its output, a decoder can be used to realize any Boolean expression which is in

Sum of Product (SOP) canonical form. The minterms present in the output

expression need to be connected with an additional OR gate. IC 74138 is a 3 to

8 line decoder IC. The canonical output expressions of Sum and Carry are

found from the truth table directly. As the outputs of the IC 74138 are active

LOW, every output must be passed through an inverter before connecting them

to the OR gate. According to the De-Morgan’s theorem, inverted input OR is

equivalent to NAND ( )A + B = AB . Thus, NAND gate is connected at the output

of the decoder.


TRUTH TABLE OF FULL ADDER:

Inputs Outputs

X Y Z C (Carry) S (Sum)

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

From the truth table we get,

( )S = m 1, 2, 4, 7∑

( )C = m 3, 5, 6, 7∑

CIRCUIT DIAGRAM OF A FULL ADDER USING DECODER IC 74138:

DESIGN PROCEDURE:

1. Truth table of a full adder is prepared.

2. From the truth table, output expressions of Sum and Carry are found in

canonical Sum of Product (SOP) form (with minterms).

3. Circuit diagram is drawn as per the output expressions.








The full adder using decoder IC 74138 was designed and its truth table has

been verified.



EXPERIMENT NAME: Design a Half Adder using a 4:1 Multiplexer IC.

AIM: To design a Half Adder using IC 74153.

APPARATUS REQUIRED:


1. 4:1 MUX IC 74153 1



THEORY:

A half adder has two inputs for the two bits to be added and two outputs one

form the sum ‘ S’ and other form the carry ‘C’. A multiplexer can be used to

implement any Boolean function which is in canonical Sum of Product (SOP)

form. A single multiplexer can implement a single function. Since a half adder

has two output functions (Sum and Carry), two multiplexers will be required to

implement the half adder.

TRUTH TABLE OF HALF ADDER:

Input Output

X Y C (Carry) S (Sum)

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

( ) ( )C x, y = m 3∑

( ) ( )S x, y = m 1, 2∑


PIN DIAGRAM OF IC 74153:

CIRCUIT SET UP OF A HALF ADDER USING A 4:1 MULTIPLEXER IC:


DESIGN PROCEDURE:

1. Truth table of a half adder is prepared.

2. From the truth table, output expressions of Sum and Carry are found in

canonical Sum of Product (SOP) form (with minterms).

3. Inputs of the half adder (x and y) are connected with the select inputs (S0

and S1) of the multiplexers.

4. According to the output expressions of C and S, inputs of the multiplexers

(I0, I1, I2, ….., I7) are connected to either a 0 (LOW) and 1 (HIGH).





4. Circuit is verified as per the truth table of the half adder.


Thus the half adder using a 4:1 Multiplexer IC was designed and its truth table

has been verified.



EXPERIMENT NAME: Design of a full adder/full subtractor with a control line

using IC 74283.

AIM: To design a full adder/full subtractor with a control line using IC 74283

and to verify it with two 4 bit numbers.

APPARATUS REQUIRED:


1. 4 BIT PARALLEL ADDER IC IC 74283 1


3. IC TRAINER KIT -


THEORY:

IC 74283 is a 4 bits cascade adder. Inside this IC, there are 4 full adders

internally cascaded together with the carry bits. The one of the two numbers

required to be added is applied at A4, A3, A2 and A1 and other number is

applied at B4, B3, B2 and B1.

With some modifications, this adder IC can also be used for subtraction. In this

experiment four XOR gates are used in the circuit set up. One input of all the

XOR gates is shorted together with the Cin input of the IC74283. When LOW

input is connected with Cin, the XOR gates work as a shorted line and thus the

other inputs of the XOR gates (i.e. B4, B3, B2 & B1) gets connected with the

adder IC directly. In this condition, the circuit works as an adder. When Cin is

connected to HIGH, one input of all the XOR gates becomes HIGH and hence

they work as inverters. Now, inverted Bs (i.e 1’s complement of B) enters into

the adder IC. But, as Cin is also HIGH, the adder adds a ‘1’ with the 1’s

complement of B. Thus effectively the IC get 2’s complement of B which is


added with A. Therefore the IC performs subtraction using 2’s complement of

the second number B.

MANUAL CALCULATIONS OF ADDITON AND SUBTRACTION:

Say,

A = 1 1 0 12 4 3 2 1A =1, A =1, A =0 & A =1⇒

B = 1 0 0 12 4 3 2 1B =1, B =0, B =0 & B =1⇒

Addition: Subtraction:

Result: out 4 3 2 1C =1, S =0, S =1, S =1 & S =0 Result: 4 3 2 1S =0, S =1, S =0 & S =0

& outC =1(as result is positive)

CIRCUIT SET UP OF A FULL ADDER/FULL SUBTRACTOR WITH A

CONTROL LINE USING IC 74283:

1 1 0 1

+ 1 0 0 1

0 1 0 0

1 1 0 1

+ 1 0 0 1

1 0 1 1 0


DESIGN PROCEDURE:

1. A circuit set up is designed using 4 (four) XOR gates.

2. One input of all the XOR gates is shorted with Cin.


1. Two numbers A & B (A>B) with 4 bits are considered to verify the operation

of the designed circuit.

2. Calculations of A+B and A-B are done manually.




6. Cin is connected to LOW and then the result of A+B is verified.

7. Cin is connected to HIGH and then the result of A-B is verified. Final carry

Cout indicates a positive result.

8. For both addition and subtraction, the results produced by the connected

circuit were verified matching them with the manual result.


The full adder/full subtractor with a control line using IC 74283 was designed

and its operations as an adder and as a subtractor have been verified.

experiment number: 0 experiment name:...

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