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POWERDISSIPATIONINFPGA

DEVICES

RICHARDFABIANRODRIGUEZ

JAIMEANDRESSALAZARUNIVERSIDADDELVALLE

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CONTENT

1. INTRODUCTION2. POWERDISSIPATION:concept,components

andequaon.

3. POWERESTIMATIONTECHNIQUEFORFPGA.3.1-Switchingacvity

3.2-Capacitance

4.FPGAvs.ASIC

5.CONCLUSIONS

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1.INTRODUCTION

Developmentofportablecompungsystem. PowerdissipaonisbecomingoneofthemostimportantissuetoconsiderinthedesignofFPGAbasedsystems. FPGAisbecomingmorepopularbecauseCMOStechnology

improvesatanexponenalratebutpowerdissipaondiffersalotcomparedtoASICbasedsystems.

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2.POWERDISSIPATION

ASICpowercomponents:Dynamicandstaccomponents.Junconleakageandtunnelinggatecurrentsare

notconsidered.

FPGApowercomponents(all3withdynamicand

staccomponents): Powerupcomponent. Configuraoncomponent.

Execuoncomponent.

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Firstterm=dynamicpower.ExponenalVdd. Secondterm=stacpower.

Vdd=voltagesourcesupply. C=parasiccapacitance. F=operangfrequency. =acvityofthecircuit. Vt=thresholdvoltageofthetransistor. S=slopefactor. U=ulizaonofaresource. Si=switchingacvityofaresource. i=numberofaresourceinaFPGA. Io=reversecurrent.

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3.POWERESTIMATIONTECHIQUEFOR

FPGAs

TheworkofJasonH.AndersonandFaridNajm,showsamethodbycalculangFPGApowerconsumponbyFPGAinterconnect.Theystudiedtwospecialproblems:

Switchingacvitypredicon. Interconnectcapacitancepredicon.

Theyproposeamodelforpredicngtheseparameterswhenaccurateroungdataisincompleteorunavailable.

InthisstudyitisuseXilinxVirtexIIPROcommercialFPGAforinvesgaon.

Switchingacvityisstudiedandexamineifzerodelayacvityvaluescanbeusedreliablyasesmatesofthecalculaonofrouteddelayacvityvalues.

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PrediconMethodologyOverview

Targetparameters: Netsrouteddelayacvitypredicon. Interconnectcapacitancepredicon.

Prediconparameters:valuesknowbeforeroungcompleon. Generalsteps:

AsetofbenchmarkcircuitsareselectedandmappedintoVirtexIIPRO.

Thecircuitsaredividedintotwosets:characteriza3onsetandtestset.

Thecharacterizaoncircuitsareanalyzedandprediconandtargetparametersvaluesareextracted.

Thenwiththeseparameters,theyperformmul-variableregressionanalysistoestablishanempiricalrelaonshipbetweenthese.

Applyprediconmodelstopredictcapacitanceandrouteddelayacvityvaluesfornetsinthetestcircuits.

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3.1SwitchingAcvity

SwitchingacvityofanetinaFPGAissignificantinthecalculaonofpower.

Wecanconceivedifferentviewsofthisacvity: Zerodelayacvity Logicdelayacvity Routeddelayacvity.

Whendelaysareconsidered,switchingacvitynormallyincreasesbecausetheintroduconofglitches.

Anunderstandingofhowswitchingacvitychangeswhendelaysareconsideredisimportantbecause:

FPGApowerdissipaonisdominatedbyinterconnecon. Duetothepresenceofprogrammableswitchesintheinterconneconnetwork,pathdelaysinFPGAsaredominatedbyinterconnectratherthanbylogicdelays,suggesngthetheeffectofglitcheswillbegreaterinFPGAsthaninASIC.

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SwitchingAcvityAnalysis

Simulaon-basedapproachusing10krandominputvector. Twodifferentvectorsets:representshighinputacvityand

lowinputacvity.

Tabulaonofcomparisonoftotalnumbertransioninthelogicandrouteddelaysimulaonsofeachcircuit,withthenumberoftransionsinthezerodelaysimulaon.

Significantincreaseinacvitywhendelaysareconsidered.Theincreaseinacvityaresomehowlessdrascwhenlowacvityvectorsetwereused.

Conclusion:zeroandlogicdelayacvityvaluesdonotnecessarilycorrelatestronglywithrouteddelayacvityvalues.

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SwitchingAcvityPrediconModel

ThecombinaonalpartofalogiccircuitcanberepresentedasaBooleanNetwork.

BooleanNetwork:directedacyclicgraph(DAG).Node:single-outputlogicfuncon.Edgesbetweennodes:input-output

dependenciesbetweenthecorrespondinglogicfuncons.

ForanodeyinacircuitDAG: Inputs(y)=thesetofnodesthatarefaninsofy.Depthofanodey(Dy)=thelengthofthelongestpathfromanyprimaryinputtoy.

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SwitchingAcvityPrediconModel

PRy:Predicvefunconthatrepresents

theseverityofglitchingonysoutputs.

GENy:Amountofglitchinggeneratedby

y.

PROPy:Amountofglitchingpropagated

byysinputs.

Dy:Depthofthenodey.

PLy:representthesetofdifferentpath

lengthsfromaprimaryinputtonode.

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GENy:Amountofglitchinggeneratedbyy.

PROPy:Amountofglitchingpropagatedbyysinputs.

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3.2Capacitance

EarlycapacitanceprediconforFPGAsisnotwellstudied,andisverydifferenttocalculateitinFPGAsthaninASICbecause

oftheprogrammablenatureofFPGAinterconnecon.

Earlyworksforesmatescapacitancevaluesusedgeneric,non-architecturespecificparameterstopredictit.

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InterconnectCapacitancePredicon

Model

CADapplicaonsaredesignedtocalculatecapacitanceveryquicklyastheyare

neededtotheinnerloopofdesignandsimulaonsalgorithms.Soparametersare

chosenbyalowcomputaonalcriteria.Someofthesearenotneededbuttheyare

menoned.

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Results

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4.Powerdissipaon:

FPGAvs.ASIC

Vdd=voltagesourcesupply.

Vt=thresholdvoltageofthetransistor.

ASIC:

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4.1ASIC

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ASIC

AllthesetechniquesareASICorientedand

theirefficiencywhenimplementedinFPGA

hasnotyetbeendemonstrated.

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4.2FPGA

Therearethreepowercomponents:

Power-upcomponentConfiguraoncomponent

Execuoncomponent

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4.3ExperimentalResults

ASIC:SynopsysDesignCompiler,PowerCompiler,VCS,PrimePower.

FPGA:QuartusIIv4.2,Powerplay.

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4.3.1Counters

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4.3.1Counters

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4.3.2HadamardTransformIP

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4.3.2HadamardTransformIP

IPpowerdissipaoninASIC

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4.3.2HadamardTransformIP

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5.CONCLUSIONS

FPGAdeviceswillnevercompetewithASICforapplicaonswherelowpowerisanissue

becausetheirintrinsicgenericarchitecture.

TheFPGAwillbeconfinedtocircuitprototypingforfunconalvalidaonor

reconfigurablecompung.

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BIBLIOGRAPHICREFERNCES

[1]AMARAAMARA,FredericyAMIEL,Thomas.FPGAvs.ASICforlowpowerapplica3onsInstutoSuperiordeElectronica

deParis.2005.

[2]ANDERSON,JasonH.NAJM,FaridN.Poweres3ma3onTechniquesforFPGAs2004.