feedback: principles & analysis

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Feedback: Principles & Analysis Dr. John Choma, Jr. Professor of Electrical Engineering University of Southern California Department of Electrical Engineering-Electrophysics University Park; Mail Code: 0271 Los Angeles, California 90089-0271 213-740-4692 [OFF] 626-915-7503 [HOME] 626-915-0944 [FAX] [email protected] (E-MAIL) EE 448 Feedback Principles & Analysis Fall 2001

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Feedback: Principles & Analysis. Dr. John Choma, Jr. Professor of Electrical Engineering University of Southern California Department of Electrical Engineering-Electrophysics University Park; Mail Code: 0271 Los Angeles, California 90089-0271 213-740-4692 [OFF] - PowerPoint PPT Presentation

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Page 1: Feedback:   Principles  &  Analysis

Feedback: Principles &

Analysis

Feedback: Principles &

Analysis Dr. John Choma, Jr.Professor of Electrical Engineering

University of Southern California Department of Electrical Engineering-Electrophysics

University Park; Mail Code: 0271Los Angeles, California 90089-0271

213-740-4692 [OFF] 626-915-7503 [HOME]

626-915-0944 [FAX][email protected] (E-MAIL)

EE 448

Feedback Principles & Analysis

Fall 2001

Page 2: Feedback:   Principles  &  Analysis

Overview Of Lecture

Overview Of Lecture

• Feedback System Representation System Analysis

• High Frequency Dynamics Open And Closed Loop Damping Factor Open And Closed Loop Undamped Natural Frequency Frequency ResponsePhase Margin

• High Speed Transient Dynamics Step Response Rise Time Settling Time Overshoot

65

Page 3: Feedback:   Principles  &  Analysis

Open Loop Model

Open Loop Model

X(s) Y(s)

Open Loop Amplifier:

A (s)ol

• Gain:

Parameters Zero Frequency Gain Frequency Of Zero Frequency Of Dominant Pole Frequency Of Non–Dominant Pole

Frequency Of Zero Can Be Positive (RHP Zero) Or

Negative (LHP Zero) Note That A Simple Dominant Pole Model Is Not Exploited

• Input And Output Variables Input Voltage Or Current Is X(s)Output Voltage Or Current Is Y(s)

Aol (0)zo

p1

p2

3

Aol (s) = Aol (0) 1 –

s zo

1 + s p1

1 + s p2

66

Page 4: Feedback:   Principles  &  Analysis

Open Loop Transfer Function

Open Loop Transfer Function

• Damping Factor:

Measure Of Relative Stability Measure Of Step Response Overshoot And Settling Time

• Undamped Natural Frequency: Measure Of Steady State Bandwidth Measure Of "Ringing" Frequency And Settling Time

• Poles Dominant Pole Implies Complex Poles Imply Identical Poles Imply

ol >> 1

ol < 1

ol = 1

4

Aol (s) = Aol (0) 1 –

s zo

1 + s p1 1 +

s p2

= Aol (0) 1 –

s zo

1 + 2 ol

nol

s +

s

2

nol 2

ol = 1 2

p2

p1

+

p1

p2

nol = p1 p2

67

Page 5: Feedback:   Principles  &  Analysis

Closed Loop Transfer Function

Closed Loop Transfer Function

• Loop Gain (Return Ratio w/r To Feedback Factor, f ):

• Closed Loop Gain:

Y(s)

Open Loop Amplifier:

A (s)ol

Feedback: f

X(s)+

– Acl (s) =

Aol (s) 1 + f Aol (s)

= Aol

(s) 1 + T (s)

T

(s) = f Aol (s)

T

(0) = f Aol (0)

T

(s) = f Aol (s) =

f Aol (0) 1 – s zo

1 + s p1 1 +

s p2

= T (0) 1 –

s zo

1 + 2ol

nol

s +

s 2

nol 2

Acl (s) = Acl (0) 1 –

s zo

1 + 2cl

ncl

s +

s 2

ncl 2

68

Obtained Through SubstitutionOf Open Loop Gain Relationship

Into Closed Loop Gain Expression

Page 6: Feedback:   Principles  &  Analysis

Closed Loop Parameters

Closed Loop Parameters

• Closed Loop Damping Factor:

• Closed Loop Undamped Frequency:• "DC" Closed Loop Gain:

T(0) Large For Intentional Feedback

T(0) Possibly Large For Parasitic Feedback

Aol (s) = Aol (0) 1 –

s zo

1 + s p1 1 +

s p2

= Aol (0) 1 –

s zo

1 + 2ol

nol

s +

s

2

nol 2

Acl (s) = Acl (0) 1 –

s zo

1 + 2cl

ncl

s +

s 2

ncl 2

T

(s) = T (0) 1 –

s zo

1 + s p1

1 + s p2

cl = ol

1 + T

(0)

– T

(0)

1 + T

(0)

nol 2 zo

ncl = nol 1 + T

(0)

Acl (0) = Aol (0)

1 + T (0)

Acl (0) 1

f

69

T

(0)

f Aol (0)

Page 7: Feedback:   Principles  &  Analysis

Closed Loop General Comments

Closed Loop General Comments

• Damping Factor Potential Instability Increases With Diminishing Damping Factor Potential Instability Strongly Aggravated By Large Loop Gain

Note: Open Loop Damping Attenuation By Factor Of Square Root Of One Plus "DC" Loop Gain

For Intentional Feedback Having Closed Loop Gain Of (1/f ), Worst Case Is Unity Gain (f = 1), Corresponding To Maximal T(0)

Open Loop Zero Closed Loop Damping Diminished, Thus Potential Instability

Aggravated, For Right Half Plane Open Loop Zero Closed Loop Damping Increased, Thus Potential Instability

Diminished, For Left Half Plane Open Loop Zero

• Undamped Frequency Measure Of Closed Loop Bandwidth Closed Loop Bandwidth Increases By Square Root Of One Plus

"DC" Loop Gain, In Contrast To Increase By One Plus "DC" Loop Gain Predicted By Dominant Pole Analysis

zo > 0

zo < 0

cl = ol

1 + T

(0)

– T

(0)

1 + T

(0)

nol 2 zo

ncl = nol 1 + T

(0)

70

Page 8: Feedback:   Principles  &  Analysis

Step Response Example Of Damping Factor Effect

Step Response Example Of Damping Factor Effect

Normalized Time

0.00

0.20

0.40

0.60

0.80

1.00

1.20

1.40

1.60

1.80

2.00

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Damping Factor = 5

3

1

0.8

0.5

0.2

0.05

Normalized Response

Transmission Zero Assumed To Lie At Infinitely Large Frequency

n t

71

Page 9: Feedback:   Principles  &  Analysis

Phase Margin Phase Margin

(v) = zo

p1 – tan –1

p2 – tan –1

– tan –1

• Unity Loop Gain Frequency Assumes Frequencies Of Zero And Second Pole Are Larger Than

• Substitutions: • Phase Margin

Difference Between Actual Loop Gain Phase Angle And –180; A Safety Margin For Closed Loop Stability

Approximate Phase Margin:

Since Can Be Negative, k Can Be A Negative Number

Result Is Meaningful Only For

u

ko

ko kp > 1

T

(s) = T (0) 1 –

s zo

1 + s p1

1 + s p2

u T(0) p1

p2 = kp u zo = ko u k

kp ko – 1

kp + ko

m tan –1 1 + k

T(0) T(0) – k

tan –1 (k)

Acl (s) = Aol

(s) 1 + T (s)

72

Page 10: Feedback:   Principles  &  Analysis

Phase Margin Characteristic

Phase Margin Characteristic

-60

-40

-20

0

20

40

60

80

100

120

-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3

Phase Margin (deg.)

k

T(0) = 1

T(0) = 5

T(0) = 100

73

Page 11: Feedback:   Principles  &  Analysis

Circuit Response Parameters

Circuit Response Parameters

Closed Loop Damping Factor:

Closed Loop Undamped Frequency:

Phase Margin:

Acl (s) = Acl (0) 1 –

s zo

1 + 2cl

ncl

s +

s 2

ncl 2

T

(s) = T (0) 1 –

s zo

1 + s p1

1 + s p2

u T(0) p1 p2 = kp u zo = ko u

k kp ko – 1

kp + ko

ol = 1 2

p2

p1

+

p1

p2

nol = p1 p2

ncl = nol 1 + T

(0)

cl = 1

2 kp

T

(0) 1 + T

(0)

kp T(0) 1 –

1 ko

+ 1 kp

2 1 –

1 ko

ncl = u

kp 1 + T

(0)

T(0) u

kp

m tan –1 1 + k

T(0) T(0) – k

tan –1 (k)

74

Page 12: Feedback:   Principles  &  Analysis

Closed Loop Example Calculation

Closed Loop Example Calculation • Given:

• Desire Maximally Flat Closed Loop Response, Which Implies • Computations:

• Requisite Phase Margin:

In Practical Electronics, Phase Margins In The 60s Of Degrees

Are Usually Mandated, Which Requires That The Non-Dominant Pole Frequency Be 2.5 -To- 4 Times Larger Than The Unity Gain Frequency

T(0) = 25 & ko = 5

cl > 1 / 2

cl kp

2 1 –

1 ko

1

2

kp > 3.125

k = kp ko – 1

kp + ko k = 1.8

f m tan –1 1 + k

T(0) T(0) – k

f m 63.28

75

Page 13: Feedback:   Principles  &  Analysis

Closed Loop Step Response: Problem Formulation

Closed Loop Step Response: Problem Formulation

X(s) Y(s)

Closed Loop Amplifier:

A (s)cl= 1/s = A (s)/scl

• Problem Setup: (Damped Frequency Of Oscillation)

• Normalized Variables: (Normalized Time Variable)

(Output Normalized To Steady–State Response)

(Error Between Steady State And Actual Output Responses)

dcl

ncl 1 – cl 2

x ncl t

yn (t)

y (t)

Acl (0)

(t) 1 –

y (t) Acl (0)

Acl (s) = Acl (0) 1 –

s zo

1 + 2cl

ncl

s +

s 2

ncl 2

Yn (s) Y (s)

Acl (0) =

1 – s zo

s 1 + 2cl

ncl

s +

s

2

ncl 2

M zo

ncl

ko kp

76

Page 14: Feedback:   Principles  &  Analysis

Closed Loop Step Response: Solution

Closed Loop Step Response: Solution

• Solution:

• Assumptions:

(Underdamped Closed Loop Response)

(Satisfied For Right Half Plane Zero)

cl < 1

zo + cl ncl > 0

x ncl t

Yn (s) = 1 –

s zo

s 1 + 2cl

ncl

s +

s

2

ncl 2

X(s) Y(s)

Closed Loop Amplifier:

A (s)cl= 1/s = A (s)/scl

yn (t) = 1 – (t)

77

(x) =

1 + 2 M cl + M 2

M

2 1 – cl

2

1/2

e – cl x Sin x 1 – cl 2

+

M zo

ncl ko

kp

= tan –1 M 1 – cl

2

1 + M cl

Page 15: Feedback:   Principles  &  Analysis

Closed Loop Step Response Example #1

Closed Loop Step Response Example #1

Norm

aliz

ed

Ste

p

Resp

onse

-0.5

0

0.5

1

1.5

2

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Damping Factor = 0.2

0.5

0.9

Q = 1

Normalized Time

78

M = 1M = 1

Page 16: Feedback:   Principles  &  Analysis

Closed Loop Step Response Example #2

Closed Loop Step Response Example #2

Norm

aliz

ed

Ste

p

Resp

onse

-0.25

0

0.25

0.5

0.75

1

1.25

1.5

1.75

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Damping Factor = 0.2

0.5

0.9

Q = 5

Normalized Time

Note That An Increase In TheFrequency Of The Zero Diminishes

Undershoot But Does NotSubstantially Reduce Overshoot

79

M = 5M = 5

Page 17: Feedback:   Principles  &  Analysis

Closed Loop Settling Time

Closed Loop Settling Time

• Observations Magnitude Of Error Term Decreases Monotonically With x Maxima Of Error Determined By Setting Derivative Of Error Term With Respect To x To Zero Maxima Are Periodic With Period First Maximum Of Error Establishes Undershoot Point Determine Second Maximum And Constrain To Desired Minimal Error

• Procedure Let Be The Normalized Time Corresponding To Second

Error Maximum Let Be The Magnitude Of Error Corresponding To If Is The Desired Settling Error, Represents The Settling Time

Of the Circuit

xm

xm

m xm

(x) =

1 + 2 M cl + M 2

M

2 1 – cl

2

1/2

e – cl x Sin x 1 – cl 2

+

yn (x) = 1 –

(x)

80

m

Page 18: Feedback:   Principles  &  Analysis

Closed Loop Settling Time Results

Closed Loop Settling Time Results

• Results:

• For Large M (Far Right Half Plane Zero):

yn (x) = 1 – (x)

xm

1 – cl 2

2 4 – kp

m exp –

kp

4 – kp

(x) =

1 + 2 M cl + M 2

M

2 1 – cl

2

1/2

e – cl x Sin x 1 – cl 2

+

xm = 1

1 – cl 2

+ tan

–1 1 – cl

2

cl + M

m =

1 + 2 M cl + M 2

M

e –cl xm

81

Page 19: Feedback:   Principles  &  Analysis

Closed Loop Settling Time Example

Closed Loop Settling Time Example

• Requirements Settling To Within One Percent In 1 nSEC Assume Zero Is In Far Right Half Plane (Reasonable

Approximation For Common Gate And Compensated Source Follower; First Order Approximation For Common Source)

Assume Very Large "DC" Loop Gain

• Computations

Second Pole Must Be At Least 2.7 Times Larger Than Unity Gain Frequency

Required Phase Margin: f m tan–1 (kp ) = 69.9

xm = ncl tm 2

4 – kp = 5.575 ncl 2 (887.2 MHz) ;

ncl u kp

u 2 (537 MHz)

82

m exp – kp

4 – kp 0.01 kp > 2.73 ;