Community Leader in opensource EDA deployment.

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http://chitlesh.fedorapeople.org/FEL fedora­electronic­lab­list@redhat.com

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Empowers you with an advancedhardware design and simulation platformfor micro­nano electronics engineering.Design/Model Simulate ASICs Evaluation Boards

EDA­FEL­012/PP#02.00

Initiated 3 years ago by providing a handful set ofdesign tools, now Fedora Electronic Lab is a matureddesign and simulation platform for Micro­NanoElectronics Engineering and Embedded Systems.Fedora Electronic Lab, a subset of Fedora (with 15million users around the world), is also available forfree. FEL has already been adopted by manyuniversities, engineers and startups.

The software provided benefits both EDA engineersand ASIC designers engaged in chip design.– Analog/Digital Circuit design and simulation– Perl modules for CAD engineers– Verification and Documentation– Eclipse IDE for Embedded Systems Development– Micro Controller Programming and Simulation

Design ToolsHistory

FEL empowers you with a quality­class Linux distribution, coupled a maturedEDA platform for your advanced electronic hardware design and simulation !– Design tools for Application­Specific Integrated Circuit (ASIC) design flows.– Extra standard cell libraries supporting upto a feature size of 0.13um.– Interoperability between EDA packages to achieve different design flows.– Collection of Perl modules is offered to extend Verilog and VHDL support.– Collaborative development and code review methodologies.– Tools for embedded/ARM design.

FEL also empowers your entreprise Linux distributions(CentOS­5/RHEL­5) with EPEL­5 repository.

Proven community Leader in innovative opensource software development

VLSI Design Layout & ChecksIncludes– A continuous DRC that operates in background and maintainsan up­to­date picture of violations.– A hierarchical circuit extractor that only re­extracts portions ofthe circuit that have changed.– Plowing that permits interactive stretching and compaction.– Routing tools that work under and around existing connections.– Logs and corner stitching to achieve efficient implementations.Dedicated to training in sub­micron CMOS VLSI designwith full editing facilities.Supports technology files by the MOSIS foundry service.Switch­level simulation of the layout,by considering transistors as ideal switches,or using RC time constants to predict the relative timing of eventsthrough extracted capacitance and lumped resistance values.Ensures that layout connectivity matches the logical design representedby the schematic or netlist before tapeout by automatically– extracting devices and nets formed across layout hierarchy and,– comparing them to the schematic netlist. (LVS)Generates GDS II stream format and Caltech Intermediate Form (CIF)from a given layout.Achievement : Thick­film circuit layout using the Magic layout editor.

Digital Design

Fedora Electronic Lab was designed to help youcreate a chip (mixed­signal supported) fromspecification, simulate the HDL designs, conductfunctional verification, do physical design andfinally handoff your chip for manufacturing.FEL also includes tools to help you createevaluation boards for your chips.

Supports both VHDL and Verilog designs.Implementation of the VHDL language

o IEEE 1076­1987 standardo IEEE 1076­1993 standardo the protected types of VHDL00

(aka IEEE 1076a or IEEE 1076­2000)o and non­standard third party libraries.

VPI functionality and PLA capabilities.Pretty printing or cross references generation in HTML.Makefile generation for any component in a design.A graphical waveform viewer with TCL support.A Verilog simulator and synthesis tool for IEEE 1364­2001 standard.Logic optimizations with espresso.

Key Features:

Fedora's HDL simulation environment enablesyou to verify the functional and timing modelsof your design.Automatic layout generation from HDL filesand standard cell libraries up to a feature sizeof 0.13µm can be carried out on Fedora 12.

Focus on your complex designs and users should not compile EDA software but use them out of the box.

Verilog­mode is being used by thousands of engineers world wide. The Verilog AUTOS are in useby many of the leading IP providers, including IP processor cores sold by MIPS and ARM.

Extra hardware modelling capabilities

(Context­sensitive highlighting, Auto­Indenting, Macro expansion, ...) capabilitiesReduce Verilog Coding time with Emacs

Extend home grown design flow methodology for professional use.Take full advantage of the existing EDA tools on Fedora (both frontend and backend)Have a quick grip on the gate count and static timing analysis.Reduce the gap between proprietary EDA tool and opensource EDA toolSpin one's own home grown IP core portfolio. (DDS,SPI controller, I2C controller...)Auto­generate code, e.g. testbenches, stimulus/ATPG vectors, code wrappers, etcExecute various operations from a multi­tool environment in a design flow.Analyze large quantities of output data quickly and efficiently.

Make full use of Parametrized­based design with Perl modules for both Verilog and VHDLThe Perl modules being shipped with Fedora Electronic Lab empower digitaldesigners and CAD engineers with methodologies to:

From project definition via Synthesis, physical optimizationand layout design flows till CIF/GDSII handoff, Fedoraensures that with the 7 extra standard cells (up to a featuresize of 0.13µm), designers have adequate design tools.GDSII files created can even be used on analog layouteditors to benefit with Analog/Mixed signal capabilities.

Frontend to Backend ASIC design flows

Use a 3D view representation(generated from GDSII data) ofthe physical layout in teaching.

PCB layout editors are provided tohelp you create evaluation boardsof your chips.Prototyping can be automatedwith the wide collection of Perlmodules, provided under theFedora umbrella.

– General Purpose Circuit Simulatorso Nonlinear AC/DC analysiso Transient, Fourier analysiso S­parameter and harmonic balance analysis

– Beyond Spice capabilities:Level 49, BSIMv4 and EKV implementations

– Multi­lingual, ablilty to mimic different variants of spice, andalso supporting the newer languages like Verilog­AMS

Circuit SimulationBuild interactive schematics for your custom designs.Various types of netlists can be extracted, simulated or used for PCB layout.All spice simulators included possess mixed­mode capabilities.

– Draws publishable­quality electrical circuit schematic diagrams.– Circuit components can be retrieved from libraries which are fully editable.– Easy­to­use GUI with TCL interface or GTK interface.– Coupled with espresso and eqntott, tclspice can be used for mixed signal simulations.

A professional­quality printed circuit board designenvironment along with :­ schematic capture, simulation, prototyping attributemanagement,­ bill of materials (BOM) generation and netlisting intoover 20 netlist formats.Footprints can be generated by simple Perl scripts.These Perl scripts can be maintained under a revisioncontrol sytem with Eclipse IDE.

Includes a rats nest feature, design rule checking, and can provide industry standard RS­274­X (Gerber), NCdrill, and centroid data (X­Y data) output for use in the board fabrication and assembly process.Offers high end features such as an autorouter and trace optimizer, which can tremendously reduce layout time.Creates PCB of up to 8 layers with an unlimited number of components and nets.Includes a viewer for Gerber files (RS274X), which supports NC­drill and Excellon formats.

PCB Layout Design

Fedora also ships the kicad version and fped which are required for OpenMoko's (an opensource smartphone) development.

Embedded Systems Development

µController Programming

ARM and AVRDevelopment SystemSupports the Atmel's STK500 and thePPI (parallel port interface) programmertypes.Includes– Cross compilers and Programmers– a Universal In­System Programmerfor Atmel AVR and 8051– a Program for interfacing the AtmelJTAG ICE to GDBSmall Device C CompilerIncludes openocd (On Chip JTAGDebugger for arm processors)

Supported compilers :the Small Device C Compiler, the GNU PIC Utilities, the PICC compilers,the PIC30 toolchain, the C18 compiler, the JAL and JALV2 compilers,the CSC compiler, and the Boost compilers.

Ease to use IDEs for microcontrollers circuit design, simulation and programmation to serial, parallel and USB ports.IDE includes an oscilloscope and a flowchart integration.Supported debuggers : ICD2 and GPSim.Supported programmers : ICD2, PICkit1,PICkit2 & PicStart+ programmers.Supports 8051 and AVR and Binutils for SPU on IBM Cell processors.Includes 8051 and 8085 simulators.

Copyright © 2003 ­ 2009 Red Hat Inc and Others. All rights reserved.

It can be downloaded freely as a LiveDVD.

Download the latest version 12.All Fedora Electronic Lab packages can be freelyinstalled via yum from official repositories.

Website :http://chitlesh.fedorapeople.org/FEL

technical support :Fedora Electronic Lab Mailing List

AboutFedora Electronic Lab is a subproject of theFedora Project dedicated to EDA tools and openhardware content. We develop and provide each6 months a new version release for free. Our goalis not only package those tools for you, but shapethose tools to satisfy design methodologies.