Filip Maksimovic Mike Lorek Spring 2015 Adapted from past EE141 labs

EE 140/240A ­ Full IC Design Flow Tutorial

1. Server Login

For server access, we recommend you use a remote desktop client called x2go. This program uses accelerated X11 tunneling to reduce the latency associated with using applications over SSH. To use it, download the client, and click the ‘New Session’ button in the top­left corner. For the host name, use one of the t7400 servers (t7400­1 through t7400­7). Login should be the login of your instructional account. The desktop environment can be changed with the ‘Session Type’ option; GNOME seems to work the best with Cadence. Leave everything else at the default setting and type in your credentials to start a remote connection. Note: if you have a Mac, you will need to install XQuartz to use x2go. If, for whatever reason, you do not want to use x2go, or x2go is not working, you can directly SSH from a console (use Putty for Windows, or terminal in Mac OS X). This is done with the following command:

ssh ­X username@t7400­1.eecs.berkeley.edu

t7400­1 can be replaced with any of the other t7400 servers. From there, you will have access to a terminal from which you can proceed with the lab.

2. Cadence Setup & Launch

Cadence is the one­stop shop for nearly all of your analog circuits needs. To set up Cadence on your instructional account, navigate to your home directory (you can do this by typing: cd ~ if you’re lost) and execute the following script:

/share/b/bin/cadence­setup.csh

When prompted to enter a directory, type: ee140 and hit Enter. Navigate to the newly created folder (cd ~/ee140 should do the trick), and type:

icfb2 &

This will open Cadence! Every time you want to start it, just navigate into the ee140 directory and type icfb2 &. There’s no need to run the setup script again. For

Cadence documentation, go to https://inst.eecs.berkeley.edu/~inst/pub/ or click the “help” button in Cadence. You can also harass your GSIs. NOTE: if you have more than one session running Cadence on the servers, you will likely experience very slow performance. When closing the remote desktop window, x2go will, by default, suspend your session. Next time you connect using x2go, you should be presented with the option to resume the suspended session. This is a nice feature because you can leave your design environment open. To terminate a session, please exit Cadence by closing the icfb console window, and log out of your session from your GNOME/other remote desktop window.

3. Creating a Schematic View

If the Library Manager doesn’t open automatically with the icfb console window, open it by clicking Tools ­> Library Manager. You should see a window pop up that looks like this:

In Cadence, there is a relatively straightforward hierarchical organizational structure. Libraries (the furthest left column in the library manager) are collections of Cells, and Cells are collections of Views. The first thing that you will need is a new library. To do this, go to the library manager and click File → New → Library. A new window will pop up. Type “lab1” in the name field and press OK.

At this point, Cadence will prompt you for something called a Technology File. The technology file is a library or group of libraries that all cell views inside of your new library will automatically reference. This basically means that you will not have to import models every time you run a new simulation. To import the technology file for this class, click the ‘Attach to an existing techfile’ button, press ok, and use the drop down menu to select ‘gpdk090’. This stands for general­purpose design kit, 90nm. General purpose refers to the type of process (typical choices are general purpose ­ GP, low power ­ LP, high performance ­ HP, and radio frequency ­ RF), and the 90nm refers to the minimum feature size available.

Now that you have a library, you can create your first schematic. Select your new ‘lab1’ library in the library manager, and click File → New → Cell View. When prompted, name the new cell view “inverter” and select ‘Composer­Schematic’ from the drop­down menu. The schematic editor should open up. Now we can build a virtual representation of our circuit at the transistor level.

To instantiate circuit elements in the schematic, press the ‘i’ key. This will bring up a menu with fields ‘Library’, ‘Cell’, ‘View’, and ‘Names’. To put an NMOS transistor into your schematic, use the “Browse” button to get to gpdk090 → nmos1v → symbol. You can also type these references into the fields manually. As soon as you do this, you will be prompted with lots of new options. What you are actually doing at this point is instantiating a parameterized cell, or P­cell for short. You can parameterize the transistor gate width, length, and fingers. Your choices will be reflected in the schematic. For now, let’s stick with a minimum­sized transistor with a Length of 100nm and a Width of 120nm. Press the ‘hide’ button or hit the Enter key in the instantiate menu and put the transistor into your schematic. If you ever want to change a p­cell’s properties after placing it in the schematic, select it by clicking on it and pressing the ‘q’ key. Following those same instructions, instantiate a PMOS transistor (pmos1v) with a 100nm length and a 120nm width. In addition, instantiate global symbols ‘vdda’ and ‘gnd’ from the analogLib library. Now that all of our components are in the schematic, you will need to connect them together. Press the ‘w’ key to open up the ‘Add Wire’ window. This will allow you to make connections between nodes. Simply click on the red squares ­ the contacts ­ in the schematic view, and make the connections needed for an inverter circuit. Remember to connect the bulk terminals of the NMOS and PMOS devices to gnd and vdda respectively.

To navigate the schematic, use the arrow keys on the keyboard to pan around. You can zoom in/out by clicking the magnifying glass buttons on the toolbar, or with the hotkeys control­Z/shift­Z. You can also zoom to a specific area by click­dragging with the right mouse around the region of interest. The last thing that you need is two pins to indicate the input and output of your inverter. This way you cell view can interface with higher level schematics (more on this later). Press the ‘p’ key to open up the ‘Add Pins’ window, type the names of your pins with spaces between them (I used input and output here, you can use whatever you like). Make sure that you select ‘InputOutput’ in the direction drop­down menu, click ‘Hide’, place your pins in the schematic, and wire them up.

If you followed the instructions carefully, your schematic should look something like this:

When it does, press the ‘Check and Save’ button (it looks like a box with a check mark). Leave the schematic editor open for now; we’ll need it for the later portions of the lab. One more quick thing to note before you create a symbol. Sometimes it is useful to label nodes instead of directly connecting them with a wire. To connect two nodes, just label them with the same name! To create a label, press the ‘l’ key, type in the desired node name, and click on the wire in the schematic.

4. Creating a Symbol View

Now that your schematic is finished, go back to the library manager and highlight your ‘inverter’ cell view in the lab1 library. Click File → New → Cell View. Now, select the Composer­Symbol tool to create a symbol view and open the symbol editor. The first thing you will need to do is synchronize the pins in the schematic and in the symbol. To do this, click Edit → Update Pins from View. Any discrepancies between the pins in the symbol view and in the schematic view will be listed here. Given that your symbol is non­existent at this point, your list will have the input and output pins.

Notice that vdda and gnd do not show up here. As mentioned earlier, those are global pins that are shared throughout the design automatically. After you press OK, you will have the opportunity to place the missing pins in the symbol editor. Click to place the pins, rotating by clicking the right mouse button if needed. Note that the red dot is the actual point where a wire will connect, so put it towards the edge of the symbol. Draw various shapes using Add → Shape to make your symbol look like an actual inverter. Save your symbol view when finished.

5. Circuit Simulation with ADE

Before you simulate anything, you will need to build a test bench for your inverter. To do this, create a schematic called ‘inverter_tb’ in the lab1 library. Once you do that, instantiate a cell called ‘vpulse’ from the analogLib library. When you instantiate the voltage source, enter the string vin for the ‘DC Voltage’ property. Assigning parameters to variables allows you to change them easily and sweep them in the simulator. Set the two vpulse voltage levels to 0V and 1V, and set the rise and fall times to 10ps. The pulse width should be 10ns and the period should be 20ns. Now, instantiate the inverter symbol that you created only moments ago. Don’t forget to connect vdda to a 1V supply! The ‘vdc’ source in the analogLib library should be used here. Finally, connect all the circuit components together properly with wires. You should also label the input and output nets to easily identify them when viewing the simulation results. Your testbench schematic should look something like this:

Hit check and save like before. You will get a few warnings that you can safely ignore. Now you can finally set up the simulation for your inverter. Click Tools → Analog Environment to open up the legendary Virtuoso Analog Design Environment (ADE). This tool is a little bit obtuse (it was designed in around 1995) but extremely

powerful. Let’s start with two simple simulations: a dc simulation to determine our inverter’s voltage transfer characteristic, and a transient simulation to determine its propagation delay. Let’s first begin by setting the design variables. Click on Variables → Edit to open up the Design Variable Editor. Then click the ‘Copy From’ button at the bottom. Remember how you set the DC voltage of the vpulse source to a variable? Here is where you can use it in your simulation. Set the default value to 1V so that your variable window looks like this:

Now we can set up the simulation. Click on Analyses → Choose to open the analysis window. Select ‘dc,’ set the sweep variable to ‘Design Variable,’ and use ‘vin’ as the variable name. Sweep vin from 0V to 1V with a step size of 10mV. Click OK. Follow the same procedure to create a transient simulation with a duration of 100ns. To make the simulator automatically plot the desired waveforms, click Outputs → To Be Plotted → Select on Schematic, and click on the input and output nodes that you labeled earlier. Afterwards, your ADE window should look like this:

To run the simulation, click the green traffic light on the right side, say OK to the Welcome to Spectre window (after clicking the ‘Do not show this text again’ button, of course) and the simulation will run. You should see the input and output waveforms for the dc and tran simulations plotted automatically. From the output vs. input dc sweep simulation, find the gain by estimating the slope of the curve near output = VDD/2. Press the ‘d’ key to bring up a pair of cursors, position them correctly, and observe the cursor values/slope at the bottom of the window. Make note of the DC gain for your lab report. People would normally associate an inverter with digital circuits, but it turns out that it makes a decent amplifier! The propagation delay of the inverter is defined as the time between the input crossing VDD/2 and the output transitioning to VDD/2. Use the cursors on the transient simulation waveforms to measure the high→low and low→high propagation delays. Record these values for your lab report.

6. Creating a Layout View

Go back to the library manager and create a new inverter cell view as you did previously. This time, select ‘Virtuoso’ as the Tool for your new cell view. This will open up an empty layout editing view.

The very first thing that we will do is draw rulers to specify the outline of our inverter layout. Press the ‘k’ key and use the rulers to draw a 3.0 µm x 1.6 µm rectangle. Using this as a template, we can start drawing the physical manifestation of our schematic. If it helps, you may want to keep your schematic view open so that you can refer to it while working on the layout. The first thing that we will do is place the metal lines for vdda and gnd. Do this by first pressing the ‘p’ key. You may have noticed earlier that a window titled ‘LSW’ opened after you created the layout. With the ‘Create Path’ window still open, select the Metal1 drw in the LSW window. This will tell the path creator in which layer you wish to draw a shape. Increase the width of the path to 0.6 µm and place paths across the top and bottom of your rectangle so that the edge of the metal is flush with the boundary of your square: Navigating the layout is the same as the schematic, repeated here for convenience. Use the arrow keys on the keyboard to pan around. You can zoom in/out by clicking the magnifying glass buttons on the toolbar, or with the hotkeys control­Z/shift­Z. You can also zoom to a specific area by click­dragging with the right mouse around the region of interest.

Next, we will instantiate the transistors. This is done in almost the same way as in the schematic editor. Press the ‘i’ key and navigate to the layout view of the transistors. Enter the desired width and length for the PMOS and NMOS transistor P­cells to match your schematic, and place the devices in your layout. Press shift­F so Virtuoso draw all layers in the hierarchy to see inside the transistor P­cell.

What do the different layers mean? Use their names in the LSW window to determine the purpose of each layer and how it is used to create a MOSFET. Where is the gate? Where are the source, the drain, and the channel? The next step is to start making connections between the contacts. Connections are typically made using low resistivity materials, like metals. Sometimes, it is possible to do routing using polycrystalline Silicon (that’s the Poly layer) but only over very short distances. Draw a 0.12µm metal trace between the two drains of the transistors, and draw a 0.1µm Poly trace connecting the two gates. One more thing for later: instantiate a Metal1­to­Poly connection. To do this, hit ‘i’ to instantiate a cell, and

browse to gpdk090 → M1_POLYc. Place the contact so that it contacts the Poly path that you placed earlier. After you make those connections, your layout should look something like this:

We’ve connected the gates, the drains, and soon we will connect the sources to the supply rails. But these FETs are four­terminal devices. Where is the contact to the bulk? Since CMOS traditionally uses a P­doped substrate, the PMOS device needs to be surrounded by an N­well to operate properly. The P­cell includes an N­well automatically, but it is not large enough to add a contact for biasing. To do this, press the ‘r’ key and draw a rectangle that surrounds the PMOS transistor. Make sure that the N­well rectangle also overlaps with the vdda metal layer that you drew earlier.

Now that the two main transistor structures have been drawn (gate, source, drain, appropriately doped channel regions) we can make the body contacts. Once again, use the ‘i’ key to instantiate an M1_PSUB contact and an M1_Nwell contact. After placing them on the appropriate vdda and gnd paths, select one of them and press the ‘q’ key to edit the properties of the contact. To reduce the contact resistance between the metal and the bulk, set the Columns fields of both contacts to 3. Your layout should now look something like this:

As a final step, use 0.12 µm wide Metal 1 traces to connect the sources of both transistors to the appropriate supply rails. In addition, draw metal paths extending the input and output connections to the far left and far right of the cell boundary.

7. Design Rule Checking (DRC)

Now that your inverter cell layout is finished, we will run the DRC checker to verify that your drawn layers obey all of the design rules. Design rules are provided by the foundry performing the IC fabrication to (ideally) ensure that the IC devices you have drawn will perform as desired after the chip is made. Open the Design Rules Manual (DRM) to get a feel for some of the design rules for the various layers. The DRM can be opened with with the following shell command: evince /home/ff/ee141/gpdk090_v3.9/docs/gpdk090_DRM.pdf Switch back to the Virtuoso window to run DRC. Click the ‘Verify’ menu at the top of the Virtuoso window, then click ‘DRC’. Uncheck the ‘Rules Library’ box. Enter the following for ‘Rules File’: /home/ff/ee141/gpdk090_v3.9/diva/divaDRC.rul

Your DRC configuration window should look like this:

Click OK to run the DRC checker. The results of the DRC run will be displayed in the icfb window. You will likely have errors after your first DRC attempt. The errors can be difficult to understand initially; try to decode what needs to be fixed, and ask your GSI if you get stuck. When you have no DRC errors in your layout, you will see the following in the icfb window following the DRC run:

8. Adding Pins to the Layout View

Next, we must add pins to the layout to define the inputs and outputs in this cell view. These pins need to match those defined earlier in the schematic and symbol views. Click the ‘Create’ menu at the top of the layout window, followed by ‘Pin’. The ‘Create Symbolic Pin’ menu should open. You can enter multiple pin names separated by spaces in the ‘Terminal Names’ dialog box to place multiple pins successively. Enter “input output vdda! gnd!” in this box. The ! notation designates a pin as being global and shared by the entire design hierarchy. You can create a pin on many different layers. Change the ‘Pin Type’ option to ‘Metal1_T’; this places the pins in the metal 1 layer. Click the ‘Display Pin Name’ checkbox so a text box displaying the pin name is created along with the pin itself. Click the ‘Display Pin Name Option’ button and change the height to 0.1. Your ‘Create Symbolic Pin’ dialog box should look like this:

Click the ‘Hide’ button to switch the focus back to your Virtuoso window. Position the first pin on the left edge of the input metal 1 wire, as this is where a signal from the preceding stage would interface with the cell. After placing the pin, your cursor will now control the placement of the input pin label. Click again to place the label in an appropriate place. After you have placed the ‘input’ pin label, the pin placement process will repeat automatically for each pin you entered in the ‘Terminal Names’ box above. Place the output, vdda!, and gnd! pins and labels in the appropriate places. Your layout after adding pins should look similar to the screenshot below.

9. Layout vs. Schematic Verification

The next step in the IC design flow is to check whether the polygons you drew in your layout view actually create the devices and connections you made in the schematic view of the circuit. To do this, we will run a layout vs. schematic (LVS) checker. From the Virtuoso layout window menu bar, click Assura → Technology. In the ‘Assura Technology File’ dialog box, enter the following: /home/ff/ee141/gpdk090_v3.9/assura_tech.lib Click OK. In the Virtuoso menu bar, click Assura → Run LVS. Make sure the ‘Technology’ option is set to ‘gpdk090’. Your ‘Run Assura LVS’ menu should look like this:

Click OK to run LVS. If your layout matches your schematic, you will see the following message:

If you have any LVS errors, please correct them by making the appropriate adjustments to your layout. If you have to change your layout, be sure to run the DRC check again to verify that your updated layout also meets the design rules. At this point, your layout now passes DRC and LVS. This is an important milestone in the IC design process ­ nice work! Next we will examine how the physical design of the circuit (layout) impacts its performance.

10. Parasitic Extraction with Assura We will now extract the parasitic resistances and capacitances from the layout view. From the Virtuoso menu bar, click Assura → Open Run. Make sure ‘Run Name’ lists the current cell you are working on (ie inverter). Click OK. From the Virtuoso menu bar, click Assura → Run RCX. Adjust the settings in the Setup, Extraction, and Netlisting tabs to match the screenshots below.

Click OK to run the RCX extractor. You should see the following message indicating a successful run:

Return to the Library Manager, and your inverter cell should now have a new view named ‘av_extracted’. Open this view. It should look something like a combination of your schematic and layout views. If you zoom in and look closely, you will see that small parasitic R and C components are present.

11. Parasitic Extracted Circuit Simulation

Finally, we are going to simulate the inverter with your layout’s extracted parasitics included in the circuit. First, we need to create a ‘config’ view for the inverter_tb cell. In the Library Manager, create a new view for your inverter_tb cell. Change the tool to ‘Hierarchy Editor’, make sure the cell name is inverter_tb, and click OK. In the ‘New Configuration’ window, click the ‘Use Template’ button and select ‘spectre’ as the template. This will populate the fields in the ‘New Configuration’ window. At the top right of the window, change the ‘Top Cell View’ field from ‘myView’ to ‘schematic’. Click OK to create the hierarchy configuration view. Your window should look like the screenshot below.

Click View → Update in the menu bar to update the hierarchy. This may bring up a window asking you to save other cell views; if so, click OK. Now, right click on the inverter cell and select Set Cell View → av_extracted. The hierarchy editor window should look like the following screenshot:

Update the hierarchy again, and then Save the configuration. Open the Library Manager window and double click the inverter_tb ‘config’ cell view. This prompts you to open the hierarchy configuration (window in previous screenshot), and/or the top cell view. You should already have the configuration window open, so just open the top cell view. You should now see your inverter_tb schematic, but look at the top of the window ­ the config view is open. Click on your inverter symbol, then press ‘x’ to descend into the inverter cell. Click OK. You should now see the av_extracted view that you opened earlier. Your inverter cell is now represented by the parasitic extracted circuit in your testbench! Press ‘b’ to ascend one level in your circuit’s hierarchy, returning to the top­level testbench schematic. Click Tools → Analog Environment to open the simulator. Click Simulation → Netlist → Create. The netlist to be simulated, with the parasitics included, should be

displayed. Look at the parasitic components to get a feeling for their values. Save a copy of the netlist (either text or screenshot) for inclusion in your lab report.

Configure ADE to simulate the circuit as you did previously. Use the wave viewer again to measure the DC gain, and rising/falling propagation delays. Are the simulation results different with the annotated layout parasitics?

12. Deliverables

A. Schematic simulation a. DC gain b. High­low propagation delay c. Low­high propagation delay

B. Screenshot of finished inverter layout C. Netlist with extracted parasitics D. Extracted simulation

a. DC gain b. High­low propagation delay c. Low­high propagation delay