final presentation implementation of dsp algorithm on soc student : einat tevel supervisor :...
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Final PresentationFinal Presentation
Implementation of DSP Algorithm on SoC
Student : Einat TevelStudent : Einat Tevel
Supervisor : Isaschar WalterSupervisor : Isaschar Walter
Accompanying engineer : Emilia Burlak Accompanying engineer : Emilia Burlak
The project is conducted withThe project is conducted with
cooperation of Rafael. cooperation of Rafael.
winter 2003/2004winter 2003/2004
Project Goals - ReviewProject Goals - Review Studying and investigating the architecture of Studying and investigating the architecture of
System on Programmable Chip (SoC).System on Programmable Chip (SoC). Deciding on the Software/Hardware partition to Deciding on the Software/Hardware partition to
be implemented.be implemented. Implementing a signal processing algorithm on Implementing a signal processing algorithm on
the chosen platform.the chosen platform.Second Semester:Second Semester:
Implementing a signal processing Implementing a signal processing algorithm based on a FIR/IIR Filter with algorithm based on a FIR/IIR Filter with Programmable parameters.Programmable parameters.• Simulating and checking the code of the Simulating and checking the code of the
algorithm in hardware and software. algorithm in hardware and software. • Running the algorithm on the board.Running the algorithm on the board.
Project ScheduleProject ScheduleSecond SemesterSecond Semester
Defining the algorithm - CIC Defining the algorithm - CIC Filters.Filters.
Design - Block Scheme.Design - Block Scheme.
Hardware.Hardware.
Software.Software.
Verification.Verification.
CIC Filters CIC Filters Overview Overview
Cascaded Integrator-Comb Filters.Cascaded Integrator-Comb Filters. Multirate filters used for realizing Multirate filters used for realizing
large sample rate changes in digital large sample rate changes in digital systems.systems.
Multiplierless structures, consists only Multiplierless structures, consists only of: Adders, Subtractors and of: Adders, Subtractors and Registers. Registers.
Decimation.Decimation. Interpolation.Interpolation.
CIC Filters CIC Filters Structure Structure
Cascade of Integrators.Cascade of Integrators. Resampling Switch (decimate/expansion).Resampling Switch (decimate/expansion). Cascade of Differentiators. Cascade of Differentiators.
CIC FiltersCIC Filters Parameters Parameters
Number of Stages (N).Number of Stages (N). Rate Change Factor (R).Rate Change Factor (R). Differential Delay (M).Differential Delay (M).
CIC FiltersCIC Filters Hardware/Software Hardware/Software
Hardware:Hardware: Generic implementation of Decimator.Generic implementation of Decimator. Generic implementation of Interpolator.Generic implementation of Interpolator.
Software:Software: Filter parameters : N, R, M.Filter parameters : N, R, M. Filter Mux Select : Dec/Int.Filter Mux Select : Dec/Int. Data input for filtering.Data input for filtering.
All wrapped into one in SoC.All wrapped into one in SoC.
DesignDesignSystem ComponentsSystem Components
plb2opbbridge
O PB C ICFilters
OPB
UARTSDRAM
G PIO(LEDs)
PLB
PPC 405
Monitor
UARTUART
send/receive send/receive files.files.
PPC405 PPC405
Software.Software. OPB CIC Filters OPB CIC Filters
Hardware Core.Hardware Core. LEDs.LEDs. SDRAM.SDRAM.
DesignDesignSystem FlowSystem Flow
plb2opbbridge
O PB C ICFilters
OPB
UARTSDRAM
G PIO(LEDs)
PLB
PPC 405
Monitor
- Receiving file from Receiving file from PC.PC.
- File read and File read and analyzed.analyzed.
- Sending parameters Sending parameters and data to filters.and data to filters.
- Receiving processed Receiving processed data from filters.data from filters.
- Sending data to PC.Sending data to PC.
DesignDesignBlock Scheme - TopBlock Scheme - Top
- OPB SW-HW IntfcOPB SW-HW IntfcGenericGeneric SW-HW SW-HW
interface.interface.
- CIC FiltersCIC FiltersImplementation of Implementation of
the CIC Filters the CIC Filters modules.modules.
OPB
O PB SW -HW
Intfc.
Data
Addr CICFilters
Block Scheme Block Scheme OPB SW-HW IntfcOPB SW-HW Intfc
Using Using IPIF (IP Interface): a portable, pre-designed bus interface, that takes care of the bus interface signals, bus protocol and other interface issues.
Data
Addr
IP IF SW -HWIntfc
rd
wr
Data
Addr
Block Scheme Block Scheme SW-HW IntfcSW-HW Intfc
Consists of:Consists of:• Address Decoder.Address Decoder.• FIFOs.FIFOs.• Control/Status Control/Status
Regs.Regs.• Other signals:Other signals:
• sw_rstsw_rst• paramsparams
Data
FIFO IN
FIFO OUT
fifo_in_dout
fifo_out_din
Control Reg.
AddressDecoder
Status Reg.
Data
fifo_in_en
start
finish
control_reg_valid
fifo_in_rd_en
fifo_out_wr_en
wr
rd m ux_select
finish_en
sw_rst
S tages_num
Sam ples_rateDiff_delay
addr
Block Scheme Block Scheme CIC FiltersCIC Filters
Consists of:Consists of:• CIC CIC
Decimator.Decimator.• CIC CIC
Interpolator.Interpolator.• CIC Filters CIC Filters
Intfc.Intfc.
C IC _D E C
C ICFilte rsIn tfc.
C IC _IN T
start
finish
fifo_in_dout
m ux_select
fifo_in_rd_en
m ux_select_en
fifo_out_din
fifo_out_wr_en
filter_Din_en
filter_Din
m ux_Select
filter_Dout
filter_Dout_en
sw_rst
filter_param s (x3)
HardwareHardware
Code written in VHDL :Code written in VHDL :• Generic CIC Filters: Decimator, Generic CIC Filters: Decimator,
Interpolator.Interpolator.• Interfaces: SW-HW intfc, Filters Intfc.Interfaces: SW-HW intfc, Filters Intfc.
Using “user core reference design” to Using “user core reference design” to instantiate the IPIF and attach it to the logic.
FIFO - generated core from CoreGen. Simulation – Using Modelsim.
SoftwareSoftwareFlow ChartFlow Chart
Receive Params from PC
Send Params to
Core
Send START to
Core
Wait for FINISH from Core
Send Data from Core
to PC
Wait for Input file from PC
SoftwareSoftwareCodeCode
Code written in C :Code written in C :• Check_leds function : counting using LEDs.Check_leds function : counting using LEDs.• Check_sdram function : Memory read/write.Check_sdram function : Memory read/write.• CIC function: previous flow chart in a while CIC function: previous flow chart in a while
loop.loop. Frequently used commands:
• XUartLite_RecvByte(uart_base_addr);• XIo_Out32(cic_base_addr, control_reg);• XIo_In32(cic_base_addr+20);
VerificationVerification
Simulation of the CIC Algorithm in Simulation of the CIC Algorithm in MATLAB:MATLAB:• data_out = dec_param(data_in, N ,R ,M)data_out = dec_param(data_in, N ,R ,M)• data_out = int_param(data_in, N ,R ,M)data_out = int_param(data_in, N ,R ,M)
The system’s output was compared to The system’s output was compared to the MATLAB’s output using various the MATLAB’s output using various inputs and parameters.inputs and parameters.
MATLAB GUI.MATLAB GUI.
GUIGUI
Filter Param
s
Files
Results
GUI GUI FeaturesFeatures
Filter Type, N, M, R, chosen by user.Filter Type, N, M, R, chosen by user. Data input file specified by user.Data input file specified by user. HW input filename specified by user.HW input filename specified by user. Creates HW input file to be run by user.Creates HW input file to be run by user. HW output filename specified by user.HW output filename specified by user. Runs SW simulation.Runs SW simulation. Compares and shows results using Compares and shows results using
graph.graph.
Hardware InterfaceHardware Interface
INPUT: INPUT: Receives file via UART using Hyper-Receives file via UART using Hyper-Terminal.Terminal.• The file contains the data in the right format The file contains the data in the right format
for the HW. The file can be created using the for the HW. The file can be created using the GUI.GUI.
OUTPUT:OUTPUT:Sends the results via UART using Hyper-Sends the results via UART using Hyper-Terminal.Terminal.• The results are captured into file.The results are captured into file.
The file can be read using the GUI.The file can be read using the GUI.
Hyper TerminalHyper Terminal
Conclusions and Conclusions and RemarksRemarks..
SoC is a powerful platform for SoC is a powerful platform for integrating Hardware and Software.integrating Hardware and Software.
Still new and therefore encountered Still new and therefore encountered some problems.some problems.
Thank YouThank You