final presentation part-a
DESCRIPTION
Final Presentation Part-A. Infrastructure design & implementation of MIPS processors for students lab based on Bluespec HDL. Students: Danny Hofshi, Shai Shachrur Supervisor: Mony Orbach. Winter 2012. Reminder. FPGA. C++. Bluespec Scemi. Bluespec HDL. - PowerPoint PPT PresentationTRANSCRIPT
Final PresentationPart-A
Infrastructure design & implementation of MIPS processors for students lab based on
Bluespec HDL
Students: Danny Hofshi, Shai ShachrurSupervisor: Mony Orbach
Winter 2012
FPGA
Bluespec Scemi
Bluespec HDL
C++
Reminder
Project Goals (from characteristic presentation)
Part A:
Creating the Laboratory working environment.
1. Hardware environment – RTL , interface to outer world ( pci - express ), Xilinx utilities.
2. Software environment – simulation of a MIPS processor on the above RTL using simplified commands, the same environment will be used for emulation and simulation.
Project Characterization
Multi cycle MIPS hardware
Adjusting the experiment flow
Test, Sync & Conclusions
Designing the MIPS improvements
performance questionsProgram for testing
Running a pilot group
Danny & ShaiLab staff
Part A
Part B
We are here
What has been done
Hardware infrastructure
Hardware
PCIe cable
Virtex 5 FPGA
Linux Environment
What has been done
RTL Design
MIPS Design
Xilinx BRAM
Xilinx BRAM
BlueSpecS C E M I
- PCIe
-Clk control
Communicating with a c++ environment using generic interface
BlueSpec
Co-Process
or
The MIPS state machine
What has been done
Software environment
Control interface Ability to Put & get data from the instruction
memory.Ability to Put & get data from the data
memory.Ability to control the MIPS operation (Co-
processor)- stop- load PC, start & wait for interrupt - load PC & start for a specific number of cycles
Retrieve performances (Co-processor).- Number of clock cycles. - Number of Instructions.
SCEMI
CompilerPerl Script compiler – translate assembler
code to our specific SCEM interface.
addi $t1 $zero 2 addi $t2 $zero 2 add $t3 $t1 $t2sw $t3 $zero 0 stop
604569602 0 0 1 0604635138 4 4 1 01952289 8 8 1 02 8 86402048 12 12 1 0
1082130432 16 16 1 0
0 1 1 1 22 0 0 1 21 0 0 1 2
Processor commands
Stop commandwill generate an interrupt
Load PC Set PCStart
User work FlowWrite Assembler Code & Data memory
Type executable command
Receive performances and data
addi $t1 $zero 2 addi $t2 $zero 2 add $t3 $t1 $t2sw $t3 $zero 0 stop
Compiler604569602 0 0 1 0
604635138 4 4 1 01952289 8 8 1 02 8 86402048 12 12 1 0
1082130432 16 16 1 0
0 1 1 1 22 0 0 1 21 0 0 1 2
Communication module C++ MIPS Data
received
On the PC
Project Characterization
Multi cycle MIPS hardware
Adjusting the experiment flow
Test, Sync & Conclusions
Designing the MIPS improvements
performance questionsProgram for testing
Running a pilot group
Danny & ShaiLab staff
Part A
Part B
We are here
Test programThe Bubble sort Assembler code:// size of arrayaddi $s0 $zero 64 // address counteraddi $s1 $zero 0 // swap indicatorstart : addi $s2 $zero 0 start_in_iteration : lw $t0 $s1 0lw $t1 $s1 4 // $t0=1 if we need to swap, $t0=0 elseslt $t3 $t1 $t0beq $t3 $zero no_swapsw $t0 $s1 4sw $t1 $s1 0// set swap indicatoraddi $s2 $zero 1no_swap : beq $s1 $s0 end_iterationaddi $s1 $s1 4beq $zero $zero start_in_iteration end_iteration : beq $s2 $zero stop_sortaddi $s1 $zero 0addi $s0 $s0 -4beq $s0 $zero stop_sortbeq $zero $zero start
RunThe program Run on the CPU. Typing the command line to compile and run the above code [s03992455@diglabl2 fpga]$ perl parser.pl -source bubble_sort.S -end -meminit mem_init.txtStarting to parse code ********* Running command_file.txt ************ (Writing Data to the I-MEM)Loading data to I-mem: 605028416 0 0 1 0Loading data to I-mem: 605093888 4 4 1 0Loading data to I-mem: 605159424 8 8 1 0Loading data to I-mem: 2384986112 12 12 1 0Loading data to I-mem: 2385051652 16 16 1 0Loading data to I-mem: 19421226 20 20 1 0Loading data to I-mem: 291504131 24 24 1 0Loading data to I-mem: 2921857028 28 28 1 0Loading data to I-mem: 2921922560 32 32 1 0Loading data to I-mem: 605159425 36 36 1 0Loading data to I-mem: 305135618 40 40 1 0Loading data to I-mem: 640745476 44 44 1 0Loading data to I-mem: 268500982 48 48 1 0Loading data to I-mem: 306184196 52 52 1 0Loading data to I-mem: 605093888 56 56 1 0Loading data to I-mem: 638648316 60 60 1 0Loading data to I-mem: 301989889 64 64 1 0Loading data to I-mem: 268500976 68 68 1 0Loading data to I-mem: 1082130432 72 72 1 0Loading to arg register 0 1 1 1 2 (Loading the start value of the MIPS Program counter)Load PC from arg register2 0 0 1 2 (Applying the start value to the PC)Start CPU 1 0 0 1 2 (Starting the run on the MIPS) ####### Program run on CPU finished ####### (Receiving an interrupt from the PC) SceMi Service thread finished!SceMi Service thread finished!
Results ********* inquiring check_mem.txt ************ (Reading the performance counters sort DATA) requesting number of cycles (Sending a data request to the Co-processor)number of clock cycles is 591number of instructions is 122{data 32'h00000011 resp_type 4'h1 resp_addr 32'h00000000}{data 32'h00000014 resp_type 4'h1 resp_addr 32'h00000004}{data 32'h00000015 resp_type 4'h1 resp_addr 32'h00000008}{data 32'h00000037 resp_type 4'h1 resp_addr 32'h0000000c}{data 32'h0000003c resp_type 4'h1 resp_addr 32'h00000010}{data 32'h0000003d resp_type 4'h1 resp_addr 32'h00000014}{data 32'h0000003d resp_type 4'h1 resp_addr 32'h00000018}{data 32'h00000045 resp_type 4'h1 resp_addr 32'h0000001c}{data 32'h00000047 resp_type 4'h1 resp_addr 32'h00000020}{data 32'h0000004a resp_type 4'h1 resp_addr 32'h00000024}{data 32'h0000004d resp_type 4'h1 resp_addr 32'h00000028}{data 32'h00000050 resp_type 4'h1 resp_addr 32'h0000002c}{data 32'h00000053 resp_type 4'h1 resp_addr 32'h00000030}{data 32'h00000058 resp_type 4'h1 resp_addr 32'h00000034}{data 32'h00000059 resp_type 4'h1 resp_addr 32'h00000038}{data 32'h0000005d resp_type 4'h1 resp_addr 32'h0000003c}{data 32'h00000060 resp_type 4'h1 resp_addr 32'h00000040}{data 32'h00000061 resp_type 4'h1 resp_addr 32'h00000044}Finished parsing
591 Cycles
122 Instructions
4.844 Cycles per instruction
RemarksWe can also run in simulation mode for RTL
debug.A full verification on the whole MIPS
command set was made.
DiscussionWe
implement Meow
prediction ?