B.Tech TutorialCAD Algorithm for synthesis of Digital Systems

1) Write a HDL code where inputs are read from text file name as input.txt and their complements values are written in output file as output.txt.(Note: Please generate a file named as input.txt which has total 10 binary values i.e.1,3,5,7,11,13,17,19,21,23 )

2) We define the distance from the Gray code word a to the Gray code word b as the number of transitions from code word a to code word b. For example, consider the 4-bit Gray code words "0101" and "1111" as a and b. The distance from a to b is 4 since four transitions are needed (i.e., "0101" -"0100" - "1100" - "1101" 1111). Design a circuit to calculate the distance of two 4-bit Gray code words and write HDL code.

3) Write a HDL code for the input n (4 bit) Fibonacci series.4) Many instrument panels use binary-coded-decimal (BCD) format, in which 10

decimal digits are coded by using 4 bits. During an addition operation, if the sum of a digit exceeds 9,then 10 will be subtracted from the current digit and a carry is generated for the next digit. Design a 3-digit BCD adder which has two 12-bit inputs, representing two 3-digit BCD numbers, and an output, which is a 4-digit (16-bit) BCD number. Derive the HDL code accordingly.

5) A Manchester decoder transforms a Manchester-coded data stream back to a regular binary data stream. There are two output signals. The data signal is the recovered data bit, which can be '0' or '1'. The valid signal indicates whether a transition occurs. The valid signal is used to distinguish whether the '0' of the d at a signal is due to the O-to-1 transition or inactivity of the data stream. Drive the VHDL code for the logic.

6) Write a HDL Code that takes input of 8 bit serial data and converts it in the parallel data.

7) Design n bit Linear Feedback Shift Register (LFSR). Write HDL code and simulate it.

8) A leading-zero counting circuit counts the number of consecutive 0's from an input signal. We want to design a sequential version of this circuit. The design should check one bit of the input at a time and increment accordingly. The counting stops when the first '1' is encountered. Design HDL code for the same logic.

9) We wish to design an FSM to detect the "10101010" pattern in the receiving end. The circuit has an input signal, data-in, and an output signal, match. The match signal will be asserted as '1' for one clock period when the input pattern "10101010" is detected. (a) Derive the state diagram. (b) Derive HDL code to detect the desired sequence.

10 An arbiter is a circuit that resolves any conflict and coordinates the access to the shared resource. Considers an arbiter with two subsystems, as shown in Figure A. The subsystems communicate with the arbiter by a pair of request and grant signals, which are labeled as r (1) and g(1) for subsystem 1, and as r (0) and g(0) for subsystem 0. When a subsystem needs the resources, it activates the request

Instruction:

1) Use HDL as many utilities as you can used in designing the problems. There will be extra marks for using different HDL utilities.

2) Draw algorithm and explain your design in brief in each problems.3) Explain your code with proper commenting.4) Write a test bench of to verify each RTL.5) Last date to submit the tutorial is 15-09-2014. You should create a zip folder with your roll number as name of file and mail to email -ID: amit_mjoshi@yahoo.co.in

signal. The arbiter monitors use of the resources and the requests, and grants access to a subsystem by activating the corresponding grant signal. Once its grant signal is activated, a subsystem has permission to access the resources. After the task has been completed, the subsystem releases the resources and deactivates the request signal. Since an arbiters decision is based partially on the events that occurred earlier (i.e., previous request and grant status), it needs internal states to record what happened in the past. Design the FSM and write HDL code to meet this requirement.

Figure A. Block Diagram of an arbiter