final - volume 3 no 4

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FUNCTIONAL TESTING OF A MICROPROCESSORTHROUGH LINEAR CHECKING METHOD

Prof. Dr. Pervez AkhtarNational University of Science & Technology,

Karachi Campus, Pakistan

[email protected]

Prof. Dr. M.Altaf Mukati

Hamdard Institute of Information Technology,

Hamdard University, Karachi, Pakistan

[email protected]

ABSTRACTThe gate-level testing also called low-level testing is generally appropriate at the

design time and for small circuits. The chip-level testing and board-level testing

also called high-level testing are preferred when the circuit complexities are too

high, making it difficult to perform low level testing in a reasonable amount oftime. The cost of low-level testing is also generally very high. Such high costs and

time are only justified when some design-changes are required. In this paper, ahigh level quick checking method, known as Linear Checking Method, is

presented which can be used to qualify the functionality of a Microprocessor. This

can also be used to check hard faults in Memory chips.

Keywords: Microprocessors, ALU, Control Unit, Instructions.

1 INTRODUCTIONDue to the advances in the integrated circuit

technology, more and more components are being

fabricated into a tiny chip. Since the number of pinson each chip is limited by the physical size of the

chip, the problem of testing becomes more difficult

than ever. This problem is aggravated by the fact

that, in nearly all cases, integrated circuit

manufacturers do not release the detailed circuit

diagram of the chip to the users [1].

The users are generally more interested to know

about the chip, whether is it functionally working

and relied upon? if not, the whole chip is replaced

with a newer one. This is contrast to the gate-level

testing of a digital circuit, which is used to diagnose

faulty gates in the given circuit, in case of failing.

The idea of using functional testing is also

augmented by the fact that in case of any functionalfailure, caused due to any fault in the chip, the user

can not repair the chip. Hence the users have only

two choices: either to continue using the chip with a

particular failing function, knowing that the failing

function will not be used in the given application or

to replace the whole chip.

The functional modeling is done at a higher level

of abstraction than a gate-level modeling. This in-

fact exists between the Gate-level modeling and the

Behavioral modeling, which is the highest level of

abstraction [2]. The functional fault modeling should

imitate the physical defects that cause change in the

function or behavior, for example; the function of a

synchronous binary up-counter is to advance one

stage higher in binary value when clock hits it. Aphysical defect, which alters this function, can be

modeled in terms of its effect on the function. Such

defect-findings are extremely important at the design

time or if the design changes are required at a later

stage.

What, if a microprocessor does not produce the

correct results of any single or more functions? From

the users perspective, it is enough to know which

function is failing, but from designers perspective,

the cause of failing is also important to know, so that

the design changes may be carried out, if necessary.

This is certainly a time-taking process. For example,

the gate level simulation of the Intel 8085

microprocessor took 400 hours of CPU-time andonly provided 70% fault coverage [3].

High level functional verification for the complex

Systems-On-Chip (SOCs) and microprocessors has

become a key challenge. Functional verification and

Automatic Test Pattern Generator (ATPG) is one

synergetic area that has evolved significantly in

recent years due to the blossoming of a wide array of

test and verification techniques. This area will

continue to be a key focus of future Microprocessor

TEST and Verification (MTV) [4].

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Functional failures can be caused due to single ormultiple stuck-at faults in any of its functional block.

The functional-testing, which refers to the selection

of tests that verify the functional operation of a

device, is one of an efficient method to deal with the

faults existing in a processor. Functional testing can

also be carried out at a smaller level, for example, a

functional test of a flip-flop might be to verifywhether can it be set or reset? and further, can it hold

the state or not? Similarly, the other MSI chips such

as Multiplexers, Encoders, Decoders, Counters,

Hardwired-Multipliers, Binary-Adders & Subtrac-

tors, Comparators, Parity Checkers, Registers and

other similar circuits can also be verified for their

required functionalities.

Some designers and manufacturers provide built-

in self-test (BIST) these days that generate the test on

the chip and responses are checked within the chip

itself. However, the widespread use of such

testability techniques is hampered by a lack of tools

to support the designer and by the additional cost in

chip area as well as the degradation in performance

[5]. For example, the Intel 80386 microprocessor

employs about 1.8% area overhead for BIST to test

portions of the circuit [6].

The ever increasing complexity combined with

the advanced technology used in the design of the

modern microprocessors, has lead to two major

problems in producing cost-effective, high quality

chips:

1. Verification: This is related to validate thecorrectness of the complex design. Simulation

is the primary means of design validation used

today. In the case of processor design

validation, the sequences are either written

manually or generated automatically by arandom sequence generator [7].

2. Testing: This is related to check the

manufactured chips for realistic defects. A

variety of test generation and design-for-

testability (DFT) techniques is used to ensure

that the manufactured chips are defect-free.

Both design verification and testing depend,

therefore, on test sequences used to expose either the

design faults or manufacturing defects. It has also

been found that manufacturing test pattern

generation can be used for design verification [8] and

that design verification techniques can be used to

find better manufacturing tests [9]. However, to findthe effective test patterns for either of the said

purposes is not simple, due to high complexities of

microprocessors. Hence the only effective method

left is to develop the functional tests. Considerable

work has been done in the field of microprocessor

functional testing. One of such work, known as

Linear Checking Method is presented in this paper.

Before performing functional testing, functional

description of the chip must be known. In case of

microprocessor, this can be obtained through its

instruction set. The two most important functional

blocks of any microprocessor are the CU (Control

Unit) and the ALU (Arithmetic Logic Unit). All the

instructions, at low-level, are composed of Op-Codes

and operands. An op-code, also called the Macro-

instruction, goes to the CU, which decodes eachmacro-instruction into a unique set of micro-

instructions. The operands go to the ALU, which

processes it according the tasks defined within the

micro-instructions. In between these functional

blocks, there exists several registers for the

temporary storage of op-codes, decoded-instructions

and operands.

The fault may occur at various places in the

processors, causing it to function incorrectly. Some

of the common faults are: Register Decoding Fault,

Micro-Operation Decoding Fault (caused may be due

to internal defect to the CU), Data Storage Fault

(caused may be due to Stuck-at Fault or Pattern

Sensitive Fault in the memory inside the

Microprocessor), Data Transfer Fault (caused may be

due to Stuck-at Fault or Bridging Fault on the busses

connecting the various functional blocks of a

Microprocessor) or ALU Fault (caused due to

internal defect to the ALU). In each case, the given

microprocessor results in producing incorrect

function/ functions.

In the subsequent sections, first the functional

verification has been described in general and then

the Linear Checking Method has been presented

through several examples. Based on the results

obtained, the conclusion has been drawn and the

further work has been proposed.

2 FUNCTIONAL VERIFICATIONThe micro-instructions from the CU and the

operands of an instruction are sent to the ALU

simultaneously. The ALU then carries out the

intended task or function. This can be shown with

the help of a block diagram, as in Fig. 1.

Figure 1: Functional testing

The typical instructions are ADD, SUB, MUL,



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SHL, SHR, ROTL, ROTR, INC, DEC, COMPL,AND, OR, XOR and many others.

3 LINEAR CHECKING METHODThis method can be used to test and verify, not

only the functionality of a microprocessor (more

specifically ALU), but the memories as well. Linearchecking is based on computing the value of K

using the equation 3.1:

i i i iK = f (x, y) + f (x, y) + f (x, y) + f (x, y) (1)

Equation 1 is called the basic equation. The

variables x and y are the operands, i is theinstruction. The value of K does not depend on the

values of x and y, but only depends on the instruction

and on the size of operands (number of bits in theoperands). It means the value of K is unique for

every instruction. The chances are very little that the

two instructions may have the same constant value of

K. An 8 and 16-bit ALUs have different values of K,

for the same instruction. Hence, in this method, K isused as a reference value to verify the functionality

of an individual instruction.

3.1 Examples of functional verifications

Consider a 4-bit ALU. The value of K can be

computed as follows:

Suppose the instruction is ADD(x, y) = x + y

Here, n = 4. Let x = 5 (0101) and y = 3 (0011)

Therefore x = 1010 and y = 1100

The value of K can be obtained from Equation 1,as follows:

ADD(5,3)+ADD(5,12)+ADD(10,3)+

ADD(10,12) = K

8 + 17 + 13 + 22 = 60

Hence, for a 4-bit ALU, the ADD instruction

will always be tested with respect to its reference

value of 60, regardless what values of x and y are

taken, i.e. instead of 5 and 3 as in the above example,

now these values are taken as 9 and 10 respectively.Still the value of K remains the same, as proved

below:

i.e. for x = 9 (1001) and y = 10 (1010)

x = 6 (0110) and y = 5 (0101)

ADD(9,10)+ADD(9,5)+ADD(10,6)+ADD(6,5)=

60

The generalized formula can also be developed to

find the value of K for the ADD instruction, for any

size of ALU, as follows:

K+(n) = 4(2n

1)

Where, the subscript with K represents the

function. Hence from the generalized form, we

obtain the same value of K i.e. if n = 4, then K+(4) =4(15) = 60.

Similarly, the value of K for any instruction can

be obtained, provided its functional description isknown. The value of K, for the various other

frequently used instructions, can be obtained

similarly, as follows:Again assume a 4-bit ALU. Taking x = 10 and y

= 12 then x = 5 and y = 3 in all the computations.

3.1.1 Multiply instruction (f(x,y) = X * Y)fi(x,y) = MPY(x,y) = X * Y

Hence, from equation 3.1, the value of K can be

obtained as follows:

MPY(12,10)+MPY(10,3)+MPY(5,12)+MPY(5,3)

120 + 30 + 60 + 15 = 225

Generalized form K* = (2n

1)2

3.1.2 Transfer instruction (f(x) = x)This is a single valued function, hence only one

variable is taken in computation of K, thus y is

ignored in equation 1.

Thusi

f (x) = x

= x + x + x + x = 10 + 10 + 5 + 5 = 30

Generalized form K = 2(2n

1)

3.1.3 Shift-Right instruction (f(x) = SHR(x))It is also a single valued function. With x = 1010:

(a)i

f (x, y) &i

f (x,y ) reduce toi

f (x) and

(b)i

f (x, y) &i

f (x, y) reduce toi

f (x)

Nowi

f (x) represents the value of x, after SHR

operation i.e. 1010 0101 andi

f (x) represents the

value of x after SHR operation i.e. 0101 0010.

Hence, K = 0101 + 0101 + 0010 + 0010

or K = 5 + 5 + 2 + 2 = 14

Generalized form K = 2(2n-1

1)

3.1.4 Shift-Left instruction (f(x) = SHL(x))With the same explanation as in section 3.1.3,

the equation 1 becomes:

i i i iK = f (x) + f (x) + f (x) + f (x)



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Hence, with x = 1010i

f (x) = 0100 &

x = 0101i

f (x) = 1010

Therefore, K = 4 + 4 + 10 + 10 = 28

Generalized form K = 2(2n 2)

3.1.5 Logical-OR instruction (f(x) = xORy)

i i i iK = f (x, y) + f (x, y) + f (x, y) + f (x, y)

= (xORy)+(xOR y )+( x ORy)+( x OR y )

= 1110 + 1011 + 1101 + 0111

=14 + 11 + 13 + 7 = 45


3.1.6 Logical-AND instruction (f(x) = xANDy)


= (xANDy)+(xAND y )+( x ANDy)+

( x AND y )

= 1000 + 0010 + 0100 + 0001

= 8 + 2 + 4 + 1 = 15

Generalized form K = 2n 1

3.1.7 Logical-XOR instruction (f(x) = xXORy)


=(xXORy)+(xXOR y )+( x XORy)+

( x XOR y )

= 0110 + 1001 + 1001 + 0110

= 6 + 9 + 9 + 6 = 30


3.1.8 Increment instruction (f(x) = INC(x))This is also a single valued function:

i i i iK = f (x) + f (x) + f (x) + f (x)

= 1011 + 1011 + 0110 + 0110

= 11 + 11 + 6 + 6 = 34


+ 1)

3.1.9 Decrement instruction (f(x) = DEC(x))

i i i iK = f (x) + f (x) + f (x) + f (x)

= 1001 + 1001 + 0100 + 0100

= 9 + 9 + 4 + 4 = 26


- 3)

3.1.10 Complement instruction (f(x) x )

i i i iK = f (x) + f (x) + f (x) + f (x)

= 0101 + 0101 + 1010 + 1010 = 30

Generalized form K = 2(2n - 1)

3.1.11 2s comp. instruction (f(x)

x + 1)i i i i

K = f (x) + f (x) + f (x) + f (x)

= 0110 + 0110 + 1011 + 1011 = 34

Generalized form K = 2(2n + 1)

3.2 Memory error correctionLinear checks can also be used to verify

memories. For example, let the multiplication x*y

function is stored in the memory. Let the operands

are 4-bit length, with x = 1010 and y = 0010, it

means x = 0101 and y = 1101. Hence, all the four

components of equation 1 are computed and the

results are stored in memory, as shown in Table 1.

Table 1: linear checks on memories

f(x,y) 20 00010100

f(x, y ) 130 10000010

f(x ,y) 10 00001010

f( x , y ) 65 01000001

K 225 11100001

If the sum of four components is not equal to the

value of K, then there must be some fault existing in

the memory. Similarly, any of the precedingfunctions can be used to verify the memories. The

testing can be done more accurately if the contents of

f(x,y) are stored at address (x,y). In the above

example, the contents can be stored on the

corresponding addresses as shown in Table 2. If

addition of the contents does not come equal to the

value of K, then it will indicate some fault in the

memory. Here, the location of fault is also obtained.

Table 2: address versus contents in memory testing

Address

x yContents

1010 0010 00010100

1010 1101 10000010

0101 0010 00001010

0101 1101 11100001



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4 RESULTSAll the computations done in the previous section

are summarized in tables 3 & 4 for n = 4 & 8

respectively:

Table 3: Values tabulated through linear checkingmethod for n = 4

Instruction i if (x, y)

iK (n)

iK (4)

Clear 0 0 0

Transfer x 2(2n

1) 30

Add x + y 4(2n 1) 60

Multiply x y (2n 1)2 225

Subtract x y 0 0

Logical OR x y 3(2n

1) 45

Logical

ANDx y 2

n 1 15

Logical

XORx y 2(2

n 1) 30

Complement x 2(2n

- 1) 30

2s comp. x + 1 2(2n

+ 1) 34

Increment x + 1 2(2n

+ 1) 34

Decrement x 1 2(2n - 3) 26

Shift-Left (x2,x3,...xn,0) 2(2n

2) 28

Shift-Right (0,x2,x3,...xn-1) 2(2n-1

1) 14

Rotate-Left (x2,x3,...xn,x1) 2(2n

- 1) 30

Rotate-Right (xn,x2,...xn-1) 2(2n - 1) 30

Table 4: Values tabulated through linear checking

method for n = 8

Instruction i if (x, y)

iK (n)

iK (8)

Clear 0 0 0

Transfer x 2(2n

1) 510

Add x + y 4(2n 1) 1020

Multiply x y (2n 1)2 65025

Subtract x y 0 0

Logical OR x y

3(2n

1) 765

Logical

ANDx y 2

n 1 255

Logical

XORx y 2(2

n 1) 510

Complement x 2(2n

- 1) 510

2s comp. x + 1 2(2n

+ 1) 514

Increment x + 1 2(2n

+ 1) 514

Decrement x 1 2(2n

- 3) 506

Shift-Left (x2,x3,...xn,0) 2(2n

2) 508

Shift-Right (0,x2,x3,...xn-1) 2(2n-1

1) 254

Rotate-Left (x2,x3,...xn,x1) 2(2n

- 1) 510

Rotate-Right (xn,x2,...xn-1) 2(2n

- 1) 510

5 CONCLUSIONIt is concluded that the value of K can be

obtained for any given instruction. The CLR (clear)instruction is a special one, since it does not have any

operand; all the four components of the equation 3.1

are taken as 0. Note that almost all the values

obtained for K are unique, except for Transfer,Complement, Logical XOR and Rotate-

Left/Right instructions, which means if the

instructions are transformed due to any fault in theCU (or in any associated circuit) then these particular

functional failures cannot be distinguished but the

processor as a whole can be declared to have

contained a fault. The last column in tables 3 & 4 canbe obtained directly from the generalized forms. This

column is stored in the memory along with the

relevant function.

6 FUTURE WORKFurther research is proposed on the given method,

especially in the case when the Reference Value(K) of two or more functions is obtained same i.e. to

distinguish or identify an individual failing function,

in case when their reference values happen to be thesame, as mentioned under the conclusion.



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7 REFERENCES[1] Su Stephen Y.H., Lin Tony S., Shen Li:

Functional Testing of LSI/VLSI Digital

Systems, Defense Technical Information Center,Final Technical Report, School of Engineering

Applied Science and Technology Binghampton,

NY, August 1984

[2] Altaf Mukati: Fault Diagnosis and Testing ofDigital Circuits with an Introduction to Error

Control Coding, Pub. Higher EducationCommission Pakistan, ISBN: 969-417-095-8,

2006

[3] Jian Shen, Abraham J.A.: Native mode

functional test generation for processors withapplications to self test and design validation,

Test Conference (1998), Proc. International

Volume, Issue, 18-23 Oct 1998 pp. 990 999.

[4] Magdy S.Abadir, Li-C. Wang, Jayanta Bhadra:

Microprocessor Test and Verification (MTV

2006), Common Challenges and Solutions,Seventh International Workshop, Austin, Texas,

USA. IEEE Computer Society 4-5 December

2006, ISBN: 978-0-7695-2839-7

[5] Jian Shen, Jacob A. Abraham: Native Mode

Functional Test Generation for Processors with

Applications to Self Test and Design Validation,

Proc. Computer Engineering Research Center,The University of Texas at Austin, 1998.

[6] P. P. Gelsinger: Design and Test of the 80386,IEEE Design and Test of Computers, Vol. 4, pp.

42-50, June 1987.

[7] C. Montemayor et al: Multiprocessor DesignVerification for the PowerPC 620

Microprocessor, Proc. Intl. Conf. on Computer

Design, pp. 188-195, 1995.

[8] M. S. Abadir, J. Ferguson, and T. Kirkland:Logic design verification via test generation,

IEEE Trans. on Computer-Aided Design of

Integrated Circuits and Systems, Vol. 7, pp. 138-148, 1988.

[9] D. Moundanos, J. A. Abraham, and Y. V.

Hoskote: A Unified Framework for DesignValidation and Manufacturing Test, Proc. Intl.

Test Conf., pp. 875-884, 1996.



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OPERATING SYSTEMS FOR

WIRELESS SENSOR NETWORKS: AN OVERVIEW

Daniele De Caneva, Pier Luca Montessoro and Davide Pierattoni

DIEGMUniversity of Udine, Italy{daniele.decaneva; montessoro; pierattoni}@uniud.it

ABSTRACT

The technological trend in the recent years has led to the emergence of complete

systems on a single chip with integrated low power communication and transducer

capabilities. This has opened the way for wireless sensor networks: a paradigm of

hundreds or even thousands of tiny, smart sensors with transducer and

communication capabilities. Manage such a complex network that has to work

unattended for months or years, being aware of the limited power resouces of

battery-supplied nodes is a challenging task. Attending that task requires an

adequate software platform, in other words an operating system specifically suitedfor wireless sensor networks. This paper presents a brief overview of the most

known operating systems, highlighting the key challenges that have driven their

design.

Keywords: wireless sensor networks, operating systems.

1 INTRODUCTIONThanks to the well known Moores Law

integrated circuits are becoming smaller, cheaper

and less power consuming. This trend has led to the

emergence of complete systems on a chip withintegrated low power communication and

transducer capabilities. The consequence is the

opening of the ubiquitous computing era, in which

electronic systems will be all around us, providing

all kind of information services to users in a

distributed, omnipresent but nearly invisible fashion.

One of the most important applications that new

technologies are enabling is the paradigm of

Wireless Sensor Networks (WSNs), wherehundreds or even thousands of tiny sensors with

communication capabilities will organize

themselves to collect important environmental data

or monitor areas for security purposes.The hardware for WSNs is ready and many

applications have become a reality, nevertheless the

missing of a commonly accepted system

architecture and methodology constitute a curb to

the expansion and the improvement of such

technologies. Aware of that, many research groups

in the world have proposed their own systemarchitecture. The key point in all these proposals is

the capability of the software to manage a

considerable number of sensors. In particular, there

is a tradeoff between the responsiveness of the

system and the extremely scarce resources of the

nodes in terms of power supply, memory andcomputational capabilities.

In this article will be presented an overview of

the most known operating systems designed for

WSNs. Without proposing direct comparisons, we

describe the key features of these architectures, thechallenges that led their development, with the aim

of helping the reader to choose among these

systems the one that best suites his/her purposes.

2 OVERVIEW2.1 TinyOS

TinyOS [1] is virtually the state-of-the-art of

sensor operating systems. Berkeley University

researchers based their work aiming to face two

issues: the first was to manage the concurrencyintensive nature of nodes which need to keep in

movement different flows of data simultaneously,

while the second was to develop a system with

efficient modularity but believing that hardware andsoftware components must snap together with littleprocessing and storage overhead. The purpose of

the researchers was also to develop a system that

would easily scale with the current technology

trends, supporting smaller devices as well as the

crossover of software components into hardware.

Considering power as the most preciousresource and trying to achieve high levels of

concurrency, the system was designed following an

event-based approach, which avoids reserving a

stack space for each execution context. This design

guideline was drawn from a parallelism with high

performance computing, where event-basedprogramming is the key to achieve high

performance in concurrency intensive applications.



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In TinyOS neither blocking nor polling operation is

permitted and the CPU doesnt waste time in

actively looking for interesting events; on the

contrary, unused CPU cycles are spent in a sleep

state.

System configuration can be summarized in a

tiny scheduler and a set of components. Thescheduler is a simple FIFO utilizing a bounded size

scheduling data structure for efficiency, nonetheless

a more sophisticated scheduling policy could be

implemented. When the task queue is empty, the

CPU is forced to the sleep state waiting for an

hardware event to trigger the scheduling of the

event-associated tasks. Tasks in the TinyOSarchitecture are atomic and run to completion

although they can be preempted by events. This

semantics of tasks allows the allocation of a single

stack, which is an important feature in memory

constrained systems.

Three types of components were thought toconstitute the TinyOS architecture. The first type of

components are the hardware abstraction which

map physical hardware like I/O devices into

component models. The second type of components

is called synthetic hardware and simulates the

behavior of advanced hardware; often synthetic

hardware sits on top of the hardware abstraction

components. The last type of components are the

high level software components, which perform

control, routing and all data transformations such as

data aggregation and manipulation. This kind ofabstraction of hardware and software in the

component model is intended to ease theexploitation of tradeoffs between the scale of

integration, the power requirements and the cost of

the system. Every component owns a fixed-size

frame that is statically allocated: this allows toknow exactly the memory requirements of a

component at compile time and prevents the

overhead associated with dynamic allocation.

TinyOS was originally developed in C, giving

the system the capability of targeting multiple CPU

architectures. However, the system was afterwards

re-implemented in nesC: this is a programming

language specific for networked embedded systems,

whose key focus is holistic approach in design.Its remarkable that for TinyOS a byte-code

interpreter has been developed that makes thesystem accessible to non-expert programmers and

enables quick and efficient programming of a

whole WSN. This interpreter, called Mat, depicts

the programs code as made of capsules. Thanks to

the beaconless, ad-hoc routing protocol

implemented in Mat, when a sensor node receivesa newer version of a capsule, it will install it.

Through a hop-by-hop code injection, Mat can

update the code of the entire network.

2.2 MANTISThe MultimodAl system for NeTworks of In-

situ wireless Sensors [3] was developed focusing on

two design key: the need for a small learning curve

for users and the need for flexibility. The first

objective led to fundamental choices in thearchitecture of the system and the programming

language used for its implementation. In fact, to

lower the entry barrier the researchers decided to

adopt a largely diffuse design methodology, that is,

the classical structure of a multithreaded operating

system. For this reason MANTIS includes features

like multithreading, preemptive scheduling withtime slices, I/O synchronization via mutual

exclusion, and standard network stack and device

drivers. The second choice is associated with the

purpose of flattening the learning curve for users

and determinates the use of standard C as

developing language for the kernel and the API.The choice of C language additionally entails the

cross-platform support and the reuse of a vast

legacy code base.

MANTIS kernel resembles UNIX-style

schedulers providing services for a subset of

POSIX threads along with priority based scheduling.

The thread table is allocated statically, so it can be

adjusted only at compile time. The scheduler

receives notes to trigger context switches from an

hardware timer interrupt. This interrupt is the only

kind of hardware interrupt handled by the kernel: infact all the others interrupts are sent directly to

device drivers. Context switches are triggered notonly by timer events but also by system calls or

semaphore operations. Besides drivers and user

threads, MANTIS has a special idle, low-priority

thread created by the kernel at startup. This threadcould be used to implement power-aware

scheduling: thanks to its position, it can detect

patterns of CPU utilization and adjust kernel

parameters to conserve energy.

MANTIS researchers thought that wireless

networking management was a critical matter, so

they developed the layered network stack as a set of

user level threads. In other words, they

implemented different layers in different threadsadvocating that this choice promotes flexibility to

the detriment of performance. This flexiblestructure is useful in particular for dynamic

reprogramming, because it enables application

developers to reprogram network functionalities

such as routing by simply starting, stopping and

deleting user-level threads.

Drawing from the experience in WSNs, thedevelopers of MANTIS gave their system a set of

sophisticated features like dynamic reprogramming

of sensors nodes via wireless communication,

remote debugging and multimodal prototyping.

MANTIS prototyping environment provides aframework for testing devices and applications



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across heterogeneous platforms. It extends beyond

simulation permitting the coexistence of both

virtual and physical nodes in the same network.

This feature is derived directly by the system code

architecture, which can run without modifications

on virtual nodes within an x86 architecture.

Dynamic reprogramming in MANTIS isimplemented as a system call library, which is built

into the kernel. There are different granularities of

reprogramming: entire kernel reflashing,

reprogramming of a single thread, changing of

variables within the thread. Along with dynamic

reprogramming, an important feature has been also

developed: the Remote Shell and Command Serverwhich allows the user logging in into a node and

taking control of it. The server is implemented as an

application thread and gives the user the ability to

alter nodes configuration, run or kill programs,

inspect and modify the inner state of the node.

2.3 ContikiContiki is an operating system based on a

lightweight event-driven kernel. It was developed

drawing from previous operating systems works

with the goal of adding features like run-time

loading and linking of libraries, programs and

device drivers, as well as support for preemptive

multithreading.

Event-based systems have shown goodperformance for many kind of WSNs applications;

however, purely event-based systems have thepenalty of being unable to respond to external

events during long-lasting computations. A partial

solution to this problem is adding multithreading

support to the system, but this would causeadditional overhead. To address these problems

Contiki researchers have done the compromise of

developing an event-driven kernel and

implementing preemptive multithreading features

as a library, which is optionally linked with

programs that explicitly require it.

Contiki operating system can be divided in three

main components: an event driven kernel that

provides basic CPU multiplexing and has noplatform-specific code, a program loader and

finally a set of libraries that provide higher levelfunctionalities.

From a structural point of view, a system

running Contiki can be partitioned in two parts: a

core and a set of loadable programs. The core is

compiled into a single binary image and is

unmodifiable after nodes deployment. Theprograms are loaded into the system by the program

loader, which may obtain the binaries either from

the communication stack (and thus from the

network) or from the systems EEPROM memory.

Shared libraries like user programs may bereplaced in deployed systems by using the dynamic

linking. Dynamic linking is based on synchronous

events: a library function is invoked by issuing an

event generated by the caller program. The event

broadcasts the request to all the libraries and a

rendezvous protocol is used to find out the library

that implements the required function. When the

correct library has completed the call, the controlreturns back to the calling process. Since dynamic

linking bases its functioning on synchronous events,

it is essential that context switching overhead is as

small as possible, in order to have a good system

performance. Contiki developers have granted this

by implementing processes as event handlers,

which run without separate protection domains.The flexible mechanism of dynamic linking

allowed Contiki researchers to implement

multithreading as a library optionally linked with

programs. Another important component based on a

shared library is the communication stack.

Implementing the communication stack as a libraryallows its dynamic replacement and, more precisely,

if the stack is split into different libraries it

becomes easy to replace a communication layer on

the run.

2.4 PicOSPicOS is an operating system written in C and

specifically aimed for microcontrollers with limited

RAM on chip. In the attempt to ease theimplementation of applications with constrained

resource hardware platforms, PicOS creators leanedtowards a programming environment, which is a

collection of functions for organizing multiple

activities of reactive applications. This

environment is capable to provide services like aflavor of multitasking and tools for inter-process

communication.

Each process is thought as a FSM that changes

its state according to the events. This approach is

very effective for reactive applications, whose

primary role is to respond to events rather than

processing data or crunching numbers. The CPU

multiplexing happens only at state boundaries: in

other words FSM states can be viewed ascheckpoints, at which PicOS processes can be

preempted. Owing the fact that processes arepreemptible at clearly defined points, potentially

problematic operations on counters and flags are

always atomic. On the other hand, such non-

preemptible character of PicOS processes makes

this system not well suitable for real time

applications. In PicOS active processes that need towait for some events may release the CPU by

issuing a wait request, which defines the

conditions necessary to their recovery. This way the

CPU resources could be destined to other processes.

The PicOS system is also equipped with severaladvanced features, like a memory allocator capable



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of organizing the heap area into a number of

different disjoint pools, and a set of configurable

device drivers including serial ports, LCD displays

and Ethernet interfaces.

2.5 MagnetOSApplications often need to adapt not only to

external changes but also to the internal changes

initiated by the applications themselves. An

example may come from a battlefront application

that may modify its behavior switching from the

defensive to the offensive mode: this applicationcould change its communication pattern and

reorganize the deployed components. Focusing on

this point, researchers at the Cornell University

argued that network-wide energy management is

best provided by a distributed, power-aware

operating system. Those researchers developedMagnetOS aiming to the following four goals. The

first was the adaptability to resources and network

changes. The second was to follow efficient

policies in terms of power consumption. The third

goal was giving the OS general-purpose

characteristics, allowing it to execute applications

over networks of nodes with heterogeneous

capabilities and handling different hardware and

software choices. The fourth goal was providing the

system with facilities for deploying, managing and

modifying executing applications.The result was a system providing a SSI,

namely a Single System Image. In this abstraction,the entire network is presented to applications as a

single unified Java virtual machine. The system,

which follows the Distributed Virtual Machine

paradigm, may be partitioned in a static and in adynamic component. The static component rewrites

regular Java applications into objects that can be

distributed across the network. The dynamic

component provides on each node services for

application monitoring and for object creation,

invocation and migration. In order to achieve good

performance an auxiliary interface is provided by

the MagnetOS runtime that overrides the automatic

object placement decisions and allowsprogrammers to explicitly direct object placement.

MagnetOS uses two online power-awarealgorithms to reduce application energy

consumption and to increase system survival by

moving application components within the entire

network. In practice, these protocols try to move he

communication endpoints in order to conserve

energy. The first of them, called NetPull, works atthe physical layer whereas the second one, called

NetCenter, works at the network layer.

2.6 EYESThis operating system was developed within the

EYES European project and tries to address the

problems of scarce resources in terms of both the

memory and power supply and the need for

distribution and reconfiguration capabilities.

The researchers found solution to these

problems developing a event-driven system. In fact,

EYES OS is structured in modules that are executedas responses to external events, leaving the system

in a power saving mode when there is no external

event to serve. Every module can ask for several

tasks to be performed; each task in turn defines a

certain block of code that runs to completion. In

this paradigm, no blocking operation is permitted

and no polling operation should be instantiated: theprogrammer instead will use interrupts to wake up

the system when the needed input becomes

available.

The system provides a scheduler which can be

implemented as a simple FIFO or a more

sophisticated algorithm. The interrupts are also seenas tasks scheduled and ready to be executed.

In the EYES architecture there are two system

layers of abstraction. The first layer is the Sensor

and Networking Layer, which provides an API for

the sensor nodes and the network protocols. The

second layer is the Distributed Services Layer,

which exposes an API for mobile sensor

applications support. In particular, two services

belong to this layer: the Lookup Service and the

Information Service. The first supports mobility,

instantiation and reconfiguration, while the latterdeals with aspects of collecting data. On top of

cited layers stand the user applications.The EYES OS provides a four-step procedure

for code distribution, designed to update the code

into nodes, including the operating system. This

procedure is resilient to packet losses during theupdate, using as few communication and local

resources as possible and halting the node

operations only for a short period.

3 CONCLUSIONSThe operating systems here described present

different approaches to the common problems ofWSNs. It is not in the aim of this article to express

opinions about the presented systems; nevertheless,some general guidelines could be drawn from the

work experience made by all the esteemed

researchers.

We present now some guidelines for the

development of the next generation of WSN

operating systems, that should help both researchersand users.

The constrained nature of resources in

embedded systems is definitely evident, so a

small, efficient code is a primary goal, as wellas power-aware policies are an obligatory



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Table 1: summary of WSN OS features.

TinyOS Mantis

Objectives Manage concurrent data flows

Scale easily with technologyModularity

Small learning curve

Structure Event-based approach

Tiny scheduler and a set of components

No blocking or pollingDeveloped in nesC

Multithreaded OS,

UNIX-style scheduler

Statically-allocated thread tableDeveloped in C

Special

features

A byte code interpreter for non-expert

programmers

Specific idle task that adjusts kernel

parameters to conserve energy

Remote debugging and reprogramming

Contiki PicOS

Objectives Preemptive multithreading support

Runtime loading and linking of libraries

Aimed for microcontrollers with tiny RAM

Structure Lightweight event-driven kernel

Multithreading features as an optionally

linked library

Each process thought as a FSM

Multiplexing at state boundaries

Written in C

Special

features

Capable of changing communication layer on

the run

Memory allocator

A set of configurable device drivers

MagnetOS EYES

Objectives Adaptability to resource and network changes

Manage nodes with heterogeneous

capabilities

Address problems of scarce memory and

power supply

Structure Single System Image, the entire network is a

unified Java virtual machine

Event driven OS

Structured in modules executed as responses

to external events

Each task runs to completion

Special

features

Two on-line special algorithms to reduce

energy consumption

Two layers of abstraction with specific API

for applications and physical support

Four-step procedure to update the code

Table 2: the seven expected features of the next generation WSN operating systems.

Power-aware policies

Self organization

Easy interface to expose data

Simple way to program, update and debug

network applications

Power-aware communication protocols

Portability

Easy programming language for non-techusers



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condition to exploit the efficiency in WSN

applications.

To ensure a proper functioning of a network,

which is constituted by unattended nodes that

could have been deployed in a harsh

environment, the operating system must providea mechanism for self-organization andreorganization in case of node failures.

A WSN, especially if composed of a huge

number of nodes, must behave as a distributed

system, exposing an interface where data and

processes are accessible and manageable like it

happens with databases.

A large number of nodes carries also the need

for an easy, yet power efficient way to program

the network, which should be also usable after

the deployment and without affecting normal

functioning. Such a programming (and re-

programming) procedure must be robust tointerference and to all other causes of

transmission failures during the dissemination

of code chunks. While the entire re-

programming of the core of the system may not

be necessary, the applications must be patched,updated or even totally changed if the main

purpose of the WSN is changed. This leads to

the preference, if possible, of different levels of

re-programming granularity.

The operating system must treat wireless

communication interfaces as special resources,providing a set of different power aware

communication protocols. The system has tochoose the proper protocol, according to the

current environment state and application needs.

The operating system should be portable todifferent platforms: this is necessary both for the

possible presence of nodes with different tasks

and for the opportunity of a post-deployment of

newer sensors, which could be placed in order

to reintegrate the network node set.

The operating system should provide aplatform for fast prototyping, testing and

debugging application programs. In this context

it is remarkable to note that, if the WSN

paradigm will spread in a kaleidoscopic set of

applications, touching many aspects of our life,

then program developers will not be just

communication and computer engineers. It

appears clear that, in order to support non-

technical developers, a really simple API or

even an application-typology programming

language must be provided, alongside with thenormal and more efficient API. Making WSN

easy to use will make them more attractive and

step up their diffusion.

4 REFERENCES[1]J. Hill, R. Szewczyk, A. Woo, S. Hollar, D.

Culler, K. Pister: System Architecture

Directions for Networked Sensors, ASPLOS.

(2000).

[2]K. Sohraby, D. Minoli, T. Znati: WirelessSensor Networks: technology, Protocols and

Applications, John Wiley & Sons Inc. (2007).[3]H. Abrach, S. Bhatti, J. Carlson, H. Dai J. Rose,

A. sheth, B. Sheth, B. Shucker, J. Deng, R. Han:

MANTIS: System Support for MultimodAl

NeTworks of In-situ Sensors, Proceedings of the

2nd ACM International Conference on Wireless

Sensor Networks and Applications. (2003).

[4]A. Dunkels, B. Grnvall, T. Voigt, J. Alonso:The Design for a Lightweight Portable

Operating System for Tiny Networked Sensor

Devices, SICS Technical Report (2004).

[5]E. Akhmetshina, P. Gburzynski, F. Vizecoumar:PicOS: A Tiny Operation System for Extremely

Small Embedded Platforms, Proceedings of theConference on Embedded System and

Applications ESA02 (2002).

[6]R. Barr, J. Bicket, D. S. Dantas, B. Du, T.W.D.Kim, B. Zhou, E. Sirer: On the need for system-

level support for ad hoc and sensor networks,

SIGOPS Oper. Syst. Rev. (2002).

[7]S. Dulman, P. Havinga: Operating SystemFundamentals for the EYES Distributed Sensor

Network, Proceedings of Progress02 (2002).



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Performance Evaluation of Deadline Monotonic Policy

over 802.11 protocol

Ines El Korbi and Leila Azouz SaidaneNational School of Computer Science

University of Manouba, 2010 Tunisia

Emails: [email protected] [email protected]

ABSTRACT

Real time applications are characterized by their delay bounds. To satisfy the

Quality of Service (QoS) requirements of such flows over wireless

communications, we enhance the 802.11 protocol to support the Deadline

Monotonic (DM) scheduling policy. Then, we propose to evaluate the performance

of DM in terms of throughput, average medium access delay and medium accessdelay distrbution. To evaluate the performance of the DM policy, we develop a

Markov chain based analytical model and derive expressions of the throughput, the

average MAC layer service time and the service time distribution. Therefore, we

validate the mathematical model and extend analytial results to a multi-hopnetwork by simulation using the ns-2 network simulator.

Keywords: Deadline Monotonic, 802.11, Performance evaluation, Average

medium access delay, Throughput, Probabilistic medium access delay bounds.

1 INTRODUCTION

Supporting applications with QoS requirements

has become an important challenge for all

communications networks. In wireless LANs, the

IEEE 802.11 protocol [5] has been enhanced and the

IEEE 802.11e protocol [6] was proposed to supportquality of service over wireless communications.

In the absence of a coordination point, the IEEE

802.11 defines the Distributed Coordination

Function (DCF) based on the Carrier Sense Multiple

Access with Collision Avoidance (CSMA/CA)

protocol. The IEEE 802.11e proposes the Enhanced

Distributed Channel Access (EDCA) as an extension

for DCF. With EDCA, each station maintains four

priorities called Access Categories (ACs). The

quality of service offered to each flow depends on

the AC to which it belongs.

Nevertheless, the granularity of service offered

by 802.11e (4 priorities at most) can not satisfy the

real time flows requirements (where each flow ischaracterized by its own delay bound).

Therefore, we propose in this paper a new

medium access mechanism based on the Deadline

Monotonic (DM) policy [9] to schedule real time

flows over 802.11. Indeed DM is a real time

scheduling policy that assigns static priorities to flow

packets according to their deadlines; the packet with

the shortest deadline being assigned the highest

priority. To support the DM policy over 802.11, we

use a distributed scheduling and introduce a new

medium access backoff policy. Therefore, we focus

on performance evaluation of the DM policy in terms

of achievable throughput, average MAC layer

service time and MAC layer service time

distribution. Hence, we follow these steps:

First, we propose a Markov Chainframework modeling the backoff process of

n contending stations within the same

broadcast region [1].

Due to the complexity of the mathematical

model, we restrict the analysis to n

contending stations belonging to two traffic

categories (each traffic category is

characterized by its own delay bound).

From the analytical model, we derive thethroughput achieved by each traffic

category.

Then, we use the generalized Z-transforms[3] to derive expressions of the average

MAC layer service time and the servicetime distribution.

As the analytical model was restricted totwo traffic categories, analytical results are

extended by simulation to different traffic

categories.

Finally, we consider a simple multi-hopscenario to deduce the behavior of the DMpolicy in a multi hop environment.

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The rest of this paper is organized as follows. In

section 2, we review the state of the art of the IEEE

802.11 DCF, QoS support over 802.11 mainly the

IEEE 80.211e EDCA and real time scheduling over

802.11. In section 3, we present the distributed

scheduling and introduce the new medium access

backoff policy to support DM over 802.11. In section

4, we present our mathematical model based on

Markov chain analysis. Section 5 and 6 present

respectively throughput and the service time

analysis. Analytical results are validated by

simulation using the ns-2 network simulator [16]. In

section 7, we extend our study by simulation, first to

take into consideration different traffic categories,

second, to study the behavior of the DM algorithm in

a multi-hop environment where factors like

interferences or routing protocols exist. Finally, we

conclude the paper in section 8.

2 LITTERATURE REVIEWS

2.1 The 802.11 protocol

2.1.1Description of the IEEE 802.11 DCFUsing DCF, a station shall ensure that the

channel is idle when it attempts to transmit. Then it

selects a random backoff in the contention

window 1CW,0 , where CW is the currentwindow size and varies between the minimum andthe maximum contention window sizes. If the

channel is sensed busy, the station suspends its

backoff until the channel becomes idle for a

Distributed Inter Frame Space (DIFS) after a

successful transmission or an Extended Inter FrameSpace (EIFS) after a collision. The packet is

transmitted when the backoff reaches zero. A packet

is dropped if it collides after maximum

retransmission attempts.

The above described two way handshaking

packet transmission procedure is called basic access

mechanism. DCF defines a four way handshaking

technique called Request To Send/Clear To Send

(RTS/CTS) to prevent the hidden station problem. A

station jS is said to be hidden from iS if jS is

within the transmission range of the receiver of iS

and out of the transmission range of iS .

2.1.2Performance evaluation of the 802.11DCF

Different works have been proposed to evaluate

the performance of the 802.11 protocol based on

Bianchis work [1]. Indeed, Bianchi proposed a

Markov chain based analytical model to evaluate the

saturation throughput of the 802.11 protocol. By

saturation conditions, its meant that contending

stations have always packets to transmit.

Several works extended the Bianchi model either

to suit more realistic scenarios or to evaluate other

performance parameters. Indeed, the authors of [2]

incorporate the frame retry limits in the Bianchis

model and show that Bianchi overestimates the

maximum achievable throughput. The native model

is also extended in [10] to a non saturated

environment. In [12], the authors derive the average

packet service time at a 802.11 node. A new

generalized Z-transform based framework has been

proposed in [3] to derive probabilistic bounds on

MAC layer service time. Therefore, it would be

possible to provide probabilistic end to end delay

bounds in a wireless network.

2.2 Supporting QoS over 802.11

2.2.1 Differentiation mechanisms over 802.11Emerging applications like audio and video

applications require quality of service guarantees in

terms of throughput delay, jitter, loss rate, etc.

Transmitting such flows over wireless

communications require supporting service

differentiation mechanisms over such networks.

Many medium access schemes have been

proposed to provide some QoS enhancements over

the IEEE 802.11 WLAN. Indeed, [4] assigns

different priorities to the incoming flows. Priority

classes are differentiated according to one of three

802.11 parameters: the backoff increase function, the

Inter Frame Spacing (IFS) and the maximum frame

length. Experiments show that all the three

differentiation schemes offer better guarantees for

the highest priority flow. But the backoff increase

function mechanism doesnt perform well with TCP

flows because ACKs affect the differentiationmechanism.

In [7], an algorithm is proposed to provide

service differentiation using two parameters of IEEE

802.11, the backoff interval and the IFS. With this

scheme high priority stations are more likely toaccess the medium than low priority ones. The above

described researches led to the standardization of a

new protocol that supports QoS over 802.11, the

IEEE 802.11e protocol [6].

2.2.2 The IEEE 802.11e EDCAThe IEEE 802.11e proposes a new medium

access mechanism called the Enhanced Distributed

Channel Access (EDCA), that enhances the IEEE

802.11 DCF. With EDCA, each station maintains

four priorities called Access Categories (ACs). Each

access category is characterized by a minimum and a

maximum contention window sizes and an

Arbitration Inter Frame Spacing (AIFS).

Different analytical models have been proposed

to evaluate the performance of 802.11e EDCA. In

[17], Xiao extends Bianchis model to the prioritized

schemes provided by 802.11e by introducing

multiple ACs with distinct minimum and maximum

contention window sizes. But the AIFS

differentiation parameter is lacking in Xiaos model.

Recently Osterbo and Al. have proposed

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different works to evaluate the performance of the

IEEE 802.11e EDCA [13], [14], [15]. They proposed

a model that takes into consideration all the

differentiation parameters of the EDCA especially

the AIFS one. Moreover different parameters of QoS

have been evaluated such as throughput, average

service time, service time distribution and

probabilistic response time bounds for both saturated

and non saturated cases.

Although the IEEE 802.11e EDCA classifies the

traffic into four prioritized ACs, there is still no

guarantee of real time transmission service. This is

due to the lack of a satisfactory scheduling method

for various delay-sensitive flows. Hence, we need a

scheduling policy dedicated to such delay sensitive

flows.

2.3 Real time scheduling over 802.11

A distributed solution for the support of real-

time sources over IEEE 802.11, called Blackburst, is

discussed in [8]. This scheme modifies the MAC

protocol to send short transmissions in order to gain

priority for real-time service. It is shown that this

approach is able to support bounded delays. The

main drawback of this scheme is that it requires

constant intervals for high priority traffic; otherwise

the performance degrades very much.

In [18], the authors introduced a distributedpriority scheduling over 802.11 to support a class of

dynamic priority schedulers such as Earliest

Deadline First (EDF) or Virtual Clock (VC). Indeed,

the EDF policy is used to schedule real time flows

according to their absolute deadlines, where the

absolute deadline is the node arrival time plus thedelay bound.

To realize a distributed scheduling over 802.11,

the authors of [18] used a priority broadcast

mechanism where each station maintains an entry for

the highest priority packet of all other stations. Thus,

stations can adjust their backoff according to other

stations priorities.

The overhead introduced by the broadcast

priority mechanism is negligible. This is due to the

fact that priorities are exchanged using native DATA

and ACK packets. Nevertheless, authors of [18]

proposed a generic backoff policy that can be used

by a class of dynamic priority schedulers no matter ifthis scheduler targets delay sensitive flows or rate

sensitive flows.

In this paper, we focus on delay sensitive flows

and propose to support the fixed priority Deadline

Monotonic (DM) policy over 802.11 to schedule

delay sensitive flows. For instance, we use a priority

broadcast mechanism similar to [18] and introduce a

new medium access backoff policy where the

backoff value is inferred from the deadline

information.

3 SUPPORTING DEADLINE MONOTONIC

(DM) POLICY OVER 802.11

With DCF all the stations share the same

transmission medium. Then, the HOL (Head of Line)

packets of all the stations (highest priority packets)

will contend for the channel with the same priority

even if they have different deadlines.

Introducing DM over 802.11 allows stations

having packets with short deadlines to access the

channel with higher priority than those having

packets with long deadlines. Providing such a QoS

requires distributed scheduling and a new medium

access policy.

3.1 Distributed Scheduling over 802.11To realize a distributed scheduling over 802.11,

we introduce a priority broadcast mechanism similar

to [18]. Indeed each station maintains a local

scheduling table with entries for HOL packets of all

other stations. Each entry in the scheduling table of

node iS comprises two fields jj D,S where jS is

the source node MAC address and jD is the

deadline of the HOL packet of node jS . To

broadcast HOL packets deadlines, we propose to use

the two way handshake DATA/ACK access mode.

When a node iS transmits a DATA packet, it

piggybacks the deadline of its HOL packet. Nodes

hearing the DATA packet add an entry for iS in

their local scheduling tables by filling the

corresponding fields. The receiver of the DATApacket copies the priority of the HOL packet in ACK

before sending the ACK frame. All the stations that

did not hear the DATA packet add an entry for iS

using the information in the ACK packet.

3.2 DM medium access backoff policy

Lets consider two stations 1S and 2S

transmitting two flows with the same deadline 1D

( 1D is expressed as a number of 802.11 slots). The

two stations having the same delay bound can access

the channel with the same priority using the native

802.11 DCF.

Now, we suppose that 1S and 2S transmit flows

with different delay bounds 1D and 2D such as

21 DD , and generate two packets at time instants

1t and 2t . If 2S had the same delay bound as 1S ,

its packet would have been generated at time '2t such

as 212'2 Dtt , where 1221 DDD .At that time, 1S and 2S would have the same

priority and transmit their packets according to the



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802.11 protocol.

Thus, to support DM over 802.11, each station

uses a new backoff policy where the backoff is given

by:

The random backoff selected in 1CW,0 according to 802.11 DCF, referred as BAsic

Backoff (BAB).

The DM Shifting Backoff (DMSB):corresponds to the additional backoff slots thata station with low priority (the HOL packet

having a large deadline) adds to its BAB to

have the same priority as the station with the

highest priority (the HOL packet having the

shortest deadline).

Whenever a station iS sends an ACK or hears

an ACK on the channel its DMSB is revaluated as

follows:

iminii SDTSHOLDeadlineSDMSB (1)

Where imin SDT is the minimum of the HOLpacket deadlines present in iS scheduling table and

iSHOLDeadline is the HOL packet deadline ofnode iS .

Hence, when iS has to transmit its HOL packet

with a delay bound iD , it selects a BAB in the

contention window 1CW,0 min and computes theWHole Backoff (WHB) value as follows:

iii SBABSDMSBSWHB (2)

The station iS decrements its BAB when itsenses an idle slot. Now, we suppose that iS senses

the channel busy. If a successful transmission is

heard, then iS revaluates its DMSB when a correct

ACK is heard. Then the station iS adds the new

DMSB value to its current BAB as in equation (2).

Whereas, if a collision is heard, iS reinitializes its

DMSB and adds it to its current BAB to allow

colliding stations contending with the same priority

as for their first transmission attempt. iS transmits

when its WHB reaches 0. If the transmission fails, iS

doubles its contention window size and repeats the

above procedure until the packet is successfullytransmitted or dropped after maximum

retransmission attempts.

4 MATHEMATICAL MODEL OF THE DM

POLICY OVER 802.11

In this section, we propose a mathematical

model to evaluate the performance of the DM policy

using Markov chain analysis [1]. We consider the

following assumptions:

Assumption 1:

The system under study comprises n contending

stations hearing each other transmissions.

Assumption 2:

Each station iS transmits a flow iF with a delaybound iD . The n stations are divided into two

traffic categories 1Cand 2C such as:

1C represents 1n nodes transmitting flows

with delay bound 1D .

2C represents 2n nodes transmitting flows

with delay bound 2D , such as 21 DD ,

1221 DDD and nnn 21 .

Assumption 3:We operate in saturation conditions: each station has

immediately a packet available for transmission after

the service completion of the previous packet [1].

Assumption 4:A station selects a BAB in a constant contention

window 1W,0 independently of the transmissionattempt. This is a simplifying assumption to limit the

complexity of the mathematical model.

Assumption 5:

We are in stationary conditions, i.e. the n stations

have already sent one packet at least.

Depending on the traffic category to which it

belongs, each station iS will be modeled by a

Markov Chain representing its whole backoff (WHB)

process.

4.1 Markov chain modeling a station of category

C1

Figure 1 illustrates the Markov chain modeling a

station 1S of category 1C . The states of this Markov

chain are described by the following quadruplet

21D,ji,i,R where:

R : takes two values denoted by 2C and

2C~ . When 2C~R , the 2n stations of

category2C

are decrementing their shifting

backoff (DMSB) during 21D slots and

wouldnt contend for the channel. When

2CR , the 21D slots had already been

elapsed and stations of category 2C will

contend for the channel.

i : the value of the BAB selected by 1S in

1W,0 .



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-

Figure 2: Markov chain modeling a category 2C Station

When 2S is in one of the states 21D,0,i,i ,1W..0i , the 1n2 other stations of category

2C have also decremented theirDMSB and can

contend for the channel. Thus, 2S decrements its

BAB and moves to the state 21D,0,1i,i ,1W..2i , only if none of the 1n remaining

stations transmits.

If 2S is in one of the states 21D,0,1i,i ,1W..2i , and at least one of the 1n

remaining stations transmits, the 2n stations of

category 2C will reinitialize their DMSB and 2S

moves to the state 2121 D,D,1i,1i ,1W..2i .

4.3 Blocking probabilities in the Markov chainsAccording to the explanations given in

paragraphs 4.1 and 4.2, the states of the Markov

chains modeling stations 1S and 2S can be divided

into the following groups:

1 : the set of states of 1S where none of the

2n stations of category 2C contends for the

channel (blue states in figure 1).

1D,1i,0maxmin..0j

,1W..0i,D,ji,i,C~

21

2121

1 : the set of states of 1S where stations of

category 2C can contend for the channel

(pink states in figure 1).

1W..Di,D,Di,i,C 21212121

2 : the set of states of 2S where stations of

category 2C do not contend for the channel

(blue states in figure 2).

1D..0j

,1W..0i,D,jD,i,i

21

21212

2 : the set of states of 2S , where stations

of category 2C contend for the channel(pink states in figure 2).

1W..2i,D,0,1i,i

1W..0i,D,0,i,i

21

212

Therefore, when stations of category 1C are in

one the states of 1 , stations of category 2C are in

one of the states of 2 . Similarly, when stations of

category 1C are is in one of the states of 1 ,

stations of category 2C are in one of the states of

2 .

Hence, we derive the expressions of 1S

blocking probabilities 11p and 12p shown in

figure 1 as follows:

11p : the probability that 1S is blocked given

that 1S is in one of the states of 1 . 11p is

the probability that at least a station '1S of

the other 1n1 stations of 1C transmits

given that '1S is in one of the states of 1 .

1n1111 111p (3)

where 11 is the probability that a station'1S

of 1C transmits given that'

1S is in one ofthe states of 1 :

1W

0i

1D,1i,0maxmin

0j

D,ji,i,C~1

D,0,0,C~1

1'111

21

212

212

transmitsSPr

(4)



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21D,ji,i,R1

is defined as the probability of

the state ,D,ji,i,R 21 in the stationary

conditions and 21D,ji,i,R11 is the

probability vector of a category 1C station.

12

p : the probability that1S is blocked

given that 1S is in one of the states of 1 .

12p is the probability that at least a station

'1S of the other 1n1 stations of 1C

transmits given that '1S is in one of the states

of 1 or at least a station'2S of the 2n

stations of 2C transmits given that'2S is in

one of the states of 2 .

21 n221n

1212 111p

(5)

where 12 is the probability that a station

'1S of 1C transmits given that

'1S is in one

of the states of 1 .

1W

Di

D,Di,i,C1

D,0,D,C1

1'112

21

21212

21212

transmitsSPr

(6)

and 22 the probability that a station'2S of

2C transmits given that'2S is in one of the

states of 2 .

1W

2i

D,0,1i,i

2

1W

0i

D,0,i,i

2

D,0,0,02

2'212

2121

21

transmitsSPr

(7)

2121 D,jD,k,i2

is defined as the probability

of the state ,D,jD,k,i 2121 in the

stationary condition. 2121 D,jD,k,i22

is the probability vector of a category 2C

station.

In the same way, we evaluate 21p and 22p the

blocking probabilities of station 2S shown in

figure 2:

21p : the probability that 2S is blocked


1n1121 11p (8)

22p : the probability that 2S is blocked


1n22n

122221 111p

(9)

The blocking probabilities described above

allow deducing the transition state probabilities andhaving the transition probability matrix iP, for a

station of traffic category iC .

Therefore, we can evaluate the state

probabilities by solving the following system [11]:

j

ji

iii

1

P

(10)

4.4 Transition probability matrices

4.4.1 Transition probability matrix of acategory C1 station

Let 1P be the transition probability matrix of

the station 1S of category 1C . j,iP1 is the probability to transit from state i to state j . We

have:

2D,2imin..0j,1W..2i,p1

D,1ji,i,C~,D,ji,i,C~P

2111

2122121

(11)

1D,1Wmin..1i

,p1D,0,0,C~,D,1,i,C~P

21

112122121

(12)

1W..Di,p1

D,Di,i,C,D,1Di,i,C~P

2111

21212212121

(13)

1D,1imin..1j,1W..2i,p

D,ji,ji,C~,D,ji,i,C~P

2111

2122121

(14)

1W..1i

,pD,i,i,C~,D,i,i,C~P 112122121

(15)

1W..1Di,p

D,Di,Di,C~,D,Di,i,CP

2112

2121212212121

(16)

1W..1Di,p1

D,D1i,1i,C,D,Di,i,CP

2112

21212212121

(17)

1W..0i

,W

1D,i,i,C~,D,0,0,C~P 2122121

(18)

If WD21 then:



20/105

-

1W..0i

,W

1D,i,i,C~,D,0,D,CP 212212121

(19)

By replacing 11p and 12p by their values in

equations (3) and (5) and by replacing 1P and 1

in (10) and solving the resulting system, we can

express 21D,ji,i,R1

as a function of 11 , 12 and

22 given respectively by equations (4), (6) and

(7).

4.4.2 Transition probability matrix of acategory C2 station

Let 2P be the transition probability matrix of

the station 2S belonging to the traffic category 2C .

The transition probabilities of 2S are:

1D..0j,1W..0i,p1

D,1jD,i,i,D,jD,i,iP

2121

212121212

(20)

1D..0j,1W..0i

,pD,D,i,i,D,jD,i,iP

21

21212121212

(21)

1W..2i

,p1D,0,1i,i,D,0,i,iP 2221212

(22)

2221212 p1D,0,0,0,D,0,1,1P (23)

1W..1i

,pD,D,i,i,D,0,i,iP 222121212

(24)

1W..2i

,pD,D,1i,1i,D,0,1i,iP 222121212

(25)

1W..3i

,p1D,0,2i,1i,D,0,1i,iP 2221212

(26)

1W..0i,W

1D,D,i,i,D,0,0,0P 2121212 (27)

By replacing 21p and 22p by their values in

equations (8) and (9) and by replacing 2P and 2

in (10) and solving the resulting system, we can

express 2121 D,jD,k,i2

as a function of 11 , 12

and 22 given respectively by equations (4), (6)

and (7). Moreover, by replacing 21D,ji,i,R1

and

2121 D,jD,k,i2

by their values, in equations (4), (6)

and (7), we obtain a system of non linear equations

as follows:

1,1,1,0,0,0

constrainttheunder

,,f

,,f

,,f

221211221211

22121122

22121112

22121111

(28)

Solving the above system (28), allows deducing

the expressions of 11 , 12 and 22 , and deriving

the state probabilities of Markov chains modeling

category 1C and category 2C stations.

5 THROUGHPUT ANALYSIS

In this section, we propose to evaluate iB , the

normalized throughput achieved by a station of

traffic category iC [1]. Hence, we define:

s,iP : the probability that a station iS

belonging to traffic category iC transmits a

packet successfully. Let 1S and 2S be two

stations belonging respectively to traffic

categories 1C and 2C . We have:

1121211111

111

111s,1

Prp1Prp1

PrllysuccessfutransmitsSPr

PrllysuccessfutransmitsSPrP

(29)

22222

222

222s,2

Prp1

PrllysuccessfutransmitsSPrPrllysuccessfutransmitsSPrP

(30)

idleP : the probability that the channel is idle.

The channel is idle if the 1n stations of

category 1C dont transmit given that these stations

are in one of the states of 1 or if the n stations

(both category 1C and category 2C stations) dont

transmit given that stations of category 1C are in

one of the states of 1 . Thus:

1n

22n

121n

11idle Pr11Pr1P211

(31)

Hence, the expression of the throughput of a

category iC station is given by:



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-

c

2

1i

s,iiIdlesseIdle

ps,i

i

TPnP1TPTP

TPB

(32)

Where eT denotes the duration of an empty

slot, sT and cT denote respectively the duration of

a successful transmission and a collision.

2

1i

s,iiIdle PnP1 corresponds to the

probability of collision. Finally pT denotes the

average time required to transmit the packet datapayload. We have:

DIFSTTT

SIFSTTTTT

DACKPHY

DpMACPHYs

(33)

EIFSTTTTT DpMACPHYc (34)

Where PHYT , MACT and ACKT are the

durations of the PHY header, the MACheader and

theACKpacket [1], [13]. DT is the time required to

transmit the two bytes deadline information.

Stations hearing a collision wait during EIFS before

resuming their packets.

For numerical results stations transmit 512

bytes data packets using 802.11.b MAC and PHY

layers parameters (given in table 1) with a data rate

equal to 11Mbps. For simulation scenarios, the

propagation model is a two ray ground model. Thetransmission range of each node is 250m. The

distance between two neighbors is 5m. The EIFS

parameter is set to ACKTimeout as in ns-2, where:

SIFSTTTDIFSACKTimeout DACKPHY (35)

Table 1: 802.11 b parameters.

For all the scenarios, we consider that we are in

presence of n contending stations with2

nstations

for each traffic category. In figure 3, n is fixed to

8 and we depict the throughput achieved by the

different stations present in the network as a

function of the contention window sizeW ,

1D21 . We notice that the throughput achieved

by category 1C stations (stations numbered from

11S to 14S ) is greater than the one achieved by

category 2C stations (stations numbered from 21Sto 24S ).

Figure 3: Normalized throughput as a function of

the contention window size 8n,1D21

Analytically, stations belonging to the same

traffic category have the same throughput given by

equation (32). Simulation results validate analytical

results and show that stations belonging to the same

traffic category (either category 1C or category

2C ) have nearly the same throughput. Thus, we

conclude the fairness of DM between stations of the

same category.

For subsequent throughput scenarios, we focus

on one representative station of each traffic

category. Figure 4, compares category 1C and

category 2C stations throughputs to the one

obtained with 802.11.

Curves are represented as a function of W and

for different values of 21D . Indeed as 21D

increases, the category 1C station throughput

increases, whereas the category 2C stationthroughput decreases. Moreover as W increases,

the difference between stations throughputs is

reduced. This is due to the fact that the shifting backoff becomes negligible compared to the

contention window size.

Finally, we notice that the category 1C station

obtains better throughput with DM than with

Data Rate 11 Mb/s

Slot 20 s

SIFS 10 s

DIFS 50 s

PHY Header 192 s

MAC Header 272 s

ACK 112 s

Short Retry Limit 7



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23/105

-

Otherwise0Z1H

1WDiif

Z1HZ1H

21212

2121221212

D,i,Di,C

21

D,i,Di,CD,i,Di,C

(39)

We also have:

1D,1imin..1j,1W..2i

ZPpZP1

Z1HZp1Z1H

21

T

T

11suc11

T

T

11suc

D,i,i,C~j

11D,ji,i,C~

e

c

e

s

212

212

(40)

2W..Di,Z1ZHp1

ZPpZP1

Z1HZp1Z1H

21D,D1i,1i,C12

T

T

11suc11

T

T

11suc

D,i,i,C~D

11

D,Di,i,C

21212

e

c

e

s

212

21

21212

(41)

e

c

e

s

212

21

21212

T

T

11suc11

T

T

11suc

D,1W,1W,C~D

11

D,D1W,1W,C

ZPpZP1

Z1HZp1

Z1H

(42)

W

1Z1HZp1

ZPpZP1

Z1ZHp1Z1H

1D,1Wmin

2i

D,1,i,C~11

T

T

11suc11

T

T

11suc

D,1,1,C~11D,0,0,C~

21

212

e

c

e

s

212

212

(43)

If 1S transmission state is 212 D,0,0,C~ ,the transmission will be successful only if none of

the 1n1 remaining stations of 1C transmits.Whereas when the station 1S transmission state is

21212 D,0,D,C , the transmission occurssuccessfully only if none of 1n remainingstations (either a category 1C or a category 2C

station) transmits.

If the transmission fails, 1S tries another

transmission. After m retransmissions, if the

packet is not acknowledged, it will be dropped.

Thus, the Z-transform of station 1S service time is:

1m

D,0,D,C12D,0,0,C~11T

T

iD,0,D,C12

D,0,0,C~11

m

0i

T

T

D,0,D,C12

D,0,0,C~11T

T

1

Z1HpZ1HpZ

Z1Hp

Z1HpZZ1Hp1

Z1Hp1ZZTS

21212212

e

c

21212

212

e

c

21212

212

e

s

(44)

6.1.2 Service time Z-transform of a categoryC2 station:

In the same way, let ZTS2 be the servicetime Z-transform of a station 2S of category 2C .

We define:

Z2H2121

D,jD,k,i : The Z-transform of the

time already elapsed from the instant 2S selects a

basic backoff in 1W,0 (i.e. being in one of thestates 2121 D,D,i,i ) to the time it is found in thestate 2121 D,jD,k,i .

Moreover, we define:

21sucP : the probability that 2S observes a

successful transmission on the channel,

while 2S is in one of the states of 2 .

1n1111121suc

11nP (45)

22sucP : the probability that 2S observes a

successful transmission on the channel,

while 2S is in one of the states of 2 .

12

21

n12

2n22222

1n22

1n12121

22suc

111n

11nP

(46)

We evaluate Z2H 2121 D,jD,i,i for each state

of 2S Markov chain as follows:

1Wiand0i,W

1Z2H

2121 D,D,i,i (47)

2W..1i,Z2HZPp

ZPW1Z2H

21

e

c

e

s

2121

D,0,i,1iT

T

22suc22

T

T

22sucD,D,i,i

(48)



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-

To compute Z2H 2121 D,jD,i,i , we define

ZT jdec , such as:

1ZT0dec (49)

21

1jdec

T

T

21suc21

T

T

21suc

21jdec

D..1jfor

ZTZPpZP1

Zp1

ZT

e

c

e

s

(50)

So:

2121

jdecD,1jD,i,iD,jD,i,i

D,0j,i,D..1j,1W..0i

,ZTZ2HZ2H21212121

(51)

And:

2W..2i

ZTZPpZP1

Z2ZHp1

Z2ZHp1Z2H

21e

c

e

s

21

2121

D

dec

T

T

22suc22

T

T

22suc

D,0,i,i22

D,0,i,1i22D,0,1i,i

(52)

ZTZPpZP1

Z2ZHp1

Z2H

21e

c

e

s

21

21

Ddec

T

T

22suc22

T

T

22suc

D,0,1W,1W22

D,0,2W,1W

(53)

According to figure 2 and using equation (51),

we have:

ZTZPpZP1

Z2ZHp1

ZTZ2HZ2H

21e

c

e

s

21

21

2121

Ddec

T

T

22suc22T

T

22suc

D,0,1,122

D

decD,0,1,0D,0,0,0

(54)

Therefore, we can derive an expression of 2S

Z-transform service time as follows:

m

0i

i

D,0,0,0T

T

22D,0,0,0T

T

22

1m

D,0,0,0T

T

222

Z2HZpZ2HZp1

Z2HZpZTS

21

e

c

21

e

s

21

e

c

(55)

6.2 Average Service Time

From equations (44) (respectively equation

(55)), we derive the average service time of a

category 1C station ( respectively a category 2C

station). The average service time of a category iC

station is given by:

1TSX 1ii (56)

Where ZTS 1i , is the derivate of the servicetime Z-transform of a category iC station [11].

By considering the same configuration as in

figure 3, we depict in figure 5, the average service

time of category 1C and category 2C stations as a

function of W . As for the throughput analysis,

stations belonging to the same traffic category have

nearly the same average service value. Sim

final - volume 3 no 4

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