EVALUATION AND IMPLEMENTATION OF

TWO STAGE OP AMP USING SOFTWARE: CADENCE By

DIKITA CHAUHAN

AMITA JOSHI

&

ANUJA KARADKHEDKAR

Academic year:2010-2011

Internal guide:-Mrs. A.A. Askhedkar

1

In this project a design of a two stage fully differential CMOS operational amplifier is presented with the help of tools from Cadence.

The project is being carried out at Pune University –VLSI department due to the availability of CADENCE software.

We are currently using Cadence 5.1.41 which consists of 180 nm technology

2

CADENCE

The cadence toolset is an electronic design automation(EDA) tool, which is intended to develop professional, full scale mixed signal microchips. Other software options: Multisim L Edit Xilinx Micro wind Spice

3

WHY CADENCE?

INDUSTRY STANDARD HIGHLY POPULAR AND WORLD WIDE ACCEPTED

TOOL FOR VLSI PROJECTS. IMPROVED CAPACITY IMPROVED ACCURACY QUICK DETECTION OF CIRCUIT PROBLEMSIMPROVED RELIABILITY RF CAPABILITIES MIXED SIGNAL SIMULATION COVERS ALL DESIGN STAGES OF IC DESIGNING TIME STEPING TRANSITION FROM TANNER TOOLS TO CADENCE“SKILL”LANGUAGE.

4

TOOLS IN CADENCE

VIRTUOSO SPECTRE CIRCUIT SIMULATOR VIRTUOSO LAYOUT EDITER ASSURA RCX DEVELOPER VIRTUOSO ANALOG ELECTRONSTORM

• Thermal plots of signal electro migration are directly shown where you can easily address any identified issues or problems using VIRTUOSO ANALOG

ELECTRONSTORM OPTION

• The option ASSURA highlights the locations in signal lines that are subject to Joule heating failures

5

TYPICAL STRUCTURE OF TWO STAGE OP-AMP:-

• STAGE I : I/p differential stage.• CAPACITOR :Cc• STAGE II : Source follower. • CURRENT MIRROR CIRCUIT

6

ABOUT THE PROJECT :-

PART I: Performance of a basic two-stage

OP-AMP Design issues, constraints, tradeoffs

discussed

PART II: Alternative architectures for

improved performance Design of output stages

7

DESIGN ISSUES:-

TYPICAL SPECIFICATIONS

Supply voltage:+/-2.5V

Dc differential gain :>70 dB ,

Unity gain bandwidth :5 MHz,

Phase margin : 60o,

Slew rate : 10V/us

The power dissipation for 2.29 mW or less.

8

UNBUFFERD TWO STAGE CMOS OPAMP:-

9

GAIN :-

First stage gain:-

Second stage gain:-

10

GAIN BANDWIDTH (GB):-

 GBP = Gain x Bandwidth or A x BW.

The transconductance of the input transistors can be determined from the requirement of the gain bandwidth product and Cc.

Here, GB=gm1/

Cc

11

POWER DISSIPATION:-

Power Dissipation: The amount of power dissipated. It is the product of voltage and total current in the circuit.

Power dissipation=(VDD-(-VSS))*(I6+IBIAS)

12

SLEW RATE:-

The tail current I5 is determined from the slew rate. Slew rate should be as high as possible.

SLEW RATE= I5/Cc

13

INPUT COMMON MODE RANGE:- The input common mode voltage is defined as

ViCM=( V(+) + V(-) )/2.

Positive ICMR:-

Negative ICMR:-

14

WORKING IN CADENCE:Presenting a gist of the steps to design schematics and layout in cadence…

CREATING A LIBRARY

15

ADDING INSTANCE

16

CREATING SCHEMATIC

17

PERFORM THE ANALYIS & SIMULATE

18

LAYOUT

The creation of the mask layout is one of the most important steps in the full-customdesign flow, where the designer describes the detailed geometry and the relative positioning of each mask layer to be used in actual fabrication, using a Layout Editor.

19

VERIFICATION

• DESIGN RULE CHECKER

• LAYOUT VERSUS SCHEMATIC (LVS) CHECK.

After the mask layout design of the circuit is completed and the underlying design extracted, thedesign should be checked against the schematic circuit description created earlier

20

POST LAYOUT SIMULATION

The electrical performance of a full-custom design can be best analyzed by performing a post layout simulation on the extracted circuit net-list.

21

OUR CIRCUIT:-

22

SIMULATION RESULTS:-

23

SIMULATION RESULTS:-

24

SIMULATION RESULTS:-

25

RESULTS:-

PARAMETER

CALCULATED

OBSERVED

GAIN 77.55 dB 73.62 dB

GAIN BANDWIDTH

5 MHz 3.8 MHz

POWER DISSIPATION

0.625 mW 0.765 mW

SLEW RATE

10 V/µs 1.1 V/µs26

NEED FOR HIGH SPEED DESIGN:-

With ever increasing data rates, many applications demand high speed devices like ADC’s etc.

These devices require high accuracy op amps with high DC gain and high unity gain frequency in order to meet both , accuracy and speed of the system.

This is where need of a high speed op amp with good amount of accuracy comes in picture.

Also, signal processing is another area where high speed op amps are needed.

27

IMPROVEMENT IN THE GAIN BANDWIDTH PRODUCT Closed loop instability ->High frequencies . Compensation Capacitor->Increase in phase

margin. Pole Splitting -> Improves closed loop instability Input capacitance increases while output

capacitance decreases. Operation limited to low frequencies.

In an attempt to make Op Am stable BW of first stage decreases hence overall bandwidth decreases.

BW & phase margin should be optimized. RHP zero with compensation.GB decreases. Hence we use buffers. Three types of buffers• Nulling resistor • Current Buffer • Voltage Buffer

28

BUFFERED OP AMP SCHEMATIC

GB=gm1/Cc

Cc decreases.

Hence GB increases.

Also die area is reduced.

29

What next?

Jan 1 – Jan 15 Including the current buffer stageSchematic entry and simulation(for high speed)

Jan 15-jan20 Reduction in supply voltage.

Jan 20- Jan 30 Layout

Feb 1 – Feb 15 Verification

Feb 15- Feb 20 Post layout simulation

30

APPLICATIONS:-

Remote site instrumentationBattery powered systemsActive filters and signal processing In sensor applicationsMobile communications gearLow noise and low power op amp can

be used in medical applications

31

References:-

BOOKS:-P.E Allen and D.R. Holeberg, ”CMOS

Analog Circiut Design”B. Razavi, “Design of Analog CMOS

Integrated Circuits”IEEE PAPERS:-

Ahmed Yuonis and Marwan Hassoun, “High speed Fully Differential op amp design”

G. Palmisano and G. Palumbo, “Compensation Strategy for Two-Stage CMOS Op-Amps Based on Current Buffer”

32

OUR SINCERE THANKS TO

Prof. Mr. Shaligram, VLSI Dept. ,Pune University.

Prof. Mrs. S.G Kulkarni , E&TC Dept, MIT, Pune.

33