fm demod pll

Portland State University

Maseeh College of Engineering and Computer Science

ECE323 Project Report

Phase Locked Loop Based

FM Demodulator

Design and Verification

By:

Hieu Nguyen

Thien Nguyen

Instructor: Prof. Paul Van Hallen

Submitted: June 4th

, 2010

Table of content

I. Abstract --------------------------------------------------------------------------------- 1

II. Introduction ---------------------------------------------------------------------------- 2

III. FM demodulation using phase locked loop --------------------------------------- 3

1. Definitions and operation of a basic PLL ------------------------------------ 3

2. Analysis of a PLL ----------------------------------------------------------------- 7

3. FM demodulation using phase locked loop ---------------------------------- 16

IV. Simulation models of phase locked loop ------------------------------------------ 20

1. Abstract model -------------------------------------------------------------------- 21

2. Behavioral (macro) model ------------------------------------------------------ 28

V. Phase detector design----------------------------------------------------------------- 30

VI. Loop filter design --------------------------------------------------------------------- 49

VII. Voltage controlled oscillator design ----------------------------------------------- 71

1. Operation of emitter-coupled VCO ------------------------------------------- 71

2. Design of emitter-coupled VCO ------------------------------------------------ 72

3. Verification of the VCO’s operation ------------------------------------------ 86

VIII. Output filter design ------------------------------------------------------------------- 91

IX. Phase locked loop design and verification ---------------------------------------- 100

X. Conclusion ------------------------------------------------------------------------------ 111

XI. References ------------------------------------------------------------------------------ 112

XII. Appendixes ----------------------------------------------------------------------------- 113

1. CPI library device characteristics --------------------------------------------- 113

2. Gain block circuit and characteristics ---------------------------------------- 125

3. Fully differential implementation of phase locked loop ------------------- 140

4. Commercial phased locked loop NE564 -------------------------------------- 143

5. Lab experiment results ---------------------------------------------------------- 147

Abstract ECE323 Project – Design of a PLL Based FM Demodulator Page 1

I. Abstract

A phase locked loop (PLL) is a control system that tries to generate an output signal whose phase

is related to the phase of the input reference signal. Phase-locked loops are widely used in radio,

telecommunications, computers and other electronic applications. They may generate stable

frequencies, recover a signal from a noisy communication channel, or distribute clock timing

pulses in digital logic designs such as microprocessors. Due to the wide applications of the PLL,

it is very necessary to understand the operation and design of a PLL system.

In this paper, we first introduce you some basic definitions and operation of a phase locked

loop system, and how to use the phase locked loop as a demodulator. After that, we will go into

more details of a phase locked loop: the design of necessary blocks for a demodulator such as

phase detector, loop filter, and voltage controlled oscillator.

Then, with all these blocks we have designed, we will combine them to create a complete

demodulation circuit using a phase locked loop. Finally, in the Appendix 3, we will extend our

project into one more step. We will discuss the fully differential implementation of phase locked

loop and show you the result of our extended topology.

http://en.wikipedia.org/wiki/Control_system

http://en.wikipedia.org/wiki/Signal_%28electrical_engineering%29

http://en.wikipedia.org/wiki/Phase_%28waves%29

http://en.wikipedia.org/wiki/Radio

http://en.wikipedia.org/wiki/Telecommunications

http://en.wikipedia.org/wiki/Computer

http://en.wikipedia.org/wiki/Microprocessor

Introduction ECE323 Project – Design of a PLL Based FM Demodulator Page 2

II. Introduction

One of the most useful analog circuit technique using for AM and FM demodulation, as well as

performing band-pass filtering is the phase-locked-loop (PLL). This circuit is used widely in

today communications systems. Some of its applications are FM demodulators, tone detectors,

and many others. The basic block diagram of a PLL based FM demodulator is shown in

FigureII.1

Figure II.1: Phase-locked-loop system

In this project, we will build a FM demodulator based on phase locked loop topology. All the

circuits are built only with the Tektronik CPI library in LTSpice. This library contains standard

integrated device model for a real industrial process. Using these devices, we will then present

detailed step-by step design, calculation, simulation, and measurement process to verify the

behavior of our circuit.

There are three main parts that we need to design in our project:

Phase detector

Loop filter

Low-pass filter

Voltage control oscillator

LTSpice is used in our project as the simulation tool because it is completely free and is

supported by a large community.

The design, implementation, and verification are all performed through LTSPICE circuit

simulation.

FM modulation ECE323 Project – Design of a PLL Based FM Demodulator Page 3

III. FM demodulation using phase locked loop

Phase locked loop system (PLL) plays a very important role in electronic world. It keeps the

electronic world orderly. For example, in television, one PLL keeps the feet at the bottom, and the

head at the top of the screen. Another PLL makes the colors unchanged, i.e., red remains red and

green remains green.

Here, a question is posed: “what is the phase locked loop?”. The phase locked loop is a

circuit used to synchronize the output signal with the input signal in frequency or phase. The

output signal is generated by an oscillator, and the input signal is a reference.

When the system is synchronized (often call “locked”), the phase error between the input and

output is zero or a constant. Even though this error sometimes goes up, a control mechanism acts

on the oscillator so that the error will be minimized. With this characteristic, the output signal’s

phase is clocked to the input signal’s phase. Therefore, we have the name “phase locked loop”.

In this first section, we will introduce some basic definitions, the operation, and the analysis

of a PLL. After that, we will discuss FM demodulation using a PLL.

1. Definitions and operation of a basic PLL

A PLL system consists of 4 basic blocks:

Phase detector

Loop filter

Voltage control oscillator

Feedback divider ( which is 1 for our project)

Figure III.1 shows the block diagram of a PLL.

Figure III.1: Diagram of a PLL


In Figure III.1, we are interested in the following signals:

vi(t): the reference input voltage

ωi: the angular frequency of the reference input voltage

vd(t): the output voltage of the phase detector

vf(t): the output voltage of the loop filter

vo(t): the output voltage of the VCO

ωo: the angular frequency of the output voltage of VCO

The first block in Figure III.1 is the phase detector. The phase of the input signal and the

phase of the output signal are two inputs of this block. The phase detector will compare these two

phases and then output a voltage proportional to the difference between the two phases if the

difference is still in an acceptable range. The formula to calculate the output voltage of the phase

detector is given:

𝑣𝑑 𝑡 = 𝐾𝑑𝜃𝑒

where:

Kd is the gain of the phase detector, the unit is 𝑉

𝑟𝑎𝑑

𝜃𝑒 is the phase differene (phase error) between 2 inputs, the unit is rad.

The output of the phase detector 𝑣𝑑 𝑡 consists of a DC component and a superimposed AC

component. Our interest is the DC component. The AC component is undesired. Therefore, we

need a loop filter to remove this AC component. In most cases, to be simple, we use a first-order,

low-pass filter. This is the basic feature for the second block in Figure III.1. This loop filter will

be used to change the magnitude of the signal 𝑣𝑑(𝑡) . Therefore, we can use this loop filter to alter

the bandwidth of the PLL.

The final block in the PLL diagram is the voltage controlled oscillator (VCO). The input of

VCO is the output voltage 𝑢𝑓 from the filter. The output of VCO is the frequency ωo which is fed

back to one of two inputs of the phase detector.


When 𝑢𝑓 is zero, the VCO is free running. We call free running frequency central frequency.

When 𝑢𝑓 changes, the output frequency also changes. Therefore, we can vary the input into the

VCO to change the output frequency. We have the relationship between the input voltage and the

output frequency:

ω𝑜 = ω𝑐𝑒𝑛𝑡𝑟𝑎𝑙 + 𝐾𝑜𝑣𝑓

where

ω𝑐𝑒𝑛𝑡𝑟𝑎𝑙 : 𝑜𝑠𝑐𝑖𝑙𝑙𝑎𝑡𝑖𝑜𝑛 𝑓𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦 𝑤𝑕𝑒𝑛 𝑣𝑓 = 0 𝑜𝑟 𝑐𝑒𝑛𝑡𝑟𝑎𝑙 𝑓𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦 𝑜𝑓 𝑉𝐶𝑂 𝑟𝑎𝑑

𝑠

𝐾𝑜 : 𝑐𝑜𝑛𝑣𝑒𝑟𝑠𝑖𝑜𝑛 𝑔𝑎𝑖𝑛 𝑜𝑟 𝑠𝑙𝑜𝑝𝑒 𝑜𝑓 𝑉𝐶𝑂 (𝑟𝑎𝑑

𝑉. 𝑠)

Now, initially suppose that the input frequency ω𝑖 is equal to the central frequency ω𝑐𝑒𝑛𝑡𝑟𝑎𝑙 ,

i.e, the phase error 𝜃𝑒 is zero. The output of the phase detector vd(t) is zero. So the output of the

loop filter 𝑣𝑓(𝑡) is zero. Because there is no input for the VCO, the output frequency of VCO is

still free running with ω𝑐𝑒𝑛𝑡𝑟𝑎𝑙 . This condition forces two frequencies to be the same.

If the phase error is not zero initially, the phase detector will have a non-zero output voltage.

This will create a non-zero output voltage of the loop filter. In this output voltage will cause the

VCO to change its oscillation frequency in such a way that the error will be minimized.

Now, assume that the input voltage 𝑣𝑖(𝑡) changes its frequency suddenly at the time by an

amount of ∆𝜔. As shown in Figure II.2, the phase of the input begins leading the phase of the

output signal. The phase error is built up and increases with time. So the output of the phase

detector increases with time. The output of the loop filter also increases. This will cause the

oscillation frequency of VCO to increase. Therefore, the error becomes smaller. After some

settling time, the VCO will oscillate at the same frequency as the input signal.


Figure II.2: Transient response of a PLL onto a step variation of the reference frequency

a) reference signal vi(t)

b) output signal vo(t) of VCO

c) output vd(t) of phase detector

d) output vf(t) of the loop filter and oscillation frequency of the VCO

e) frequency of the reference signal

From a network-analysis point of view, the phase detector is a transducer that converts a

frequency difference to a voltage. The loop-filter processes the output voltage of the phase

detector and produces the control voltage to the VCO. The VCO is another transducer that

converts the processed voltage from the loop filter to frequency. The output frequency is then fed

back to the phase detector for comparison with the input frequency. Consequently, network

functions between the output of the phase detector and the input of the VCO are expressed in

terms of voltage. Network functions from the VCO to the phase detector are expressed in terms of

phase or its derivative frequency.


One of the most common applications of a PLL is the multiplication of the reference

frequency. A frequency divider placed in the feedback path of the loop between the VCO output

and the phase detector input multiplies the reference frequency by the frequency-divide ratio. This

can be explained by the basic characteristic of the PLL: two input frequencies of the phase

detector tend to be equal, i.e., the frequency after the frequency divider is equal to the reference

frequency So the VCO frequency at the input of the frequency divider must be at the reference

frequency times the divide ratio. For example, with a frequency divider that has a divide ratio of

2, the frequency of the signal at the output of the VCO will be twice that of the reference.

However, in this project, we do not use this frequency divider. So, we just use the unity

feedback for our PLL.

2. Analysis of a PLL

a. Phase detector mathematical description

First, we begin with a mathematical description of a phase detector. Phase detector is nothing

more than a simple analog multiplier, which is a mixer. We describe two inputs of the phase

detector mathematically:

𝑉1 𝑡 = 𝑉𝑝1cos(𝜔1𝑡 + 𝜃𝑒)

𝑉2 𝑡 = 𝑉𝑝2cos(𝜔2𝑡)

where:

𝑉1 𝑡 : Source 1 signal

𝑉𝑝1: Maximum amplitude of source 1 (V)

𝜔1 = 2𝜋𝑓1: Angular frequency of source 1 (rad/s)

𝜃𝑒 : Phase-error difference between signal 1 and 2 (rad)

t: Time variable (s)

𝑉2 𝑡 : Source 2 signal

𝑉𝑝2: Maximum amplitude of source 2 (V)

𝜔2 = 2𝜋𝑓1: Angular frequency of source 2 (rad/s)


Mixing two input signals produces:

𝑉1 𝑡 𝑉2 𝑡 = 𝑉𝑝1𝑉𝑝2cos(𝜔1𝑡 + 𝜃𝑒)cos(𝜔2𝑡)

Using the geometric formula, we get the following equation:

𝑉1 𝑡 𝑉2 𝑡 = 0.5𝑉𝑝1𝑉𝑝2 cos (𝜔1 − 𝜔2 𝑡 + 𝜃𝑒 + cos((𝜔1 + 𝜔2)𝑡 + 𝜃𝑒)

In the above equation, we have both low and high frequency components, (𝜔1 − 𝜔2) and

(𝜔1 + 𝜔2). However, we are interested in only the low frequency. By eliminating the high-

frequency product with a low-pass filter, we have:

𝑉1 𝑡 𝑉2 𝑡 = 0.5𝑉𝑝1𝑉𝑝2 cos (𝜔1 − 𝜔2 𝑡 + 𝜃𝑒) = 𝑉𝑝cos(ωp𝑡 + 𝜃𝑒) (III.1)

where:

𝑉𝑝 = 0.5𝑉𝑝1𝑉𝑝2: The resulting voltage level after mixing (V)

ωp = 𝜔1 − 𝜔2 (rad/s)

The derivative of (III.1) calculates the incremental phase slope. For the mixer operating with

𝜔1 = 𝜔2 , the derivative of (III.1) yields:

𝑉𝑝𝑑𝑠 𝜃𝑒 =𝑑 𝑉𝑝 cos 𝜃𝑒

𝑑𝜃𝑒= −𝑉𝑝 sin 𝜃𝑒

Where 𝑉𝑝𝑑𝑠 𝜃𝑒 : Phase detector phase slope (V)

When the phase error 𝜃𝑒 is equal to 𝜋

2 , the phase slope 𝑉𝑝𝑑𝑠 is equal to the maximum voltage

𝑉𝑝 , and the gain of phase detector is 𝐾𝑑 = 𝑉𝑝 (𝑉

𝑟𝑎𝑑) . When 𝜃𝑒 is equal to zero, 𝐾𝑑 = 0 . This

shows that maximum phase sensitivity occurs for a 90° phase difference between the input

signals, while a minimum phase sensitivity of 0 occurs for a phase difference of 0°.

With 𝜔1 = 𝜔2 in (III.1), adjusting the phase to 90° phase difference produces 0V at the

intermediate frequency (IF) port of the mixer and gives maximum phase sensitivity for a


measurement. Adjusting the phase to 0° phase difference produces a maximum voltage and gives

minimum phase sensitivity for a measurement.

Figure III.3 shows the relationship between the sinusoidal output of the phase detector and the

phase error with a 5-MHz reference frequency. This figure illustrates that phase can be given in

the units of time (20 ns for one period), cycles, phase in degrees, or phase in radians.

To be consistent in preventing errors, we think it is better to do everything in radians and at

the end convert to the units of interest. Furthermore, Figure III.3 shows that the phase detector

slope is maximized at 𝜋

2 and that is assumed to be the operating point for the linear analysis when

the loop is locked.

Figure III.3: The sinusoidal output of phase detector versus the phase error

b. VCO mathematical description

Next, we will discuss the mathematical model of VCO. What occurs in a VCO is the phase

modulated signal. We have the mathematical description of a VCO as follows:


𝑉𝑜 𝑡 = 𝑉𝑚 cos(𝜔𝑐𝑡 + 𝐾𝑜 𝑉𝑐𝑡𝑙 𝑡 𝑑𝑡) (III.2)

where:

𝑉𝑜 𝑡 : The output voltage of the VCO

𝑉𝑐𝑡𝑙 𝑡 : The control input voltage of the VCO

We are not interested in the amplitude 𝑉𝑚 of the output voltage. We will focus on the

argument of the cosine function, which is the time variation of phase. By taking the derivative of

the argument in (III.2), we have:

𝜔 =𝑑

𝑑𝑡 𝜔𝑐𝑡 + 𝐾𝑜 𝑉𝑐𝑡𝑙 𝑡 𝑑𝑡 = 𝜔𝑐 + 𝐾𝑜𝑉𝑐𝑡𝑙 (III.3)

Here, we want to analyze the loop as a small change from the lock condition. So, the center

frequency of the VCO 𝜔𝑐 is equal to the frequency of the reference signal 𝜔𝑟𝑒𝑓 . Then, we only

concern about the deviation of instantaneous frequency from that locked condition. From (III.3),

we have the deviation of instantaneous frequency as follows:

∆𝑓 =𝜔 − 𝜔𝑐

2𝜋=

𝐾𝑜𝑉𝑐𝑡𝑙

2𝜋

The instantaneous phase is the argument of the cosine function in (III.2):

𝜃𝑖 = 𝜔𝑐𝑡 + 𝐾𝑜 𝑉𝑐𝑡𝑙 𝑡 𝑑𝑡

So, the deviation of instantaneous phase from the lock condition is:

∆𝜃 = 𝜃𝑖 − 𝜔𝑐𝑡 = 𝐾𝑜 𝑉𝑐𝑡𝑙 𝑡 𝑑𝑡

Taking the Laplace transform, we have:

∆𝜃 =𝐾𝑜𝑉𝑐𝑡𝑙 (𝑠)

𝑠 (III.4)


The origin of term 1/s is shown in (III.4). This is the origin of this ideal integrator. This

relationship will be use in the mathematical analysis of the phase locked loop.

c. Phase locked loop mathematical description

We have had the mathematical models for VCO and phase detector already. Now, we need to

combine them to get the overall mathematical formula for our phase detector. To keep track more

easily, again we give the general block diagram of our PLL as shown in Figure III.4.

Figure III.4: Block diagram of a PLL

Here, to be simple, we choose some typical features for our loop filter: first order, one pole,

and one zero. So, the transfer function of the loop filter is:

𝑉𝑒(𝑠)

𝑉𝑑 (𝑠)= 𝐾𝑕

𝑠 + 𝜔𝑧

𝑠 + 𝜔𝑝

where:

𝜔𝑧 : Zero of loop filter (rad/s)

𝜔𝑝 : Pole of loop filter (rad/s)

𝐾𝑕 : mid-band gain of loop filter

By combining these three blocks together, we get the open loop transfer function:


𝐺 𝑠 = 𝐾𝑑 𝑉

𝑟𝑎𝑑 × 𝐾𝑕 × 𝐾𝑜

𝑟𝑎𝑑

𝑉. 𝑠𝑒𝑐 = 𝐾𝑑𝐾𝑕𝐾𝑜 (

1

𝑠𝑒𝑐)

Since the signal of interest for the PLL is not frequency but phase, the output frequency is

integrated in the PLL, which in the frequency domain corresponds to dividing by s, so the overall

forward gain of the PLL is:

𝐺 𝑠 =𝐾𝑑𝐾𝑕𝐾𝑜

𝑠=

𝐾

𝑠

and the overall PLL transfer function (since it is a feedback system) is:

𝜃𝑜

𝜃𝑠=

𝐾

𝑠 + 𝐾

With K is the bandwidth of the PLL in rad/s.

Once the PLL acquires lock, i.e. the VCO frequency is tracking the input frequency, the goal

of the circuit is to maintain lock. If the design is able to maintain lock, it’ll also be able to acquire

lock for most signals of interest. Maintaining lock means that the input to the phase detector never

exceeds the linear range of the phase detector. Because of the periodic behavior of the phase

detector, the output will only change proportionally with the input for a certain range of input

values. As a result the feedback characteristic breaks down when the input exceeds the linear

range and the PLL looses lock.

A second reason for loosing lock is related to the speed with which the PD input changes. If

the change in phase difference is “too fast”, the loop will loose lock as well. The acceptable rate

of change for the input signal is related to the bandwidth of the PLL. The higher the bandwidth

the faster the input can change.

On the other hand making the bandwidth too large is undesirable because it makes the PLL

less selective and noisier. One of the main characteristics of the PLL is its ability to extract

signals from a noisy background. A narrow bandwidth improves the discrimination ability of the

PLL. The choice of the PLL bandwidth is the most important design criterion for a PLL. Based on


the application, the designer must weigh the importance of tracking range and signal

selectivity/noise rejection.

d. Definition of phase

The signal that we are interested in is not the voltage or current. We are interested in the input

phase and output phase. Therefore, we will first discuss a little bit about definition of phase.

Figure III.5 shows one cycle of the sinusoidal signal and various ways to measure the abscissa

value.

Figure III.5: A 2V, 25Hz sine wave showing various measures of the abscissa

The first measure is in time. The three following measures are in phase. However, the phase

measures can be express in cycle (c), in radian (rad), or in degree (0). Because of that, we should

be careful to include units in our calculations. Otherwise, error, typically 2π, will appear in

important parameters.

For example, if the phase 𝜑 is equal to 10𝑡2 𝑟𝑎𝑑

𝑠𝑒𝑐 2, the frequency will be

𝜔 =𝑑𝜑

𝑑𝑡= 20𝑡

𝑟𝑎𝑑

𝑠𝑒𝑐 2


However, the frequency also can be express as

𝑓 = 20𝑡 𝑟𝑎𝑑

𝑠𝑒𝑐2×

1𝑐𝑦𝑐𝑙𝑒

2𝜋𝑟𝑎𝑑= 3.18𝑡

𝑐𝑦𝑐𝑙𝑒

𝑠𝑒𝑐2= 3.18

𝐻𝑧

𝑠𝑒𝑐

In the above example, the symbol f and 𝜔 may give us a clue what the unit should be.

However, if there are many calculations for phase or frequency, the task to remain the right unit

will be difficult because we often have a mistake of not considering radian as a unit.

In addition, in some common practice such as Laplace transform, derivative, or integral, we

often do not incorporate the unit in equations. This also gives us a wrong result. For example,

consider a sine wave 1Vsin(kt), suppose k=5kHz, if we take the derivative

𝑑(1𝑉𝑠𝑖𝑛 𝑘𝑡 )

𝑑𝑡= 𝐾𝑉𝑐𝑜𝑠 𝑘𝑡 (III.5)

It seems there is nothing wrong with the calculation. In fact, the unit is wrong. Equation IV.1

gives a time derivative at 0.01sec of 5𝑐𝑦𝑐𝑙𝑒 ×𝑉

𝑠𝑒𝑐cos(0.05𝑐𝑦𝑐𝑙𝑒). The term 0.05cycle inside the

cosine function can be converted into the correct unit (radian or degree), but the term 5𝑐𝑦𝑐𝑙𝑒 ×𝑉

𝑠𝑒𝑐 is

not the proper unit for the slope of a voltage waveform. So to correct this, we should convert k

from 5Hz to 10π rad/sec.

Then the derivative gives us: 𝐾

𝑟𝑎𝑑𝑉𝑐𝑜𝑠 𝐾𝑡 = 10𝜋

𝑉

𝑠𝑒𝑐 𝑐𝑜𝑠 0.05𝑐 (III.6)

Equation III.6 allows us to use any units.

Next, Figure III.6 shows how the phase different between two signal are define.


Figure III.5: Phase difference between two signals

The phase difference is measured by ∆𝜑 =∆𝑡

𝑇 𝑐𝑦𝑐𝑙𝑒𝑠 (III.7)

Equation III.7 not only illustrates the carrying of units but also the efficiency of using

whatever units are most convenient.

FM demodulation ECE323 Project – Design of a PLL Based FM Demodulator Page 16

3. FM demodulation using phase locked loop

The objective of our project is the design of a Phase-locked-loop (PLL) based FM demodulator

for US FM stations. Before going to design the PLL, we first present some basic information

about FM signal.

Transmitting baseband information, e.g. audio, video or data, at baseband frequencies is not

very efficient for a number of reasons:

We can only transmit one signal at a time because more than one could cause

overlap and we cannot separate them.

The low frequency signal is subjected to high loss in the atmosphere.

The size of the antenna related to the wavelength of the signal could be

enormously huge for the low frequency signal

A more effective use of the frequency spectrum is to modulate a carrier frequency with the

baseband information and to transmit the modulated carrier.

Given a time varying signal which is to be used as the carrier of information

𝑐 𝑡 = 𝐴𝑠𝑖𝑛(𝜔𝑡 + ∅)

This signal can convey useful information through its amplitude A, its frequency ω, and its

phase angle ∅. The carrier conveys little or no useful information unless we make at least one of

these characteristic a time dependent function. Varying one of these quantities with time is called

modulation. If the amplitude is varying, i.e. A(t), the resulting modulation is called Amplitude

Modulation (AM). If the frequency is conveying the information the scheme is called Frequency

Modulation (FM), and in the case of varying phase, it’s Phase Modulation (PM). For radio

broadcasting both AM and FM are used.

FM radio stations in the US are allocated a frequency range from 87.5 MHz to 108.1 MHz, at

0.2 MHz spacing. In order to avoid station overlap, stations are allowed to transmit signals that

deviate ± 75 kHz from their carrier frequency. The modulating signal used to create this 75 kHz


modulation has a total bandwidth of 53 kHz. This modulating signal contains several

components.

Early FM broadcasts were monophonic, with stereophonic FM broadcasting, with L(eft) and

R(ight) signals, coming quite a bit later. The FCC ruled that the stereo system had to be

compatible with the original mono system. To maintain compatibility, the following scheme was

developed. The audio frequency of the left and right stereo signals are first filtered, so that the

signal bandwidth is limited to 15 kHz. At the transmitter, the two signals L and R are added and

subtracted to obtain L+R and L-R. For noise purposes these signals are preprocessed (pre-

emphasized). Pre-emphasis consists of a shaping of the signal spectrum. During FM

modulation/demodulation the higher audio frequencies suffer more from noise. At the transmitter

the signals are filtered with a shaping filter which boosts the high frequencies with respect to the

low frequencies. The de-emphasis at the receiving end removes the reshaping by attenuating the

high frequencies. In the process of de-emphasis the high frequency noise is also attenuated.

Following the pre-emphasis, the (L+R) signal is used directly and the (L-R) is used to

amplitude modulate (AM) a 38 kHz carrier frequency. The resulting modulation is DSB-SC

(Double side band, suppressed carrier AM modulation). In other words, the modulated L-R

signal spreads from 23 kHz to 53 kHz, with no signal at 38 kHz. A third component in the

baseband signal is a 19 kHz pilot. The presence of the 19 kHz carrier indicates a stereo broadcast

and will be used in the receiver to reconstruct the suppressed 38 kHz carrier. The reason for

using a 19 kHz pilot is that it is easier to extract because there are no signal components within 4

kHz of that frequency.

The composite baseband signal is thus given by

𝑚 𝑡 = 𝐿 + 𝑅 + 𝐿 − 𝑅 𝑐𝑜𝑠𝜔𝑚 𝑡 + 𝛼𝑐𝑜𝑠𝜔𝑚 𝑡

2

The FM stereo transmitter and the spectrum of the baseband stereo signal are shown in

Figure III.6.


Figure III.6: FM Stereo Transmitter and Baseband Spectrum

This baseband signal m(t) is used to modulate a second, high frequency, carrier ωc so that

𝜔𝑜 = 𝜔𝑐 + 𝛼𝑚(𝑡)

where 𝜔𝑜 is the instantaneous frequency of the FM modulated carrier. For the sake of economy

and ease of signal processing, the carrier frequency 𝜔𝑐 that’s being modulated is an intermediate

frequency (IF) equal to 10.7 MHz. This modulated IF frequency is then multiplied with a

reference frequency to generate the transmit frequency. Remember from trigonometry that

multiplying two sine waves produces a signal at the sum and difference frequencies. So

multiplying the modulated IF frequency with a 91.2 MHz signal would produce 101.9 MHz and

80.5 MHz. This signal is pass-band filtered so that only the signal in the FM band remains. The

multiplier frequency determines the signal frequency of a particular radio station.


At the receiving end the whole procedure is reversed. The signal received from the antenna is

first amplified. Tuning your radio selects a frequency for a local oscillator (LO) which will

produce the “beat” frequency with which to multiply the incoming signal. For the local KINK

station, the incoming radio frequency signal at 101.9 MHz is multiplied with a 91.2 MHz LO

reference. This again produces signals with sum and difference frequency. The difference

frequency, situated around the IF frequency of 10.7 MHz is filtered with a pass-band filter,

centered on 10.7 MHz and with a bandwidth of ± 100 kHz The signal that remains after filtering

is the FM modulated IF frequency.

This IF signal is the input signal to be used for your PLL design. In a later section we’ll

explain how to generate this input signal.

Simulation model ECE323 Project – Design of a PLL Based FM Demodulator Page 20

IV. Simulation models of phase locked

Simulation of PLL circuit at the transistor level has several drawbacks:

Simulation time is considerably slow (up to several hours for each run)

Linear simulations cannot be accomplished due to the non-linear characteristic of

the PLL when it is acquiring lock (unlocked conditions)

That’s why we need to figure out some ways to simulate the PLL efficiently. Being able to

simulate the PLL at different level gives us a better insight about the operation of PLL and speed

up the design process significantly.

In our design process, we design the PLL based on the mathematical model (transfer

functions).

Then, there are two different functional system-level models that we use to verify the design.

They are:

Abstract (behavioral) model

Macro model

The former is very close to the mathematical model that enables us to verify the frequency

response and some other characteristics. The latter is the actual functional block that we are

going to build at the transistor level. Thus, the macro model is very helpful for quick verification

where we replace each block at the macro model by our actual circuit. The basic elements of the

two models are presented here so that we can refer to it latter.


1. Abstract model

This model is based on the mathematical relationship between the input and output of each

block rather than the time varying signal.

(a) Phase detector: pdtriangle

Figure IV.1 shows the symbol of the pdtriangle – the phase detector at the abstract level

where it operates directly on two signals that represent phase. The output is calculated by

difference between the two “phase” inputs.

As we can see in the model definition, the non-linear behavior of it is accomplished by taking

the inverse sine after taking sine. This make the whole characteristic become periodic. The

conversion gain can be modified.

* pdtriangle

.subckt pdtriangle pdp pdn pdo ref .params rin=1Meg rout=1 kd=2/pi R1 pdp pdn rin R2 src pdo rout B1 src ref V=kd*asin(sin(V(pdp) - V(pdn))) .ends pdtriangle

This is a simple non-linear model for the XOR phase detector that we implement in our

physical PLL. To use this model we need to represent frequency and phase as a voltage. The

pdtriangle model produces a triangular waveform output as a function of the difference between

its two inputs, i.e. the output represents the time-average of the output of the real XOR phase-

detector. The input signals to this model have to be voltages which represents phase.

To show the basic operation of the pdtriangle phase detector, we use the simple circuit shown

in Figure IV.2. The DC voltage input represents phase that is swept to generate the output

characteristic of the phase detector.

Figure IV.1 - pdtriangle symbol


Figure IV.2 - pdtriangle test circuit

The result is shown in Figure IV.3, in which the input voltage has been converted to degree.

We can see that the linear range of this model is from −𝜋

2→𝜋

2. We will see shortly in the design

part of our phase detector that this is the exact behavior that we want to implement at the

transistor level.

By changing the object from time varying signals to phase, we can do some specific

simulations with this model, especially the AC analysis.

Figure IV.3 - Phase detector output versus phase difference


One important thing from this model is that the output is indeed the voltage signal that we

can apply to our actual loop filter. Therefore, this abstract model is an ultimate tool that we use

for designing loop filter.

Another abstract model that we use is the integrator. In the real circuit, integration of

frequency to develop phase is inherently done inside the VCO. Thus, we need to take into

account this behavior in our model.

(b) Integrator

The symbol and Spice sub-circuit model of the abstract integrator is shown in Figure IV.4

Figure IV.4 - Integrator symbol

In this model, we employ the Laplace transform to do the integration:

𝐿 𝑑𝑡 =1

𝑠

A low frequency pole is added at very low frequency (1m) to prevent the function go to

infinity at low frequency.

A scale factor of 2𝜋 is default for this model, so that the input of it is the frequency in Hertz

(not rad/sec).

A simple circuit to test this integrator is shown in Figure IV.5 and the result is shown in

Figure IV.6. The input signal has the DC offset that make the output voltage go up linearly due

to integration.

* integrator

.subckt integrator in out ref

.params a=2*pi rin=1Meg rout=1

R1 in ref rin

B1 aout ref V=a*v(in)

Laplace=1/(s+1m)

R2 out aout rout

.ends integrator

*


Figure IV.5 - Integrator test circuit

Figure IV.6 - Waveform outputs from the integrator test circuit

The only thing left for the PLL is the voltage-controlled oscillator. The VCO implementation

at the abstract level will be shown shortly, and we will see how easy it is to make a VCO at this

level.

(c) Voltage-controlled oscillator (VCO)

The signal out of the pdtriangle phase detector is the actual voltage signal that we apple to

the loop filter. The output of loop filter is the voltage that we apply to the VCO.

The output frequency of the VCO is related to the input voltage by the equation

f = f0 ± KoVc


To translate this equation into the behavioral model, we only need to employ the built-in

behavioral voltage source of LTSpice. The conversion from the input voltage to the output

voltage that represents frequency is followed by a integration step to generate the developing

phase. The complete model for the VCO at the abstract level is shown in Figure IV.6

Figure IV.6 - VCO abstract model

The complete PLL at this level of abstraction is shown in Figure IV.7, in which the loop filter

is the actual circuit using op-amp. This model of PLL is ideal for investigating stability issue of

the PLL. As an example, we will use this to illustrate some of the concepts that we introduce in

previous sections. These illustrations will be repeated throughout out design process to achieve

the desired circuit.

Figure IV.7 - Abstract model of the PLL

The first very important simulation is the frequency response of the PLL. As we known the

input of the PLL is phase/frequency. However, this phase/frequency is also modulated by

another frequency. The response of PLL to this modulating frequency is what we mean by saying

the frequency response of the PLL.


As we design a FM demodulator, we only focus on the voltage output of the PLL (that is the

input of VCO)

A sample set of frequency response of PLL is shown in Figure IV.8

Figure IV.8 - Frequency response of PLL

Depending on our design of the loop filter, the bandwidth as well as the amount of peaking

in the frequency response will be different. This consideration will be examined in detail in the

loop filter design section.

In the previous section, we introduce the concept of tracking range and capture range. We

will now show how to verify these parameters of the PLL by using the abstract model.

Figure IV.9 - Tracking characteristics of the PLL


The input frequency is swept slowly from low to high and the back down from high to low.

The PLL does not respond to the input signal until its frequency reaches 𝑓1. This is the lower

edge of the capture range. Then the loop continues to track the input signal until its frequency

reaches 𝑓2. This is the upper edge of the tracking range.

When the frequency is slowly swept back toward low frequency, this cycle is repeated. Thus,

we can find the other limit of the capture range and lock range.

This tracking behavior is summarized in Figure IV.10

Figure IV.10 - PLL frequency-to-voltage transfer characteristics

(a) Slowly increasing input frequency

(b) Slowly decreasing input frequency

(c) Composite voltage-to-frequency transfer

characteristics

In the above section, we have introduced the behavioral models for all the elements of a PLL.

We see that in this model is only useful to verify the loop filter. Thus, we need another model

(c)


that actually working on the time-varying signal, so that we can verify other elements of the

loop. The macro model is the solution for this issue.

2. Macro model

Unlike the behavioral model that closely related to the mathematical description of each

element, the macro model behaves like the actual transistor circuit. The only thing is that we use

some functions of Spice to do that, not by the circuit elements. The great advantage of this is that

it behaves ideally as what we want. Thus, we can use them as a goal for our circuit design.

Replacing one by one ideal element with our physical circuit is a cure for designing such a huge

system like a PLL.

Moreover, due to their mathematical nature, the macro model speeds up the simulation time

quite considerable. The complete macro model for the PLL is shown in Figure IV.11

Figure IV.11 - Macro model of the PLL

The two VCO blocks are the ones that we already introduced in the previous project. The

loop filter is the actual filter that we put there.

The only thing left in the loop is the exclusive-OR logic gate. It is somewhat strange when

we put this “digital” gate inside our PLL. However, it will be clear in the phase detector design

section that this EX-OR gate is a simple implementation of a phase detector.

One extra element outside the loop is the source with a Laplace transform function. This is

the way to implement the output filter.


The macro model is extremely important for us to verify the time-domain behavior of the

PLL.

The two models (behavioral and macro) will be employed to design the transistor level PLL.

Phase Detector Design ECE323 Project – Design of a PLL Based FM Demodulator Page 30

V. Phase detector design

The basic model that we used to described a phase detector (PD) is:

𝑣𝑑 = 𝐾𝑑𝜃𝑒 + 𝑉𝑑0

In which:

𝐾𝑑 is the conversion gain of the phase detector (V/rad)

𝜃𝑒 is the phase error between the two inputs of the PD

𝑉𝑑0 is the offset voltage (free-running voltage)

This is the basic linear model for the PD that we use to implement the PLL. One important

note is that this linear model is only valid for a certain “range” of the phase difference. The range

of the PD depends on which topology is used to realize this model. This concept is illustrated in

Figure V.1.

Figure V.1 - Linear phase-detector characteristic

As an introduction, we will introduce some basic topologies that can be used as a phase

detector. More details on these topologies can be found in reference materials.

1. Four-quadrant multiplier

This topology based on the Gilbert multiplier circuit. This multiplier cell is shown in

FigureV.2


Figure V.2 - Gilbert multiplier cell

This multiplier behaves as a PD based on the identity

sin(A)cos(B) = 0.5sin(A-B) + 0.5sin(A+B)

Thus, the output of the multiplier consists of two components: the first one related to the

phase difference, the second one is a high frequency signal that can be easily filtered out.

This is the most basic realization of the PD. However, it also has some drawbacks. First, this

topology has a very small linear range. As we known, sin(a) ≈ a is only valid when a is very

small. This is illustrated in Figure V.3. The second thing is that the output of the multiplier also

depends on the amplitudes of the two input signals. This fact is undesirable in our phase detector

because the conversion gain in this case is not well-defined.

Figure V.3 - Sinusoidal phase-detector characteristic


The solution for that is to overdrive the multiplier, so that all transistors act as switches. This

kind of PD is so-called triangular phase detector which is also our choice for the PD in our PLL.

2. Exclusive-OR phase detector

When the multiplier is overdriven, this circuit acts as an exclusive-OR logic circuit.

This is the topology that we use for our phase-detector realization for the PLL-based FM

demodulator.

This circuit has the advantages of greater 𝐾𝑑 and greater linear phase range. However, the

nonlinearity of the digital circuit aggravates the effect of noise. The circuit will be examined in

details in the next section, where we actually design an EX-OR based phase-detector. For the

meantime, we continue the introduction of phase-detector topologies.

3. Sequential phase-detector

This type of phase-detector generates error voltages proportional to the phase difference by

detecting the zero crossings of the input and VCO signals.

Basically, the sequential phase-detector is based on edge-triggered circuits (flip-flops).

Some important properties of a sequential phase-detector are:

Not sensitive to duty-cycle or the exact waveform (only the transitions)

Has a wider detection range (more than ±2π)

Be able to indicate the polarity of the frequency difference when the loop is out of lock

Sensitive to missing pulses or extra transitions

These characteristics make this type of phase-detector suitable for frequency synthesis

applications where the input signal is very clean. For a random signal as FM, the EX-OR type

phase detector is more suitable.

In the above discussion, we take a detour to show some of the possible realizations of a phase

detector. Interested readers can find these topics in much more details in the cited materials.


Next, we will focus on the operation and the design process of the particular EX-OR phase

detector that we use for our PLL-based FM demodulator.

Phase-detector – using EX-OR gate

The EX-OR type phase-detector is based on the multiplier circuit. So, we analyze how to

perform a multiplication with analog circuit first.

To perform multiplication with analog circuit, we need to employ an analog multiplier.

There are some ways of implementing a multiplier. The simplest way is the multiplier using

the log and anti-log op-amp circuit. This kind of circuit is shown in Figure V.4

Figure V.4 - Analog multiplier with op-amps

Despite the ease of implementing, this op-amp multiplier has a critical limitation due to a

limited frequency response of the op-amp. Therefore, a multiplier implemented at the transistor

level is more appeal in terms of frequency performance.

The multiplier is thus created based on the exponential transfer function of bipolar transistors.


We first examine the most basic multiplier using the emitter-coupled pair. This kind of circuit

is shown in Figure V.5

Figure V.5 - Emitter-coupled pair

The differential pair produces output currents that are related to the input voltage by

𝐼𝑐1 =𝐼𝐸𝐸

1 + 𝑒−(𝑉𝑖𝑑𝑉𝑇

)


1 + 𝑒(𝑉𝑖𝑑𝑉𝑇

)

These two equations can be used to find the difference between the two output currents

∆𝐼𝐶 = 𝐼𝑐1 − 𝐼𝑐2 = 𝐼𝐸𝐸𝑒

(𝑉𝑖𝑑𝑉𝑇

)− 𝑒

−(𝑉𝑖𝑑𝑉𝑇

)

1 + 𝑒−(𝑉𝑖𝑑𝑉𝑇

) 1 + 𝑒

(𝑉𝑖𝑑𝑉𝑇

)

= 𝐼𝐸𝐸𝑡𝑎𝑛ℎ 𝑉𝑖𝑑2𝑉𝑇


Figure I.6 - Voltage-to-current transfer characteristics for the differential pair

If the differential input voltage is much less than 𝑉𝑇 , that equation can be approximated by

∆𝐼𝐶 ≅ 𝐼𝐸𝐸 𝑉𝑖𝑑2𝑉𝑇

The bias current 𝐼𝐸𝐸 can be controlled by another voltage. By making this current proportional

to an input voltage, we ca n create an analog multiplier.

From the circuit in Figure V.7, we have

𝐼𝐸𝐸 ≅𝑉𝑖2 − 𝑉𝐵𝐸

𝑅

Figure II.7 – Two quadrant multiplier


Substitute this equation into the difference output current, we get

∆𝐼𝐶 =𝑉𝑖2−𝑉𝐵𝐸

𝑅 𝑉𝑖𝑑2𝑉𝑇

Thus, this circuit acts as a multiplier that multiply 𝑉𝑖2 and 𝑉𝑖𝑑 . However, this circuit only

works under these two conditions

𝑉𝑖𝑑 ≪ 2𝑉𝑇

𝑉𝑖2 > 𝑉𝐵𝐸

The second condition restricts the multiplier to only two quadrants. Hence, this type of circuit

is so-called two-quadrant multiplier.

Gilbert came up with a circuit that allows four-quadrant multiplication. The Gilbert multiplier

cell is shown in Figure V.8.

Figure III.8 - Four-quadrant Gilbert multiplier circuit


The collector currents of the transistors Q3 – Q6 in the above circuit are:

𝐼𝑐3 =𝐼𝑐1

1 + 𝑒−(

𝑉1𝑉𝑇

)


1 + 𝑒(𝑉1𝑉𝑇

)



)


1 + 𝑒−(

𝑉1𝑉𝑇

)

Similarly, the collector currents of the transistors Q1 – Q2 are:


1 + 𝑒−(

𝑉2𝑉𝑇

)



)

Replacing the two equations for 𝐼𝑐1 and 𝐼𝑐2 into the equations for 𝐼𝑐3 - 𝐼𝑐6, we get


1 + 𝑒−(

𝑉1𝑉𝑇

) 1 + 𝑒

−(𝑉2𝑉𝑇

)



) 1 + 𝑒

−(𝑉2𝑉𝑇

)



) 1 + 𝑒

(𝑉2𝑉𝑇

)


1 + 𝑒−(

𝑉1𝑉𝑇

) 1 + 𝑒

(𝑉2𝑉𝑇

)


The differential output current is given by

∆𝐼𝐶 = 𝐼𝑐3−5 − 𝐼𝑐4−6 = 𝐼𝑐3 + 𝐼𝑐5 − 𝐼𝑐4 + 𝐼𝑐6

∆𝐼𝐶 = 𝐼𝐸𝐸𝑡𝑎𝑛ℎ 𝑉1

2𝑉𝑇 𝑡𝑎𝑛ℎ

𝑉2

2𝑉𝑇

As we have already known 𝑡𝑎𝑛ℎ𝑥 ≈ 𝑥 (𝑥 𝑠𝑚𝑎𝑙𝑙), the output current is approximately,

∆𝐼𝐶 ≅ 𝐼𝐸𝐸 𝑉1

2𝑉𝑇

𝑉2

2𝑉𝑇 𝑉1 ,𝑉2 ≪ 𝑉𝑇

Therefore, for small-amplitude signals, the circuit performs an analog multiplication.

This multiplier can be use as a phase detector (this is the multiplier phase-detector that we

introduce before).

If we overdrive the two inputs of the Gilbert multiplier cell, it will act as an exclusive-OR

phase detector.

First, we consider two square wave signals with the same frequency as the input to the

multiplier. The magnitudes of the two signals are large so that the transistors act as switches. The

behavior of the circuit when the input signals are overridden is shown in Figure V.9

Under large-signal condition, this circuit will produce an average output voltage whose value

is proportional to the phase difference between the two inputs.

We will then derive the relation between the output voltage related to the phase difference.

The DC component of the waveform is given by

𝑉𝑎𝑣𝑔 =1

2𝜋 𝑉 𝑡 𝑑(𝜔𝑜𝑡)

2𝜋

0

= 𝐼𝐸𝐸𝑅𝑐 2∅

𝜋− 1

The phase relationship is plotted in Figure V.10


Figure V.9 - Approximate equivalent circuit for an emitter-coupled EX-OR gate

Figure V.10 - Input and output waveform of the EX-OR phase detector


Figure V.11 - Phase detector output voltage versus phase difference

This phase detector is widely used in phase-locked loop and we thus used this topology for

our phase detector block.

Design of the phase detector

We design our XOR-phase detector using CPI devices.

First, we determine the bias current 𝐼𝐸𝐸 that use for biasing the circuit. As we can see from the

characteristic of the wn2 transistor in Appendix 1, the optimized collector current for the wn2 is

approximately 250µA. Thus, we will use a 500µA current source to bias the circuit. A current-

mirror current source is used to generate this biasing current.

To generate the bias current for the differential pair, we need a current source of 500µA

(250µA for each wn2 transistor)

The required current can be produced by two solutions:

Use two parallel wn2 transistors in the current mirror source.

Use the wn8 device with the resistor in the emitter to change the Base-Emitter voltage.

The second solution has the advantage of larger output resistance due to the effect of the

emitter degeneration resistor (increase the effective Early voltage.) Thus, we will use a wn8

device with a resistor in its emitter to control the output current. We have


𝐼𝐼𝑁 =𝑉𝑐𝑐 − 𝑉𝐵𝐸3 − 𝑉𝐵𝐸1 − 𝑉𝑒𝑒

𝑅1

𝑅1 =5𝑉 − 0.7𝑉 − 0.7𝑉 + 5𝑉

250𝜇𝐴= 34.4𝑘Ω

Choose R1 = 36 kΩ because 4 kΩ resistors are available in the CPI library.

To produce a 500 μA current source, we use the Widlar current source with wn8 transistor as

the output transistor.

The value of the emitter resistor of Q2 is

RE =VT

Ioln

IIN

Io

AE2

AE1 =

25.86mV

500μAln

250

500

4

1 = 35.85Ω

We use a 40 Ω resistor for RE .

The circuit is shown in Figure V.12

Figure V.12 - Current mirror source for the phase detector

As required by the project specification, the expected conversion gain is 2 V / π rad

(0.63V/rad). We can notice from the Figure V.11, the linear range of this type of phase detector is

from 0 to π.


The conversion gain is therefore

𝐾𝑑 =∆𝑉𝑜∆∅

=2𝐼𝐸𝐸𝑅𝑐𝜋

To achieve the requirement of 𝐾𝑑 =2

𝜋(

𝑉

𝑟𝑎𝑑), we must have 𝐼𝐸𝐸𝑅𝑐 = 1𝑉.

With the biasing current 𝐼𝐸𝐸 = 500𝜇𝐴, the collector resistor is 𝑅𝑐 =1𝑉

500𝜇𝐴= 2𝑘Ω.

Therefore, the complete phase detector circuit is shown in Figure V.13

Figure V.13 - Complete circuit for the phase detector

Next, we will verify the behavior of this circuit. To plot the output voltage versus phase

difference, we simulate the circuit with these Spice directives:


.tran 0 15u 14.9u 1n uic

.step param tdel 0 1000n 25n

.options plotwinsize=0 numdgt=7

The two inputs of the phase detector are:

PULSE(0.5 -0.5 tdel 1n 1n 500n 1000n)

PULSE(-0.5 0.5 0 1n 1n 500n 1000n)

In order to get the desired curve, we need to convert time to phase difference and compute the

average value of the output. We do it by adding two behavioral sources as shown in Figure V.14

Figure V.14 – Output behavioral sources for simulation

Then, the resulting output voltage versus phase difference plot is shown in Figure V.15

Figure V.15 - Output voltage versus phase difference

As we can see from the Figure, the average output voltage is a linear function of the phase

difference between the two inputs.


There is only a small error in the voltage level, a swing of -1V → +1V is achieved.

The maximum and minimum output voltage is about ±0.99V. The reason is simply because

the resistors we use for the current source is not exactly matched with the calculation. In addition,

the base currents are completely ignored in our computation. These reasons lead to the error in the

output voltage.

However, this variation is acceptable (≈1%). Hence, a re-design step is skipped, and this phase

detector circuit is ready to be used.

Before moving on to the next component of the PLL, we use the macro model of the PD that

is the EX-OR gate to verify the ideal behavior of the PD.

When the two input is in-phase: the output stays at low level


When the two input is out-of-phase: the output stays at high level

When the two input is 90o phase different: the output is square wave with 50% duty cycle and the

frequency is twice the input frequency. The average value is zero.


Total response of the macro model phase detector is shown in Figure V.16

Figure V.16 - Output voltage versus phase difference of the macro model PD

We can see that the response from the macro-model (the EX-OR gate) is exactly the same as

our transistor-level circuit. Thus, the circuit that we build meets the requirements of a phase-

detector and can be used in a PLL-based demodulator.

One observation is that the output voltages are differential. Each of the individual output has a

DC offset voltage of about 4.5V (near the positive rail.) This fact should be taken into

consideration when we connects these output to the loop filter.

The loop filter use our gain block as the active element. This gain block is actually a single

gain stage followed by an output buffer. The schematic as well as characteristics of this gain

block can be found in Appendix 2.

The consideration here is that this simple gain stage probably cannot handle this large offset

voltage. Thus, a level shifting is a good practice here.

To bring the output level down, we connect the output to a buffer stage. This stage will add a

few diode drops to the output voltage. The schematic is shown in Figure V.17


Figure V.17 - Output buffer for the PD

This buffer stage brings the output offset voltage to about -200mV. This offset level is

acceptable for most application.

One more benefit from this buffer stage is to provide shielding for the phase detector circuit.

The phase detector output is connected to the loop filter that will be discussed next.

Loop Filter ECE323 Project – Design of a PLL Based FM Demodulator Page 49

VI. Loop filter

As we have already known, the 3-dB cut-off frequency of the PLL is given by

𝝎𝟑𝒅𝑩 = 𝑲𝒅𝑲𝒉𝑲𝒐 ≡ 𝑲

This is also the bandwidth of the PLL. This value is determined by the conversion gain of the

PD (𝐾𝑑 ), the sensitivity of the VCO (𝐾𝑜 ), and the high frequency gain of the loop filter (𝐾ℎ ).

Depending on the application, the bandwidth of the PLL needs to be “shaped” for a desired

loop response.

From the feedback and control theory, this “loop shaping” task can be done by adding a

compensator into the loop. The loop before compensating is a first-order system. The integration

property that inherently present in the VCO gives the loop one pole at zero.

The loop transfer function before compensating is:

𝐺 𝑠 𝐻 𝑠 =𝐾𝑑𝐾𝑜

𝑠

This type of system is referred to as a type-1 system. For the type 1 system, one of the

limitation that affects our phase lock loop design is that it has a steady state error for the ramp

input signal. This is illustrated in Figure VI.1

Figure VI.1 - Steady state error to ramp input of type-1 system


The input signal to a PLL is phase that is the integral of frequency.

𝜃 = 𝜔𝑑𝑡

From this equation, when the input frequency is a constant, the phase is basically a ramp

function of time. Therefore, the most basic input signal to the PLL is the ramp function and we

need to optimize the response for this input signal.

The phase error when the input frequency is constant is in fact the steady state phase error for

the ramp input, and is often referred to as static phase error.

This static phase error is undesirable. The reason is that this static phase error is the input to

the phase detector which has a limited linear range (0 – π for the XOR phase detector.)

Therefore, the uncompensated system has a limitation on the linear range. A solution for this

problem is to add one more integrator to the loop.

Thus, a proportional-integral (PI) compensator is a good solution for this issue.

The basic transfer function for a proportional-integral compensator is:

𝑮𝑪 𝒔 = 𝑲𝑷 +𝑲𝑰

𝒔

This is also special case of a lag compensator and is in fact a low pass filter.

The performance improvement with a PI compensator is illustrated in the Figure VI.2

Another way to derive the phase error is to look at the operation of the PLL in the lock

condition. When the PLL is locked on the input signal, the VCO frequency is identical to the

input frequency. However, a finite phase difference (so-called phase error) is still present,

because this error is needed to generate the corrective error voltage (from the PD) to shift the

VCO frequency from the free running frequency to the input signal frequency. This is necessary

to maintain lock.


A loop filter can significantly reduce the phase error (ideally this error will be zero when we

add an integrator to the loop, but an ideal integrator cannot be realized with normal-op amp)

Figure VI.2 - Steady-state error to ramp input of a compensated system

Design of Loop filter

The loop filter determine most of the dynamic performance of the PLL. In our application,

the task is to demodulate the FM input signal. This signal has certain requirements that we must

meet in order to maintain lock under the whole range of operation.

The requirements for the PLL to work with random FM signal is based on the statistical

variation in frequency of the FM signal. The derivation is quite lengthy and not really related,

thus, we only present the final results that are used to design the PLL. More details can be found

on reference materials.


As stated before, the desired characteristic for the PLL loop filter is given by the transfer

function of a PI compensator, which is rearranged as the following

𝐻 𝑠 = 𝐾ℎ

𝑠 + 𝜔2

𝑠

In which

𝐾ℎ is the high frequency gain of the filter

𝜔2 is the zero frequency of the filter

As we know, the lock range of the PLL is directly related to the loop gain.

𝐾 = 𝐾𝑑𝐾ℎ𝐾𝑜

This value depends on the conversion gain of the PD, the sensitivity of the VCO. These two

values are somewhat “fixed” and not easy to change. The only way is to change the loop gain is

to modify the loop filter gain (which is very easy to change).

However, before modifying the value of 𝐾ℎ , we must consider the effect of it on the

demodulation process, so that we know how to choose a correct value for it.

The value of the loop gain related to the bandwidth of the PLL as well as the lock-in range of

the PLL.

In terms of bandwidth, the higher the bandwidth the faster the input can change. On the other

hand, making the bandwidth too large is undesirable because it makes the PLL less selective and

more noisy.

Remember that one of the main characteristics of the PLL is its ability to extract signals from

a noisy background. A narrow bandwidth improves the discrimination ability of the PLL.

Clearly, the tracking range and SNR improvement impose contradictory conditions on the

bandwidth requirements of the PLL. The choice of the PLL bandwidth is the most important

design criterion for a PLL. Based on the application, the designer must weigh the importance of

tracking range and signal selectivity/noise rejection.


For an FM signal the frequency deviation ∆𝜔𝑖 corresponds to the instantaneous amplitude of

the modulating signal (i.e. the „music‟). Assuming a Gaussian distribution of the amplitude of the

modulating signal, we‟ll define the maximum amplitude as that value that is exceeded only

0.05% of the time. Remember that in a Gaussian distribution we have no limit on the actual

maximum value. We do have a predictable low probability for values with a large deviation from

the average. Using the 0.05% constraint above, normal distribution tables show that in that case

∆𝜔𝑖𝑚𝑎𝑥 = 3.5 × ∆𝜔𝑖𝑟𝑚𝑠

The maximum frequency deviation, ∆𝑓𝑖𝑚𝑎𝑥 , is dictated by FCC rules to be 75 kHz.

The calculation of the bandwidth characteristics required for the demodulation of a true

(random) FM signal, involve statistics and probability theory, which are beyond the scope of this

project. We will take the results at face value. The interested reader is referred to the literature

references.

For a random FM signal the frequency deviation from the carrier and the loop bandwidth

have to satisfy either one of the following two relationships

∆𝝎𝒊𝒓𝒎𝒔 ≤ 𝟑𝝎𝑳𝝎𝟐

𝟕𝝅𝑩𝒎

∆𝝎𝒊𝒓𝒎𝒔 ≤𝝎𝑳

𝟑.𝟓

where 𝜔2 is the zero of the LF filter and 𝐵𝑚 the bandwidth (in Hz) of the modulating signal.

The parameter 𝜔𝐿 is the lock range of the PLL and for an EXOR type phase detector is given by

𝝎𝑳 =𝝅

𝟐𝑲

Using these equations and some parameter of the FM signal, we will find the gain and the

zero frequency of our loop filter.

Consider the first condition:

∆𝜔𝑖𝑟𝑚𝑠 ≤ 3𝜔𝐿𝜔2

7𝜋𝐵𝑚


𝐵𝑚 : bandwidth of the modulating signal; in our case, 𝐵𝑚 = 53𝑘𝐻𝑧

∆𝜔𝑖𝑚𝑎𝑥 : maximum frequency deviation, ∆𝜔𝑖𝑚𝑎𝑥 = 2𝜋∆𝑓𝑖𝑚𝑎𝑥 ; ∆𝑓𝑖𝑚𝑎𝑥 = 75𝑘𝐻𝑧 (dictated by

FCC rules)

𝜔2: zero of the LF filter; for a maximally flat response, 𝜔2 is set to be equal to 𝐾/4

𝜔𝐿 : the lock-in frequency, which is the maximum step change in frequency that the PLL still

stays in lock.

Use these values, we now find the appropriate value for 𝐾ℎ , which is the designed parameter

for the LF.

2𝜋∆𝑓𝑖𝑚𝑎𝑥

3.5≤

3 ×𝜋2 𝐾 × 𝐾/4

7𝜋𝐵𝑚

𝐾 ≥ 2𝜋∆𝑓𝑖𝑚𝑎𝑥

3.5×

4 × 7𝜋𝐵𝑚

3 ×𝜋2

= 480,328.3𝑠𝑒𝑐−1

Consider the second condition:

∆𝜔𝑖𝑟𝑚𝑠 ≤𝜔𝐿

3.5

2𝜋∆𝑓𝑖𝑚𝑎𝑥

3.5≤

𝜋2 𝐾

3.5

𝐾 ≥ 4∆𝑓𝑖𝑚𝑎𝑥 = 300,000𝑠𝑒𝑐−1

𝐾 ≥ 480,000𝑠𝑒𝑐−1 to satisfy both conditions.

𝐾ℎ =𝐾

𝐾𝑑𝐾𝑜=

480,000

0.63 × 2𝜋 × 75𝑘= 1.62

For the FM demodulation application, the PLL loop gain and loop filter are chosen to provide

a flat frequency response, and both the lock range and capture range are made significantly larger

than the input FM signal frequency deviation. So, we choose 𝐾ℎ = 5 to ensure it can capture the

FM signal.

𝜔2 =𝐾

4=

0.63 × 2𝜋 × 75𝑘 × 5

4= 371 𝑘𝑟𝑎𝑑/𝑠𝑒𝑐


Use the active filter topology

𝐾ℎ =𝑅2

𝑅1, 𝜔2 =

1

𝑅2𝐶

Choose 𝑹𝟏 = 𝟏𝟎𝒌Ω,𝑹𝟐 = 𝟓𝟎𝒌Ω,𝑪 = 𝟓𝟒𝒑𝑭

The implementation of the above design both with the ideal op-amp and our gain block is

shown in Figure VI.3. The frequency response of the ideal op-amp loop filter and our gain block

loop filter are compared in Figure VI.4

(a)

(b)

Figure VI.3 – Active loop filter

(a) Ideal op-amp

(b) Our designed gain-block


(a)

(b)

Figure VI.4 – Frequency response of loop filter

(a) Ideal op-amp

(b) Our designed gain-block

We can see from the ideal op-amp implementation of the loop filter that the high frequency

gain is approximately 5 (14 dB), the zero frequency is about 60kHz (371 𝑘𝑟𝑎𝑑/𝑠𝑒𝑐).

The result from the ideal op-amp is exactly the same as what we designed. However, the

response of the loop filter implemented with our gain block is so different from what we

expected.


The reason is that we do not balance the impedance between the two inputs of the gain block.

The inverting input sees the 10k resistor, while the non-inverting input is grounded.

To solve this problem, we put a terminated resistor at the non-inverting input as shown in

Figure VI.5.

Figure VI.5 - Loop filter with terminating resistor

The improved response of the loop filter using our gain block is shown in Figure VI.6. We

can notice that this response is exactly the same as the response of the ideal op-amp loop filter

(in Figure VI.4 (a))

Figure VI.6 - Frequency response of loop filter with terminating resistor


The filter in Figure VI.5 has a single input, this configuration will be used to implement the

fully – differential loop filter (see Appendix 3) where we keep the differential signals all the way

through (duplicate loop filter).

For the “single-ended” PLL, we need to convert the differential outputs from the phase-

detector to a single control signal to feed into the VCO.

To accomplish this, we make use of the “subtracting nature” of our gain block to perform the

filtering on the difference between the two input signals. To do that, we replicate the RC network

at both inputs, the circuit is shown in Figure VI.7

Figure VI.7 - Loop filter using two inputs


Figure VI.8 - Frequency response of the loop filter using two inputs

As we can see in Figure VI.8, the frequency response of the loop filter using two inputs of

the gain block is also the same as with single input. The difference is that now we filter the

differential signal between the two inputs.

In the introduction of the loop filter design, we know that the loop filter is the key component

in the PLL that control all the dynamic of the system. We are now going to verify that with our

designed loop filter.

In the following simulation, we will use the loop filter based on our actual gain block (see

Appendix 2 for characteristics of this gain block). However, the rest of the loop will be the

abstract model or the macro model. The reason is that some of the dynamic characteristics of the

loop cannot be verify with the transistor – level model. Moreover, it is much quicker to do this

with the high – level models than with the device model.

The very first thing that we want to verify is the frequency response of the loop, because it is

related to the stability of the system.

By saying frequency response, we do not mean the frequency of the voltage. Because this is

the phase (frequency) locked loop, the object that it operates on is the phase (frequency). This

phase (frequency), however, is modulated by another frequency. This modulating frequency is

what we mention in the frequency response of the PLL.


The fact that this is a feedback system bring us the issue of instability. An improperly

designed loop filter can make the whole system unstable.

To verify that our system is stable, we will use the phase – margin and Nyquist criteria to

assess the stability. To use these criterion, we must see the frequency response of the loop-gain.

In our simulation, we both look at the closed-loop gain and the loop-gain responses of the PLL.

The simulation circuits are shown in Figure VI.9.

(a)

(b)

Figure VI.9 – Simulation circuits: (a) closed-loop gain; (b) loop gain

By breaking the loop, we can see the frequency response of the loop-gain with is shown in

Figure VI.10


Figure VI.10 - Frequency response of the loop gain

We can see from the loop-gain frequency response that the phase margin is about 80𝑜 . This

means that the system is stable. The gain margin is about 60dB. These two figures of the phase

and gain margin are really good for the performance of the system.

To make a double – check, we draw the Nyquist plot of the loop-gain. This is shown in

Figure VI.11

The Nyquist plot does not encircle the -1 point, so the system is stable.

Figure VI.11 - Nyquist plot of the system

The closed-loop frequency response is shown in Figure VI.12


We can see that by choosing the zero frequency much less than the bandwidth, we get a

critically damped response, where the amount of peaking is negligible (maximally flat). This flat

frequency response is very important for our FM demodulation application, where the peaking is

directly related to the distortion of the recovered signal.

One thing to note from the response is that the cut-off frequency is about 200kHz.

In our design, we use the loop-gain 𝐾 = 𝐾𝑑𝐾ℎ𝐾𝑜 as an approximation for the bandwidth of

the system.

This loop gain 𝐾 is designed to be equal to 0.63 × 2𝜋 × 75𝑘 × 5 =1484 .4𝑘𝑟𝑎𝑑

𝑠=

236.25𝑘𝐻𝑧.

As the simulation shown, this is really a good approximation for the bandwidth of the

system. (other approximations are the natural frequency 𝜔𝑛 , noise bandwidth 𝐵𝐿, 3-dB

bandwidth 𝜔3𝑑𝐵 )

All of these approximations have their own advantages and disadvantages, interested reader

can find more explanations and comparison of these in reference material. In general, the loop

gain K is the most widely used indicator for the bandwidth of the system.

Figure VI.12 - Frequency response of the closed loop gain


One more response we get from the above simulation is the error response of the system.

This response is shown in Figure V.13

Figure VI.13 - Response of the error signal

At the low-frequency, the high gain in the system maintain good feedback, and therefore the

error signal is small. When the frequency goes up, the gain of the system goes down, making the

feedback less effective. At some point, the gain disappears, and essentially no feedback presents

in the system, the error signal follows the input signal.

Besides shaping the frequency response of the loop, the loop filter also determines the lock

range and capture range of the PLL.

The idea about the lock range and the capture range is already introduced in previous

sections. To verify it, we do a frequency sweep and see how the PLL tracks the changing input

frequency. The simulation circuit is shown in Figure VI.14.


Figure VI.14 - Simulation circuit for the lock range and capture range

The result is shown in Figure VI.15

Figure VI.15 - Simulation result for the lock range and capture range

As we can see in the result, when the input frequency is too far from the center frequency, the

VCO oscillates around its free-running frequency. When the input frequency approaches the

center frequency, the oscillation frequency of the frequency output of the VCO decreases. At

some point, the frequency of VCO tracks the input frequency. At this point, we have a locked

condition. The PLL maintains locked in a certain range of input frequency.


The lock range and capture range are:

(refer to the definition of these range in the discussion about simulation models)

Lock range: 10.5071MHz - 10.9092MHz

Capture range: 10.5307MHz - 10.8871MHz

As we mention in the effect of the PI compensator, one could expect that the lock range to be

infinite due to the fact that the phase error is zero. However, the non-linear behavior of our gain

block limits the lock range. Obviously, the controlled voltage getting from the loop filter cannot

be higher than the supply voltage.

In our case, the range is still smaller, because our gain block cannot go from rail-to-rail. The

characteristics of our gain block in Appendix 2 show that the maximum output voltage of our

gain block is from -2.5 → 2.7V.

The maximum frequency deviation that we can expect from the VCO is: −2.5 × 75𝑘; 2.7 ×

75𝑘 = −187.5𝑘𝐻𝑧; 202.5𝑘𝐻𝑧.

The expected lock range is 10.51MHz – 10.90MHz.

Comparing this expected value with the simulation value, we can see that they agree with

each other.

In this simulation and calculation, we assume that the maximum output voltage of the gain

block dictates the maximum frequency deviation. In fact, the linear range of the VCO is also

critical to the lock range. In most cases, this linear range determines the actual lock range.

About the capture range, there is no explicit relationship between this range and the lock

range. But in general, this range is less than the lock range as shown in the simulation result.

One last simulation that we will do to verify the performance of the system with this loop

filter is to look at the response of the system to a step change in frequency.

The simulation circuit is shown in Figure VI.16, where we apply a step in controlled voltage

of the input VCO that will cause a step in frequency.


Figure VI.16 - Simulation circuit for the step response

The output from the output filter is shown in Figure VI.17. We also measure the average

error voltage from the phase detector. This is shown in Figure VI.18. We can see that this error

instantaneously goes up to response to the sudden change of input frequency. Then, the error

signal decreases as the integrator comes into place and produces the needed control signal.

Figure VI.17 - Step response of the PLL


Figure VI.18 - Error signal for the step response

To make sense from the simulation results, we are going to put the mathematical descriptions

of the PLL system into MATLAB. Then, we will compare the response from the mathematical

model and the Spice result.

The linear model of the PLL that we implemented in Figure VI.16 is shown in Figure VI.19.

In this linear model, we replace the loop filter with its transfer function. The step and error

responses are shown in Figure VI.20 and Figure VI.21, respectively.

Figure VI.19 – Matlab linear model of PLL

Ko Ko Kd F(s)

LPF(s)


Figure VI.20 - Step response of the linear model

Figure VI.21 - Error response of the linear model


The effect of the integrator can be noticed in the error response, where the error is brought

back to zero after a transient time. This zero error is required to maintain wide lock range.

The step response getting from MATLAB based on the linear model is quite similar to the

result from Spice: the settling time is about 20µs, there is overshoot in the response, etc.

However, the two result is not quite close as we expected. Despite the non-linear nature of

the capturing process, when the PLL stays in lock, one could expect a high linearity in the

system.

One of the major thing that we approximate in the transfer function of the loop filter is that

we put an ideal integrator into the transfer function. In reality, an ideal integrator cannot be

realized. An unintended pole is always present in the system. To see this pole, we extend the

bode plot of the loop filter to the low frequency region.

Figure VI.22 – Frequency response of the loop filter (low frequency)

We can see that, the loop filter indeed has an unintended pole at the frequency of about

762Hz. This is what we expected because the open-loop gain of our gain block is only about 600

(55dB), thus, the response cannot go above this maximum gain.

Taking this into account, we modify the linear model, and the MATLAB result is shown in

Figure VI.23.


Figure VI.23 - Step response of the modified linear model

To see the effect of including the low-frequency pole into the linear model, we make a

simple comparisons as following

Ideal integrator model Low-frequency pole

model Spice

Peak value 1.4 1.35 1.32

Undershoot 0.15 0.1 0.1

The above MATLAB simulation is only intended to give us a basic idea of the mathematical

model of the PLL. Using this model, we can extend our design methodology, and apply control

theory to optimize the dynamic performance of the system. This topic is too broad and definitely

cannot be cover in this project report. The reference materials of this project give more

information about this.

Next, we move on to the next component in the loop – the voltage controlled oscillator.

VCO ECE323 Project – Design of a PLL Based FM Demodulator Page 71

VII. Voltage controlled oscillator design

1. Operation of emitter-coupled VCO

First, consider the circuit in Figure VII.1:

Figure VII.1: General circuit for emitter-coupled VCO

Assume that Q1 is off and Q2 is on. We have the circuit as shown in Figure VII.2.

We will choose R so that the voltage drop across R is large enough to turn on diode Q6. So,

we have 𝑉𝐵 𝑄4 = 𝑉𝑐𝑐 − 𝑉𝐵𝐸 , and 𝑉𝐸 𝑄4 = 𝑉𝑐𝑐 − 2𝑉𝐵𝐸 . Therefore, 𝑉𝐵 𝑄1 = 𝑉𝑐𝑐 − 2𝑉𝐵𝐸 . If the

base current of Q3 is neglected, we will have 𝑉𝐵 𝑄3 = 𝑉𝑐𝑐 and 𝑉𝐸 𝑄3 = 𝑉𝑐𝑐 − 𝑉𝐵𝐸 . Thus

𝑉𝐸 𝑄2 = 𝑉𝑐𝑐 − 2𝑉𝐵𝐸 . Since Q1 is off, the current I1 is charging the capacitor so that the emitter of

Q1 is becoming more negative. When 𝑉𝐸 𝑄1 = 𝑉𝑐𝑐 − 3𝑉𝐵𝐸 , Q1 is turned on.

When Q1 is on, Q5 is turned on by the collector current of Q1. As the result, the base of Q3

moves in the negative direction by one VBE drop, causing the base of Q2 to move in the negative

direction by one VBE drop. Q2 will be off, causing the base of Q1 to move positive by one VBE


drop because Q6 is also turned off. Therefore, we have one VBE drop between the emitter and the

base of Q2 because the voltage on the capacitor cannot change instantaneously. This makes Q2

reverse-biased.

Figure VII.2: Equivalent circuit during one haft-cycle

Current I1 must now charge the capacitor voltage in the negative direction by an amount

equal to two VBE drops before the circuit switches back gain. Because the circuit is symmetrical,

the haft period is given by the time required to charge the capacitor. So we have: 𝑇

2=

𝑄

𝐼1=

𝑄

𝐼𝐶.

Where 𝑄 = 𝐶∆𝑉 = 2𝐶𝑉𝐵𝐸 is the charge on capacitor. So the frequency of the oscillator is:

𝑓 =1

𝑇=

𝐼𝐶

4𝐶𝑉𝐵𝐸 (VII.1)

2. Design of emitter-coupled VCO

The first step in the design project, we have to design an emitter-coupled VCO as shown in

Figure VI.3. The circuit needs to have an oscillation frequency of 10.7MHz when Vc = Vb, and a

sensitivity of 75KHz/V, i.e., when Vc – Vb changes 1V, the central frequency changes 75KHz.


Figure VII.3: Schematic for the emitter-coupled VCO

a. Circuit with ideal current source

First, to keep the circuit simple, instead of using the real current source, we use the ideal

current source that is flowing into R1, R2 for our circuit. We choose the current flowing across

the capacitor IC = 1m𝐴. Therefore, the ideal current source is I1 = 4mA. Our schematic is shown

in Figure VII.4:


Figure VII.4: Circuit with ideal current source

From equation (VII.1) we have the formula for calculating the frequency:

f =IC

4CVBE

When Vc = Vb = 0V, we choose the current flowing across the capacitor 1m𝐴, and assume

that VBE=0.75V. So the capacitor is:

𝐶 =𝐼𝐶

4𝑓𝑉𝐵𝐸=

1𝑚𝐴

4 × 10.7𝑀𝐻𝑧 × .75𝑉= 31.153𝑝𝐹

Simulating the circuit, we get the frequency of 12675.4 KHz. The result is too far away from

the central frequency of 10.7MHz. This is because we assume the wrong value for VBE. Now, we

recalculate VBE.


With C=31.153𝑝𝐹, f=12675.4 KHz, 𝐼𝐶 = 1𝑚𝐴:

𝑉𝐵𝐸 =𝐼𝐶

4𝑓𝐶=

1𝑚𝐴

4 × 12675.4𝐾𝐻𝑧 × 31.153𝑝𝐹= 0.633𝑉

Now, with VBE = 0.633V, IC= 1m𝐴, we recalculate C to meet the requirement of central

frequency of 10.7MHz:

𝐶 =𝐼𝐶

4𝑓𝑉𝐵𝐸=

1𝑚𝐴

4 × 10.7𝑀𝐻𝑧 × 0.633𝑉= 37.16𝑝𝐹

With this modified value of C, we simulate the circuit. We get the central frequency of

10702.1 KHz. So with IC = 1m𝐴, C = 37.16pF and VBE = 0.633V, our circuit oscillates with the

frequency of 10702.1 KHz @ Vc= Vb =0V.

Now, we will calculate the other circuit elements to achieve the sensitivity of 75 KHz/V.

Using KVL:

Vc - VBE - IR1×R1 = Vb - VBE – IR2×R2 (VII.2)

Vc – Vb = IR1×R1 – IR2R2 (VII.3)

We have: I1=IR1+IR2 (VII.4)

Vc – Vb = IR1×R1 – (I1 - IR1) ×R2 (VII.5)

Vc – Vb + I1×R2 = IR1×(R1+R2) (VII.6)

To be symmetrical, we choose R1=R2.

Vc – Vb + I1×R1 = IR1×2R1 (VII.7)

𝐼𝑅1 =𝑉𝑐−𝑉𝑏

2𝑅1+

𝐼1

2= 2𝐼𝐶 (VII.8)

𝑓 =𝐼𝐶

4𝐶𝑉𝐵𝐸=

𝑉𝑐−𝑉𝑏

16𝐶𝑅1𝑉𝐵𝐸+

𝐼1

16𝐶𝑉𝐵𝐸 (VI.9)

∆𝑓

∆𝑉=

1

16𝐶𝑅1𝑉𝐵𝐸 (VII.10)


∆𝑓

∆𝑉=

75𝐾𝐻𝑧

𝑉→ 𝑅1 = 𝑅2 =

1

16 × 37.16𝑝𝐹 × 0.633𝑉 ×75𝐾𝐻𝑧

𝑉

= 35.43𝐾Ω

With 𝑅1 = 𝑅2 = 35.43𝐾Ω we simulate our circuit. We get the following result:

@ Vb = 0V, Vc = 0V: f = 10699.7 KHz

@ Vb = 0, Vc = 1V: f = 10772.7 KHz ∆𝑓

∆𝑉=

73𝐾𝐻𝑧

𝑉

@ Vb = 0, Vc = -1V: f = 10623.7 KHz ∆𝑓

∆𝑉=

76𝐾𝐻𝑧

𝑉

Up to this point, by using the ideal current source, we have the central frequency of =

10699.7 KHz, and the sensitivity is 73 KHz/V for the positive side and 76 KHz/V for the

negative side.

b. Circuit with real current source

Now, we think about applying a real current source that flows into R1 and R2.

Here, the problem is that, if Vb = Vc: 𝑉𝑅1 = 𝑉𝑅2 =𝐼1

2× 𝑅2 =

4𝑚𝐴

2× 35.43𝐾 = 70.86𝑉!!!

Since we use the supply voltage of ±5V, the voltage across R1 and R2 is too much above the

permitted range. So if we use the real current source that creates 4mA to supply current for R1

and R2 branches, we cannot do that with the power supply of ±5V.

To solve this problem, first thinking in a simple way that does not change our circuit very

much, we will reduce value of R1 and R2 to make the voltage dropped across these resistors

lower. For example, we choose the new value of resistor just half of the old value. However, to

keep the sensitivity the same, we also have to double capacitance since we have ∆𝑓

∆𝑉=

1

16𝐶𝑅1𝑉𝐵𝐸 .

But 𝐶 =𝐼𝐶

4𝑓𝑉𝐵𝐸 , so to keep the central frequency unchanged, we have to double 𝐼𝐶 . It means that

the currents through R1 and R2 are doubled also. Therefore, the voltage dropped across R1 and

R2 is still the same. So we cannot solve the problem by simply changing the values of capacitor

and resistors R1, R2.


Now, think about this problem again. We need to reduce the voltage across R1, R2. If we

cannot reduce the resistance, we can reduce the currents flowing through R1, R2. But we also

need the total current flowing into U5 and U6 to be the same 2mA. Therefore, we come up with

the solution of splitting the current source I1 into two current sources I1 and I2 as shown in Figure

VII.5.

With this solution, the voltage across R1 and R2 are just 0.1mA×35.43KΩ = 3.543V. This

value is in the acceptable range. Therefore, our solution can work in this case.

To be sure that the additional current source I2 does not affect the sensitivity, we re-derive

the equation to calculate the sensitivity. From equation (VII.7) we have: 𝐼𝑅1 =𝑉𝑐−𝑉𝑏

2𝑅1+

𝐼1

2

Since 𝐼𝐶 =𝐼𝑅1 +𝐼2

2 (VII.11)

𝑓 =𝐼𝐶

4𝐶𝑉𝐵𝐸=

𝐼𝑅1 +𝐼2

8𝐶𝑉𝐵𝐸=

𝑉𝑐−𝑉𝑏

16𝐶𝑅1𝑉𝐵𝐸+

1

8𝐶𝑉𝐵𝐸(𝐼2 +

𝐼1

2) (VII.12)

∆𝑓

∆𝑉=

1

16𝐶𝑅1𝑉𝐵𝐸 (VII.13)

From equation (VII.13), we see that the sensitivity is still the same as when we use only

current source I1. In this case, our solution works. We can use current source I2 to adjust the

central frequency, and use R1 and R2 to adjust the sensitivity. We have freedom to adjust what

we want.

Figure VII.5: Circuit with two ideal current sources I1 and I2


Now, we are successful with the ideal current source model. Let’s replace the ideal current

source with the real current source.

First, in our circuit, we want to keep the collector currents of U9 and U10 stable. If these

currents change, VBE in equation (VII.10) will change slightly. If VBE changes only some tens of

milivolts, we will get a change of several tens of KHz in frequency.

To do this, we make I1, I2 are independent of the current source of U11. This is the simplest

way to control our central frequency and we do not affect the collector currents of U9 and U10.

We use just two additional current sources. However, this solution required some more

components. The circuit is shown in Figure VII.6.

Figure VII.6: Current sources I1 and I2 are independent of U11


We need to calculate Rref1 and Rref2 to make I1 = 0.2mA, and I2 = 1.9mA. We have:

𝐼2 = 𝐼𝑟𝑒𝑓2

1 +𝑉𝐶𝐸(𝑈17)

𝑉𝐴

1 +𝑉𝐶𝐸(𝑈18)

𝑉𝐴+

2𝛽

= 𝐼𝑟𝑒𝑓2

1 +𝑉𝑐 − 𝑉𝐵𝐸 − 𝑉𝑒𝑒

𝑉𝐴

1 +𝑉𝐵𝐸

𝑉𝐴+

2𝛽

𝐼1 = 𝐼𝑟𝑒𝑓1

1 +𝑉𝐶𝐸(𝑈15)

𝑉𝐴

1 +𝑉𝐶𝐸(𝑈16)

𝑉𝐴+

2𝛽

= 𝐼𝑟𝑒𝑓1

1 +𝑉𝑐 − 𝑉𝐵𝐸 − 0.5𝐼1 × 𝑅1 − 𝑉𝑒𝑒

𝑉𝐴

1 +𝑉𝐵𝐸

𝑉𝐴+

2𝛽

From equations (VII.14) and (VII.15), we see that I1 and I2 will change if we change Vc.

Therefore, the central frequency will change. So, to keep the central frequency unchanged, we

decide to connect Vc to ground, and we will adjust Vb to control the frequency. Because of this,

when we set Vb = -1V, for example, it means that Vc-Vb = 1V, and our frequency should increase

75 KHz.

With Vc = 0V, VBE = 0.633V, VA = 29.76V, β = 180

(IV.2.13) 𝐼2 = 𝐼𝑟𝑒𝑓2 × 1.11077 (VII.17)

𝐼2 = 1.9𝑚A → 𝐼𝑟𝑒𝑓2 = 1.7105𝑚A → 𝑅𝑟𝑒𝑓2 =𝑉𝑐𝑐 −𝑉𝑒𝑒 −𝑉𝐵𝐸

𝐼𝑟𝑒𝑓 2=

5𝑉+5𝑉−0.633𝑉

1.7105𝑚A= 5.46𝐾Ω

Simulating this current source I2, we have I2 = 1.9mA. This value is the desired value we

want.

(IV.2.14) 𝐼1 = 𝐼𝑟𝑒𝑓1 ×1+

0−0.633−0.5𝐼1×35.43𝐾+5

31.515

1+0.633

31.515+

2

180

(VII.18)

Substituting I1 = 0.2mA into equation (VII.18), we get:

𝐼𝑟𝑒𝑓1 = 0.2𝑚A → 𝑅𝑟𝑒𝑓 1 =𝑉𝑐𝑐 − 𝑉𝑒𝑒 − 𝑉𝐵𝐸

𝐼𝑟𝑒𝑓1=

5𝑉 + 5𝑉 − 0.633𝑉

0.2𝑚A= 46.84𝐾Ω

(VII.14)

(VII.15)


Simulating this current source I1, we have I1 = 0.2mA. This value is the desired value we

want.

Simulating the circuit, we get the results:

@ Vb = 0V: f = 10696 KHz

@ Vb = -1V: f = 10757 KHz ∆𝑓

∆𝑉=

61𝐾𝐻𝑧

𝑉

@ Vb = 1V: f = 10630.5 KHz ∆𝑓

∆𝑉=

65.5𝐾𝐻𝑧

𝑉

We change R1 and R2 to meet the requirement of ∆𝑓

∆𝑉=

75𝐾𝐻𝑧

𝑉

𝑅1 = 𝑅2 = 46.84𝐾 ×

65.5 + 612 𝐾𝐻𝑧/𝑉

75𝐾𝐻𝑧/𝑉= 29.88𝐾Ω

Simulating the circuit again, we get the results:

@ Vb = 0V: f = 10705.4 KHz

@ Vb = -1V: f = 10627 KHz ∆𝑓

∆𝑉=

78.4𝐾𝐻𝑧

𝑉

@ Vb = 1V: f = 10778.8 KHz ∆𝑓

∆𝑉=

73.4𝐾𝐻𝑧

𝑉

The central frequency and the sensitivity are nearly the same our desired value.

We have had the circuit that meets our design goal. We continue to replace all the resistors in

our circuit with the resistor value in CPI library. The circuit in Figure VII.7 is our final circuit

with all components in CPI library.


Figure VII.7: Complete circuit for emitter-coupled VCO with cpi devices

Simulating this complete circuit, we get the output waveform as shown in Figure VI.8.

Figure VII.8: output waveform of VCO


From the waveform in Figure VII.8, we see that the output voltage is approximately ±VBE

square wave centered around zero.

Now, we will verify the central frequency and the slope of our circuit by using the frequency

measurement block (that we used in ECE322 project).

Figure VII.9: output waveform of VCO with Vb = 1V,0V,-1V

Figure VII.9 shows us the output voltages corresponding to each of the oscillation

frequencies. We step the input voltages from -1V to 1V with the step of 1V. From the waveform,

we get the following information:

@ vb=0V: V(f)=10.698MV f=10.698MHz

@ vb=1V: V(f)=10.623MV f=10.623MHz ∆𝑓

∆𝑉=

75𝐾𝐻𝑧

𝑉

@ vb=0V: V(f)=10.773MV f=10.773MHz ∆𝑓

∆𝑉=

75𝐾𝐻𝑧

𝑉

The central frequency and the sensitivity are correct.

Figure VII.10 shows the waveforms within the emitter-coupled multi-vibrator.


Figure VII.10: Waveforms within the emitter-coupled multi-vibrator

The output waveforms of outa, outb, voltage at the emitter of Q2, voltage across the

capacitor, and the [V(outb)-V(outa)] voltage are presented in Figure VII.10.

From that figure, we can see that the operation of the circuit is exactly as what we expect.

Now, we vary the (Vctl –Vb) from -3 to 3 in the step of 0.5V to verify the output frequency

of our designed VCO. Figure VII.11 shows the output waveform when we use the frequency

measure block to measure the output frequency.


Figure VII.11: Output frequencies with input voltage from -3V to 3V

From figure VII.11, we have the following table that shows the frequency versus the input

voltage:

Vctl –Vb [V] Frequency (MHz)

3 10.8872

2.5 10.879

2 10.8481

1.5 10.8106

1 10.7731

0.5 10.7355

0 10.698

-0.5 10.6604

-1 10.6227

-1.5 10.5852

-2 10.5474

-2.5 10.5098

-3 10.472


The plot of frequency vs. (Vctl –Vb) is shown in Figure VII.12:

Figure VII.12: plot of linear range of our designed VCO

From Figure VII.12, we can see that the output frequency increases linearly with (Vctl - Vb) in

the range -32.5V.

This result is what we expected from the general equation of the VCO: f =f 0±KV c

Since in our project, we just use inputs of sine waves with amplitude about 1V, and the

linearity of the VCO is directly related to the linearity of the FM demodulated signal, we now

will check the smaller range of linearity of our VCO with the finer step. We have the waveform

as shown in figure VII.13. Again, the figure is reversed because we applied the signal to Vb, not

Vctl.


Figure VII.13: plot of linear range of our designed VCO

The linearity is very good. So we can use this characteristic of our VCO to establish the

designed linearity of our FM demodulator.

3. Verification of the VCO’s operation

Now, we will verify the operation of our VCO. We want to know how it works when we put

it in a PLL. Therefore, we will use the behavioral level of the PLL which is available in the

library of LTspice. We just replace the ideal VCO block with our VCO block as shown in figure

VII.13.

Figure VII.14: Behavioral level of PLL with our designed VCO


As we can see in figure VII.14, the block named VCO_design is our real VCO. Here, one

important notice about this block is the behavioral source B2. We assign the value V=-V(A) for

it. When we designed our VCO, we grounded the input vc, and we applied the signal into the

input vb. Therefore, the control voltage is actually reversed. However, we use the ideal VCO

block U2 to generate the FM signal. This block is ideal, so the control voltage for this block is

not reversed. Therefore, to get a match waveform for the input signal and the demodulated

output signal, the input voltage for our real VCO must be reversed as shown in the schematic.

Running the simulation, we get the waveform of the reference signal and the demodulated

output signal as shown in figure VII.15:

Figure VII.15: The input and output waveforms of the PLL with our designed VCO

Next, we will run the FM demodulator with the ideal VCO to check if our designed VCO

works correctly.


Figure VII.16: Behavioral level of PLL with ideal VCO

Figure VII.17: The input and output waveforms of the PLL with the ideal VCO

From figure VII.15 and figure VII.17, we see that the demodulated waveforms have the same

shape as the input waveforms although there are differences in amplitude and phase. Therefore,

our real VCO works fine in the PLL topology.

Next, we will apply more complex reference signal to check if our VCO works fine with

such a complex signal. Similarly, we first run the simulation with our designed VCO, then with

the ideal VCO.


Figure VII.18: Behavioral level of PLL with our designed VCO

Figure VII.19: input and output waveforms of the PLL with our designed VCO


Figure VII.20: Behavioral level of PLL with the ideal VCO

Figure VII.21: input and output waveforms of the PLL with the ideal VCO

From figure VII.19 and figure VII.21, we can see that our designed VCO works very well for

a complex reference signal.

Low-pass Filter ECE323 Project – Design of a PLL Based FM Demodulator Page 91

VIII. Output low-pass filter design

In the FM demodulator circuit, beside a PLL, we need a so-called post detection filter to filter

out the carrier feed through which is present in the error voltage.

The signal from the EX-OR type phase detector is a high frequency signal which has the DC

value reflects the phase error. Thus, the input voltage to the VCO also has this high frequency

signal (≈10.7MHz).

Therefore, we need to filter out the high frequency content in this signal. Before designing

the output low-pass filter, we look at the basic specifications of a low-pass filter shown in Figure

VIII.1.

Figure VIII.1 - Basic specifications for low-pass filter

For our FM demodulator circuit, the pass-band frequency is 80KHz, the stop-band frequency

is 300kHz. This specification is sufficient to remove all the carrier feed through.

One of the considerations in the post detection filter is the phase shift. The reason is that the

input signal may contain multiple frequency signals. If the filter introduces phase shift in the

pass-band, the different amount of phase shift for different frequencies will distort the recovered

signal.


There are basically three ways to deal with this issue:

Make the pass-band wider than the actual bandwidth of the signal, so that the in-band

frequency has little effect of phase shift.

Use the Bessel filter – which has a linear phase shift (which respect to frequency) =>

reserve the shape of the signal.

Add a all-pass filter to correct the phase shift.

The last solution is so complex and is not in the scope of our project. The first two will be

examined in details in this section.

The first solution is to use a normal filter which has a sufficient cut-off frequency to

minimize the phase shift to the pass-band signal.

A well-known filter response that first comes up is the Butterworth response – or the

maximally flat response. The excellent response as well as the ease of implementation make this

type of filter is desirable for most application.

1. Butterworth filter implementation

Due to the high frequency of the carrier (more than 2 decades away from the pass-band of

50kHz,) a second-order Butterworth filter is enough to attenuate this carrier signal.

A Butterworth response is characterize by the Q factor of 2

2. The easiest way to implement

is with a Salen-Key topology.

Salen-key topology with unity gain is shown in Figure VIII.2


Figure VIII.2 - Salen Key low-pass filter topology

The design equation for this topology is:

𝜔𝑜 =1

𝑅1𝑅2𝐶1𝐶2

𝑄 =1

𝑅1𝐶2

𝑅2𝐶1+

𝑅2𝐶2

𝑅1𝐶1

To make a Butterworth response, we must have 𝑄 = 2

2, 𝜔𝑜 = 2𝜋 × 80𝑘, set 𝑅1 = 𝑅2 = 4𝑘 (to

make the design simple and this is the available resistor in CPI library)

→ 𝐶1 = 703.4𝑝𝐹; 𝐶2 = 351.7𝑝𝐹

The complete filter circuit with the CPI library devices and our designed gain block is shown

in Figure VIII.3, the frequency response is shown in Figure VIII.4


Figure VIII.3 - Butterworth low-pass filter

Figure VIII.4 - Frequency response of the Butterworth low-pass filter


The 3-dB cut-off frequency is 81.66kHz, which is nearly exact what we design. The

attenuation at 10MHz (carrier frequency) is in the order of 80dB, this is enough to reject the

carrier signal. However, the group delay is not constant throughout the pass-band. This fact can

affect the output waveform.

Next, we will consider the Bessel filter response which is desirable to reduce waveform

distortion

2. Bessel filter implementation

The Bessel filter has a linear phase shift (constant group delay) that helps to eliminate

waveform distortion.

The drawback of the Bessel filter is that it has less roll-off than Butterworth filter (same

order). Thus, to get the same amount of attenuation, we must design a Bessel filter with higher

order. The roll-off of a Bessel filter and a Butterworth filter is compared in Figure VIII.5

Figure IIIIII.5 - Magnitude response of a Bessel filter (in comparison with a Butterworth

filter)

The linear phase-shift characteristic of the Bessel filter is compared with the ideal filter and

the Butterworth filter in Figure VIII.6


Figure IVII.6 - Relative phase response characteristics of some filter types

The linearity in phase of a Bessel filter is very important when the filter needs to handle

square wave or pulses (contain many frequency components.)

Because a Bessel filter has less roll-off than a Butterworth filter, a higher order filter will be

required to get enough attenuation for out-of-band signal. In our application, we will implement

a cascading Bessel filter. This is realized by cascading two second-order Bessel filter.

The 𝑓𝑜 and Q factor for each stage can be found on standard filter hand book. Part of this

kind of table for Bessel filter response is shown in Table VIII.1.

Table VIII.1 - Normalized Bessel low-pass filter table

Bessel low-pass filter

𝒏 𝑓𝑜1 𝑄1 𝑓𝑜2 𝑄2 𝑓𝑜3 𝑄3

2 1.274 0.577

3 1.453 0.691 1.327

4 1.419 0.522 1.591 0.806

5 1.561 0.564 1.76 0.917 1.507

6 1.606 0.51 1.691 0.611 1.907 1.023


In our application, 𝑓𝑜 = 80 𝑘𝐻𝑧 is the normalized cut-off frequency. The cut-off frequency

for each stage can be found from the table as following

𝑓𝑜1 = 1.419𝑓𝑜 = 1.419 × 80𝑘 = 113.52𝑘𝐻𝑧

𝑓𝑜2 = 1.591𝑓𝑜 = 1.591 × 80𝑘 = 127.28𝑘𝐻𝑧

The Q-factor for each stage is also from the table:

𝑄1 = 0.522

𝑄2 = 0.806

Using the same approach (unity gain Salen Key topology), set 𝑅1 = 𝑅2 = 4𝑘

For the first stage:

𝐶1 = 365.92𝑝𝐹

𝐶2 = 335.73𝑝𝐹

For the second stage:

𝐶1 = 503.9𝑝𝐹

𝐶2 = 193.9𝑝𝐹

The complete circuit is shown in Figure VIII.7

Figure VI.7 - Complete circuit for the Bessel filter


The frequency response of the circuit is shown in the Figure VIII.8

Figure VII.8 - Frequency response of the Bessel filter

The last figure is the group delay response. We can see that the Bessel filter gives us a

perfect flat (constant) group delay, which is very important to reduce distortion for a multiple-

frequency signal.

The cut-off frequency is 80.54kHz, pretty close to what we designed, the attenuation at the

carrier frequency is very large (160dB). At 300kHz, the attenuation is 31.8dB. These

characteristics meet the requirements for the post detection filter.

To illustrate the effect of the phase-shift (group delay) on waveform distortion, we compare

the two filter circuits that we designed by a simple simulation.

We apply a square wave to the input of the two filters. The distortion of the two filters is

compared in Figure VIII.9. From that figure, it is obvious that the Bessel filter has less distortion

than the Butterworth filter. Despite the fact that the output is delayed, the Bessel filter keeps the


waveform pretty much the same as the input waveform (because high frequency components are

removed, the corner is rounded-off)

Figure VIII.9 - Waveform distortion comparison between a Bessel filter and a Butterworth

filter

PLL design ECE323 Project – Design of a PLL Based FM Demodulator Page 100

IX. Phase locked loop design and verification

1. Combination of all designed blocks

Up to this point, we have designed all the necessary blocks for our PLL. In this section, we

will combine all our blocks to build a complete PLL circuit.

First, we will summarize the characteristics of our designed blocks.

For the phase detector, we have:

𝐾𝑑 =2

𝜋

𝑉

𝑟𝑎𝑑 , 𝑙𝑖𝑛𝑒𝑎𝑟 𝑟𝑎𝑛𝑔𝑒 𝑖𝑠 𝑓𝑟𝑜𝑚 0 𝑡𝑜 𝜋

For the loop filter, we have:

𝐾𝑕 = 5,𝜔2 = 3.7 × 105 𝑟𝑎𝑑

𝑠𝑒𝑐

For the VCO, we have the central frequency of 10.7MHz, and the sensitivity of 75KHz/V

approximately.

The bandwidth of our design is determined by

𝐾 = 𝐾𝑑 × 𝐾𝐿𝐹 × 𝐾𝑜 =2

𝜋

𝑉

𝑟𝑎𝑑 × 5 × 75

𝐾𝐻𝑧

𝑉 × 2𝜋

𝑟𝑎𝑑

𝑐𝑦𝑐𝑙𝑒 = 1500 × 103(

1

𝑠𝑒𝑐)

→ 𝑏𝑎𝑛𝑤𝑖𝑑𝑡𝑕 = 1500 × 103 𝑟𝑎𝑑

𝑠𝑒𝑐 = 238.7𝐾𝐻𝑧

This bandwidth is confirmed in Figure VI.12 where we plotted the frequency response of the

closed loop gain.

By combining all the necessary blocks together, we get the schematic as shown in figure

IX.1.


Figure IX.1: Demodulation circuits with designed blocks

The circuit in figure IX.1, we use the Laplace model of the low-pass filter. Once our circuit

runs correctly with this ideal Laplace model, we will replace this model with the real low-pass

filter.

Here, one point we must consider is that because our VCO is grounded at Vctl and injected

the control signal at Vb, when we apply 1V into our VCO, it’s actually -1V, and vice versus.

However, the VCO used to generate the input FM signal is the ideal VCO. So, the right output

waveform is the minus sign of the output waveform that we take out from the low-pass filter.

Now, we will simulate the circuit in figure IX.1 with the reference signal of 𝑣𝑟𝑒𝑓 =

sin 106𝐾𝜋𝑡 (𝑉). We have the waveform of the reference signal and the reconstructed signal as

shown in figure IX.2.


Figure IX.2: waveforms of reference signal and reconstructed signal

In figure IX.2, we see that the reconstructed signal has the same shape with the reference

signal. Although the magnitude of the reconstructed signal is a little bit different from that of the

reference signal, it is not important because we can use the amplifier to scale the amplitude of the

reconstructed signal.

Next, we have to check whether the reconstructed signal has the same frequency as the

reference signal or not. To do that, we will use FFT analysis in LTSpice. We have the waveform

as shown in figure IX.3.


Figure IX.3: FFT of reference signal and reconstructed signal

In figure IX.3, we see that the two signals have the same frequency of 53KHz. However, the

reference signal has a very smooth FFT waveform while the reconstructed signal has some

ripples on the FFT waveform. This is because the reference signal is the ideal source consisting

of only the sinusoidal signal with the frequency of 53KHz, but the reconstructed waveform

contains not only the sinusoidal signal with the frequency of 53KHz but also some noise in our

circuit.

The presence of noise is due to the bandwidth of our circuit. Since the noise is mostly at the

high frequency, the bigger the bandwidth is, the more the noise is. Therefore, to reduce the noise,

we have to reduce the bandwidth. However, the bandwidth of our PLL is too low, the tracking

range of our PLL is also too low, and it’s difficult to reconstruct the signal. Therefore, we have

to balance between the noise and the tracking range. Since the noise level of the waveform in

figure IX.3 is not much, we can accept this result.

Now, we will apply more complex waveform into the reference input of our PLL to see if our

circuit can track this waveform. We will use the combination of 2 sinusoidal signals: 50KHz and

10KHz as shown in figure IX.4.


Figure IX.4: Demodulation circuits with signal of 10KHz and 50KHz

Simulating this circuit, we get the waveforms and the FFTs of the reference signal and the

reconstructed signal as shown in figure IX.5 and figure IX.6.

Figure IX.5: waveforms of reference signal and reconstructed signal with the reference

signal of 10KHz and 50KHz


Figure IX.6: FFTs of reference signal and reconstructed signal with the reference signal of

10KHz and 50KHz

From waveforms in figure VII.5, we see that the reconstructed signal tracks the reference

signal. And from the FFTs in figure VII.6, we see clearly 2 frequencies of the signals: 10 KHz

and 50KHz. Here, the same as the previous waveform in figure VII.3, the FFT of reference

signal is smooth and the FFT of reconstructed signal also contain some noise. We accept this

noise level.

2. Circuit with CPI components

We have had our circuit working with the Laplace model of the low-pass filter correctly.

Next, we will replace the Laplace model with the real low-pass filter and all the devices in our

demodulator circuit with CPI devices. The final circuit with CPI devices is shown in figure IX.7.


Figure IX.7: complete circuit with CPI devices

First, we will check this circuit with the reference input of 53KHz sine wave. Simulating this

complete CPI circuit, we get the waveforms as shown in figure IX.8 and IX.9.

Figure IX.8: waveforms of reference signal and reconstructed signal with reference signal

of 53KHz


Figure IX.9: FFTs of reference signal and reconstructed signal with reference signal of

53KHz

From figure IX.8 and IX.9, we see that our circuit works correctly for 53KHz sine wave.

There is some noise in the FFT of the reconstructed signal. However, it is acceptable.

Now, we will continue to check our circuit with the combination of 2 sine waves: 10KHz and

50KHz. Simulating the circuit, we get the waveforms as shown in figure IX.10 and IX.11.


Figure IX.10: waveforms of reference signal and reconstructed signal with the combination

of 50KHz and 10KHz

Figure IX.11: FFTs of reference signal and reconstructed signal with the combination of

50KHz and 10KHz


From figure IX.10 and IX.11, we see that our circuit works very well for combination of

50KHz and 10KHz sine waves. There is a little bit more noise in the FFT of the reconstructed

signal than the case of 53KHz sine wave. However, it is acceptable.

Now we will check the lock range and capture range of our complete circuit. In the loop filter

design, we have found these ranges based on our actual loop filter, but other components in the

loop are only macro models. Now, after finishing all the components, we will verify the

operating ranges of the complete transistor level PLL.

To do this, we will apply the ramp input which is from -3V up to 3V, and then from 3V down

to -3V to find which range of voltage the output can track the input. Our results of simulation are

shown in figure IX.12 and figure IX.13.

Figure IX.12: Output voltage for the ramp input


Figure IX.13: Output voltage for the ramp input

The result is:

The lock range: - 2.6V → 2.9V ⋮ 10.5 MHz → 10.9 MHz

The capture range: -2.4V → 2.5V ⋮ 10.52 MHz → 10.88 MHz

Comparing this result with what we got from the figure VI.15, we see that the lock range and

capture range are identical between the transistor level and macro model. The reason is that the

main limiting factor in this case is the maximum voltage that our gain block can produce (about

±2.5V). The linear range of our designed VCO is larger than this range. Therefore, it does not

limit the ranges of the PLL.

Conclusion ECE323 Project – Design of a PLL Based FM Demodulator Page 111

X. Conclusion

Throughout accomplishing this design project, we have developed a comprehensive

understanding of the basic operation, design process, and characteristics of one of the most

useful analog circuits – phase locked loop circuit. Even though most of the steps we did are done

by simulation with LTSPICE, the exact models in the CPI library give us the real characteristics

of the actual physical devices.

In addition, through solving the problems we encountered during our design process, we

have the opportunity to review and apply our knowledge about analog circuits we have learned

into the real application. Moreover, working through the design process in a systematic way, we

have improved our engineering skills, such as teamwork and problem solving.

References ECE323 Project – Design of a PLL Based FM Demodulator Page 112

XI. References

[1] Halen, Paul Van. "ECE323 Project Handout." FM Based Demodulation, Spring 2010.

[2] Wolaver, Dan H. Phase-Locked Loop Circuit Design. Prentice Hall, 1991.

[3] Gardner, Floyd M. Phaselock Techniques. Wiley-Interscience, 2005.

[4] Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, Robert G.Meyer. Analysis and Design

of Analog Integrated Circuits. New York: J. Wiley and Sons, 2009.

[5] Ogata, Katsuhiko. Modern Control Engineering. Prentice Hall, 2009.

[6] Franco, Sergio. Design with Operational Amplifier and Analog Integrated Circuit.

New York: McGraw-Hill, 2003.

[7] Grebene, Alan B. Bipolar and MOS Analog Integrated Circuit Design. Wiley-

Interscience, 2002.

[8] Egan, William F. Phase-Lock Basics. Wiley-IEEE Press, 2007.

[9] Best, Roland. Phase Locked Loops: Design, Simulation, and Applications. McGraw-

Hill Professional, 2007.

[10] Goldman, Stanley J. Phase-Locked Loops Engineering Handbook for Integrated

Circuits. Artech House, 2007.

[11] Vladimirescu, Andrei. The Spice Book. New York: J. Wiley and Sons, 2010.

Appendix 1 ECE323 Project – Design of a PLL Based FM Demodulator Page 113

XII. Appendixes

1) CPI library devices’ characteristics

1. Resistors

There are two resistors that are available in the CPI library: 250Ω and 4kΩ resistors.

These two resistors are not simply resistors, but include diodes that inherently present

when fabricating these resistors on Silicon substrate.

Figure A.1: CPI resistors symbols

These resistors have three terminals instead of two as normal resistors. The third terminal

is the substrate of the chip. The complete equivalent circuit for this resistor is shown in

Figure A.2.

Figure A.2: Complete circuit of the CPI resistor


In order for these resistors to work properly, these two diodes must be kept at reverse-

biased. Therefore, we must connect this terminal to a higher voltage (Vcc.)

Adding these reverse-biased diodes at the two ends of the resistor is equivalent to adding

two capacitors (depletion capacitors.) Thus, the frequency response of the resistor is also

affected.

For example, we will plot the value of the 250 Ω resistor as a function of frequency.

Figure A.3: Circuit to examine the frequency response of the resistor

Figure A.4: Frequency response of the resistor


As we can see in the figure, the value of the resistor begins to drop down when the

frequency passes 10GHz. However, for most of application, this is not a critical limitation.

2. Transistors

We will examine the characteristics of the wn2 and wn8 npn transistors, as well as the

wp2 pnp transistor in the CPI library. These three transistors are the ones that we use to

implement our circuit.

DC Characteristics

The circuit we use to examine the characteristics is shown in Figure A.3, using a wn2

transistor. The first simulation will be the output characteristic curves, a display of IC versus

VCE for different values of the base current IB.

In the simulation window, choose DC sweep. Select V1 (VCE) for the first source and

specify a linear sweep from 0 to 5 V in steps of 50mV. Select I1 (IB) for the second source

and specify a linear sweep from 1 μA to 10 μA in steps of 1μA.

Run the simulation and select the collector current, Ix(U1:C), to plot.

NOTE: Integrated circuit NPN transistors have four terminals. Besides the standard

collector, base and emitter connections there is also a substrate terminal which needs to be

connected to the most negative voltage in the circuit.


Figure A.5: Circuit for characteristic curve (for npn)

The plot from LTSpice for the DC characteristics of wn2 transistor is:

Figure A.6: The output characteristics of wn2 transistor

Replacing wn2 with wp2 device, we get the following result.

U1wn2I1

0

V1

0

.dc V1 0 5 50m I1 1u 10u 1u

HIEU NGUYEN & THIEN NGUYEN

01/29/2010


Figure A.7: Circuit for characteristic curve (for pnp)

Figure A.8: The output characteristics of wp2 transistor

As we can see from Figure A.6, the DC current gain (βF) of the wn2 device is

approximately 100: IC ≈100IB.

On the other hand, the DC current gain (βF) of the wp2 device is only about 20.


When VCE increases, IC also increases due to the Early effect. This effect is illustrated in

Figure A.9.

Figure A.9: The Early effect

The extrapolation of the characteristics back to the VCE axis gives an intercept VA called

Early voltage. This Early effect is modeled as an output resistance for the transistor.

Next we will look at the input/output characteristics IB and IC versus VBE. One way of

measuring these characteristics (one of several equivalent methods) is shown in Figure A.10.

The B1 device is an arbitrary voltage source. Its value is specified to be equal to the stepped

parameter vcb. (The .step command is entered as a Spice directive). The device currents are a

function of the base-collector voltage. The DC sweep will be executed multiple times for

different values of vcb. Enter the dc sweep as shown in Figure A.10. Also add a spice

directive for the .step command.

Figure A.10: Circuit for measuring IB and IC versus VBE


As we can see from Figure A.11, the base current increases exponentially when the base-

emitter voltage is more than the “on” voltage of the p-n junction. For this wn2 integrated

transistor device, the VBE that forward-biases the B-E junction is about 0.9V (slightly higher

than discrete bipolar transistor.)

One more thing that we can notice from Figure A.11 is that IB decreases when VCB

increases. As we know, the collector-base junction needs to be reverse-biased in order for the

BJT to be in the forward-active region. This VCB voltage reverse-biases the junction. As

VCB goes up, the depletion region at the base-collector junction becomes wider. That makes

the base becomes narrower, and decreases the recombination current in the base area.

Therefore, the base current decreases as VCB increases.

Figure A.11: Input characteristics: IB = f(VBE)

Now we examine the current gain of the device by plotting the current gain

Ix(U1:C)/Ix(U1:B) as a function of the collector current.

Use the right button in the plot pane to “Add Trace” and add the expression

Ix(U1:C)/Ix(U1:B). This plots the current gain of the transistor. Left-click on the horizontal

legend and change the quantity to Ix(U1:C) and change the scale to logarithmic.

VC

B =

0V

V

CB

= 2

V

VC

B =

4V


The plot for the wn2 device is shown in Figure A.12. Then we replace the wn2 device

with a wn8 device and perform the simulations again.

From Figure A.12 and Figure A.13, we see that the wn2 and wn8 devices have a very

similar gain. However, the collector current at which the gain is maximum is different. The

wn2 device has the maximum gain when the collector current is about 250µA, whereas, the

wn8 device has the maximum gain at the collector current is about 1mA.

This difference is due the emitter area of each device. The wn8 device is four times

bigger than the wn2, thus, its current is also scaled by the same factor.

Figure A.12: Current gain vs. collector current of the wn2 device


Figure A.13: Current gain vs. collector current of the wn8 device

We do the same experiment for the wp2 device, and get the following result:

Figure A.14: Current gain vs. collector current of the wp2 device

As we can notice from the figure, the gain of the pnp device is much less than the one of

its npn counterpart. Its gain is only in the order of 20.


AC Characteristics

In this part of the experiment we will create a Bode plot and determine the fT of the

transistor.

In the circuit in Figure A.10, change the characteristics of V1 so that the dc value is

veb and the ac value is equal to 1. Change the value of B1 so that V=2. Change the

analysis type to ac to perform a logarithmic frequency sweep from 1 kHz to 10 GHz with 100

points/decade. Change the .step directive so that the param is veb and the values range

from -0.6 to -0.9 in step of -0.1 V.

Figure A.15: Circuit to measure the frequency response of transistor

Create a Bode plot of β (IC/IB) vs. frequency, using a logarithmic scale for the y-axis.

The frequency where the gain characteristic intersects the x-axis, i.e. where the gain is equal

to 1, is called the unity-gain frequency fT. Use the cursor to find fT. By using the up/down

arrows you can make the cursor move to a different curve in the family of curves.

AC 1

V1

veb

B1

2

U1

wn2

.step param veb -0.6 -0.9 -0.1

.ac dec 100 1k 10G

HIEU NGUYEN & THIEN NGUYEN

01/29/2010


Figure A.16: Bode plot of β (IC/IB) vs. frequency of wn2 device

Figure A.17: Bode plot of β (IC/IB) vs. frequency of wn8 device


Figure A.18: Bode plot of β (IC/IB) vs. frequency of wp2 device

Notice that the unity-gain frequency is a strong function of the dc operating point of the

device. The curve of fT versus IC is of interest and we’ll now describe a method to generate

that characteristic.

Table A.1: Unity cut-off frequency (fT) of CPI transistors vs. VBE

|VBE| wn2 wn8 wp2

0.6V 36.4482MHz 35.4813MHz 12.128MHz

0.7V 1.20226GHz 1.21499GHz 420.842MHz

0.8V 7.58578GHz 7.67161GHz 3.83176GHz

0.9V 6.60693GHz 6.34837GHz 3.89045GHz


2) Gain block characteristics

The gain block that we design in part 3 of the project is a kind of operational amplifier. We

now verify some of the common characteristics of operational amplifiers for our gain block.

1. Peak output voltage vs. load impedance

Use the following circuit to find the peak output voltage of the gain block when the load

impedance changes. As we know, the op amp can only work properly when the load

impedance is bigger than a certain value.

Figure B.1: Circuit to find the peak output voltage vs. load impedance

Figure B.2: Maximum positive peak output voltage vs. load resistance


Figure B.3: Maximum negative peak output voltage vs. load resistance

As we can see from Figure B.2 and Figure B.1, the output voltage of the gain block only

reaches its maximum value when the load impedance is large than about 3kΩ.

The maximum of output voltage (no-load condition) can be found from the transfer

characteristics (Figure II.4.2).

Positive peak output voltage: 2.70686V

Negative peak output voltage: -2.53595V

2. Common-mode rejection ratio

In Figure III.4.5, we examine the open-loop gain of the gain block vs. frequency. It is the

differential mode gain. We now figure out the common mode gain Ac. The common-mode-

rejection-ratio (CMRR) is defined as

𝐶𝑀𝑅𝑅 = 𝐴𝑑

𝐴𝑐

The circuit used for examining the common mode gain is shown in Figure B.4.


Figure B.4: Circuit to find the common mode gain vs. frequency

Figure B.5: Open-loop common voltage amplification vs. frequency

The common mode signal is suppressed by -26.5dB.

Next, we find the CMRR as a function of frequency, by the circuit shown in Figure B.6.


Figure B.6: Circuit to find the CMRR vs. frequency

Figure B.7: Common mode rejection ratio vs. frequency

The normal value of CMRR is 83dB. As the frequency goes up, the CMRR drops down

significantly. However, this gain block works properly at the frequency range of 1Mhz that

we desire.


3. Output resistance

Now, we will find the output resistance as a function of frequency.

Figure B.8: Circuit to find the output resistance vs. frequency

Figure B.9: Output resistance vs. frequency

The normal output impedance of the gain block is 39.4579Ω. As the frequency goes up,

the output impedance goes down.


4. Input resistance

We use the circuit below to find the input resistance as a function of frequency.

Figure B.10: Circuit to find the input resistance vs. frequency (inverting input)

Figure B.11: Input impedance vs. frequency (Inverting input)

Rin = 14.8971KΩ (Inverting)

The input impedance at the non-inverting input drops down significantly at the frequency

of 1MHz.


Figure B.12: Circuit to find the input resistance vs. frequency (non-inverting input)

Figure B.13: Input impedance vs. frequency (Non-inverting input)

Rin = 116.045KΩ (non-inverting)

The input impedance at the non-inverting input is much higher than the inverting one.

Moreover, the frequency response of the non-inverting input is also better than the inverting.

Therefore, we will use the non-inverting input for our circuit.


5. Input bias current and offset current

To find the bias current, we perform a DC operation point simulation with the two inputs

of the gain block grounded.

Figure B.14: Circuit to find the input bias and offset current

The operation point of the circuit in Figure B.14 is shown in Figure B.15.

Figure B.15: DC operating point of the circuit in Figure B.14


Input bias current:

𝐼𝐵𝐼𝐴𝑆 =𝐼+ + 𝐼−2

=2.09812+ 2.10425

2= 2.101185𝜇𝐴

Input offset current:

𝐼𝑂𝑆 = 𝐼+ − 𝐼− = 2.09812− 2.10425 = 6.18𝑛𝐴

All of the characteristics of the gain block are summarized in Table III.4.2.

A complete equivalent circuit for our gain block is shown in Figure B.16.

Figure B.16: Complete circuit of the op-amp


Figure B.17-Complete schematic of the gain block

a. Bias point

The first thing that we simulate is the bias point of the circuit. Grounding the two inputs

of the gain block and using the .op directive, we get the following result.


Table B.1: Collector current of transistors in the gain block

Differential pair Output buffer

Q1 275.4µA Q5 283.2 µA

Q2 255.4 µA Q6 1.08mA

Active load Bias circuit

Q3 252.7 µA Q7 236.4 µA Q9 277.4 µA

Q4 257.6 µA Q8 535.0 µA Q10 1.09mA

Transfer characteristics

From this characteristic, we can figure out the actual offset voltage, the DC open-loop

gain, and the swing of the output.

Figure B.18: Circuit to measure the transfer characteristics of the gain block


The result from this measurement is shown in the Figure III.4.2.

Figure B.19: Transfer characteristic of the gain block

From this characteristic, we can get some value:

Positive peak output voltage: 2.70686V

Negative peak output voltage: -2.53595V

DC open-loop gain: Av = 2.5𝑉−(−2𝑉)

3.79𝑚𝑉 −(−3.01𝑚𝑉 )=661.8 V/V

The input offset voltage cannot be seen in the above figure, so we need a magnified

version of this. By changing the Spice directive to: .dc Vin -50uV 50uV 0.01uV, we get

the result as shown in Figure B.20.


Figure B.20: Magnified characteristics from -50uV to 50uV to find the offset voltage

From this figure, we find out that the input offset voltage is: VOS = 37.42µV.

This value is the value of the input voltage that makes the output zero.

Next, we examine the frequency response of the gain block.

Figure B.21: Circuit to examine the frequency response


The frequency response of the gain block is:

Figure B.22: Frequency response of the gain block

From the frequency response, we get the following value:

-3dB cut-off frequency: fβ = 9.14534MHz

Unity frequency (gain bandwidth product): fT = GBW = 1.61585GHz

(this is done by extending the frequency range to 1Hz to 10GHz)

Table B.2: Characteristics of the gain block

Parameter name Value Unit

Differential open-loop gain 56.4768 dB

CMRR 83 dB

Input impedance

(non-inverting)

116.045 KΩ

Input impedance

(inverting)

14.8971 KΩ

Output impedance 39.4579 Ω


-3dB cut-off frequency 9.14534 MHz

Gain-bandwidth product 1.61585 GHz

Peak positive voltage 2.67577 V

Peak negative voltage -2.50196 V

Input bias current 2.101185 𝜇𝐴

Input offset current 6.18 𝑛𝐴

Input offset voltage 37.42 µV


3) Fully differential topology

The topology that we implement in the main project has a single-ended input to the VCO.

Another to do this is by using a fully differential topology as shown in Figure A3.1.

The loop filter block and the low pass filter are duplicated to handle the differential signal

separately. This topology has an advantage that is the offset voltage in the output is reduced

because the common signal is rejected by the differential stages. Also, the circuit is more

symmetrical, thus the distortion tends to be reduced by the circuit.

The output waveform of the demodulator is plotted for some input frequency combinations.


Figure C.1 – Fully differential PLL based FM demodulator

One thing about the above circuit is that a small capacitor (3pF) is added at the output to

create a cut-off frequency at a very high frequency (≈5MHz) to attenuate any remaining noise

that disturbs the output waveform (making the waveform not very “clean”).

Figure C.2 – Input and output waveform when Vi is a 50kHz sine wave


Figure C.3 – Input and output waveform

when Vi = 0.3*(sin(100k*pi*time)+sin(75k*pi*time)+sin(10k*pi*time)+sin(50k*pi*time))

As we can see from the two above waveforms, despite some attenuation (the amplitude is not

exactly the same between input and output), the relationship is quite linear. The amount of

distortion and offset is quite small.

However, the amount of circuitry is significantly increases when we are using the fully

differential topology. In addition, to implement this topology, the two outputs of the phase

detector must be brought to exactly zero offset level. Otherwise, a small amount of offset can

cause the loop filter to be saturated at the rail voltage (remember that the loop filter has a very

high gain at low frequency).

Therefore, the design of this topology becomes very time-consuming with a lot of trial-and-

error effort. This topology is also very sensitive to mismatching and supply voltage variation.

Any change in these factors can make the whole circuit saturated.

In conclusion, this fully – differential circuit is only needed in some special cases when the

requirements are very high and we cannot meet these requirements by the single-ended topology.


4) NE564 circuit description

In the lab section accompanying with this project, we actually build a PLL based on a

commercial integrated PLL – NE564. The Appendix 5 of this project shows some of the results

that we get from the physical circuit.

To make it easy to compare the design of our group with CPI devices and the actual PLL, we

will now describe some of the basic blocks of the NE564 PLL.

This PLL also have basically the same blocks as our designed PLL, that are: the phase

detector, the VCO. In addition, the NE564 has a limiter amplifier at the input stage to “square”

the input signal before feeding to the phase detector; a post-detection processing stage to recover

the modulated signal.

However, it does not have the loop filter, and also does not support active loop filter. The

only thing we can do is to build a passive loop filter around the circuit. The block diagram of the

NE564 is shown in Figure 1. Each of the stage will be discussed in the following.

Figure 1 - Block diagram of the NE564 PLL

1. Limiter amplifier

The limiter amplifier produces a near constant amplitude output (squared wave) that serves

as the input for the phase detector.


Signal limiting is accomplished in the NE564 with a differential amplifier whose output is

clipped by diodes D1 and D2. When limiting, the DC voltage across R2 R3 remains at the diode

voltage.

Transistor Q4 is configured as current mirror source whose reference voltage is VBIAS.

Figure 2 - Limiter amplifier NE564

2. Phase detector

The phase detector block of the NE564 is shown in Figure 3. It is basically a double-balanced

mixer commonly used in PLL circuits.

The transconductance, 𝑔𝑚 , for the Q13 - Q14 differential amplifier is directly proportional to

the mirror current in Q15. Thus, by externally sinking or sourcing current at Pin 2, 𝑔𝑚 can be

changed to alter the phase comparator’s conversion gain, 𝐾𝑑 .

𝐾𝑑 ≅ 0.66 𝑉

𝑟𝑎𝑑 + 9.2 × 10−4

𝑉

𝑟𝑎𝑑 × 𝜇𝐴 × 𝐼𝐵𝑖𝑎𝑠 (𝜇𝐴)

Currents through R12 and R13 set the common-mode output voltage from the phase

comparator. Since this common-mode voltage is applied to the VCO to establish its quiescent

currents, the VCO conversion gain (𝐾𝑜 ) also depends upon the bias current at Pin 2.


Figure 3 - Phase detector of NE564

3. VCO

The VCO is of the basic emitter-coupled astable type. The basic oscillator in Figure 4

consists of Q19, Q20, Q21 and Q23 with current sinks of Q25 and Q26. The master current sink

of Q28 keeps the total current constant by altering the ratio of currents in Q25 - Q26 and the

dummy current sink of Q27.

The input drive voltage for the VCO is made up of common-mode and difference-mode

components from the phase comparator. The VCO control voltage is applied differentially to the

base of Q27 and to the common bases of Q25 and Q26.


Figure III - VCO block of NE564

From the short description of the NE564, which is a commercial integrated PLL, we can see

that this is basically the same topology that we built for our project. Therefore, it is useful to

verify the operation of our PLL with the NE564. The result from implementing the physical

circuit will then be presented in the next section.


5) Lab experiment results

a. Results from lab#1

The output waveforms on the scope

Output waveform when Vcar=20mV, 10KHz, and Vsig=1V, 200KHz


Figure: Output waveform when Vcar=1V, 10KHz, and Vsig=1V, 200KHz

Output waveform when Vcar=1V, 35KHz, and Vsig=1V, 10KHz

b. Results from lab#2

With a 10 MHz sine wave and a 100MHz Nyquist rate you should see a big spike about 10 %

of the way from the left side of the screen.


Change the signal to a square wave and explain the changes in the spectrum.


Connect the differential output of your AM generator to the scope; adjust the scope settings

(vertical and sampling rate) to match the AM signal requirements and measure and record the

FFT of your AM signal.

Vcar = 20mV (small signal)


Vcar=1V (large signal)


c. Results from lab#3


Plot the average phase detector output as a function of the phase angle difference

We have the table:

∆𝜑(°) 0 30 60 90 120 150 180 210 240 270 300 330 360

Vout(V) -1 -.621 -.304 .012 .347 .679 1 .679 .347 .012 -.304 -.621 -1

-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

0 30 60 90 120 150 180 210 240 270 300 330 360

Output voltage (V)

∆𝜑(°)


d. Results from lab#4

Use the function generator to sweep the input frequency up and down and record the

acquisition range and the lock range.

Free running frequency


The acquisition range is 713.7KHZ – 1311KHz

The clock range is 929.4KHz – 1043KHz


e. Results from lab#5

Observe and record all waveforms in this experiment.

When we inject the sinusoidal waveform, we get the following result:

When we inject the modulated sinusoidal waveform, we get the following result:


f. Results from lab#6

fm demod pll

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